ST L6740L User Manual
Hybrid controller (4+1) for AMD SVID and PVID processors
Features
■ Hybrid controller: compatible with PVI and SVI
CPUs
■ Dual controller: 2 to 4 scalable phases for CPU
CORE, 1 phase for NB
■ Dual-edge asynchronous architecture with
LTB Technology
PSI management to increase efficiency in
■
light-load conditions
■ Dual over-current protection:
Average and per-phase
■ Load indicator (CORE section)
■ Logic level support for LVDDRIII
■ Voltage positioning
■ Dual remote sense
■ Adjustable independent reference offset
■ Feedback disconnection protection
■ Programmable OV protection
■ Oscillator internally fixed at 150 kHz externally
adjustable
■ LSLess startup to manage pre-biased output
■ Flexible driver support
■ HTQFP48 package
Applications
■ Hybrid high-current VRM, VRD for desktop,
server, workstation, IPC CPUs supporting PVI
and SVI interface
■ High-density DC / DC converters
tm
L6740L
HTQFP48
Description
L6740L is a hybrid CPU power supply controller
compatible with both parallel (PVI) and serial
(SVI) protocols for AMD processors.
The device embeds two independent control
loops for the CPU core and the integrated NB,
each one with its own set of protections. L6740L
is able to work in single-plane mode, addressing
only the CORE section, according to the parallel
DAC codification. When in dual-plane mode, it is
compatible with the AMD SVI specification
addressing the CPU and NB voltages according
to the SVI bus commands.
The dual-edge asynchronous architecture is optimized by LTB Technology
transient response minimizing the output capacitor and reducing the total BOM cost.
PSI management allows the device to selectively
turn-off phases when the CPU is in low-power
states increasing the over-all efficiency.
Fast protection against load over current is provided for both the sections. Furthermore,
feedback disconnection protection prevents from
damaging the load in case of disconnections in
the system board.
tm
allowing fast load-
Table 1. Device summary
Order codes Package Packaging
L6740L HTQFP48 Tube
L6740LTR HTQFP48 Tape and reel
September 2008 Rev 3 1/44
www.st.com
1
Contents L6740L
Contents
1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4
1.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 Device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5 Hybrid CPU support and CPU_TYPE detection . . . . . . . . . . . . . . . . . . 16
5.1 PVI - parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 PVI start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3 SVI - serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.4 SVI start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.4.1 Set VID command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.4.2 PWROK de-assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.4.3 PSI_L and efficiency optimization at light-load . . . . . . . . . . . . . . . . . . . 21
5.4.4 HiZ management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.4.5 Hardware jumper override - V_FIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6 Output voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1 CORE section - phase # programming . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2 CORE section - current reading and current sharing loop . . . . . . . . . . . . 24
6.3 CORE section - load-line and load-indicator (optional) . . . . . . . . . . . . . . 25
6.4 CORE section - offset (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.5 NB section - current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.6 NB section - load-line and load-indicator (optional) . . . . . . . . . . . . . . . . . 27
6.7 NB section - offset (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/44
L6740L Contents
6.8 NB section - maximum duty-cycle limitation . . . . . . . . . . . . . . . . . . . . . . . 28
6.9 On-the-fly VID transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.10 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.10.1 LS-Less start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7 Output voltage monitoring and protections . . . . . . . . . . . . . . . . . . . . . 31
7.1 Programmable overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.2 Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.3 PWRGOOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.4 Over-current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.4.1 CORE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.4.2 NB section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9 System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.1 Compensation network guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10 LTB Technology™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
11.1 Power components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
11.2 Small signal components and connections . . . . . . . . . . . . . . . . . . . . . . . 41
12 TQFP48 mechanical data and package dimensions . . . . . . . . . . . . . . 42
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3/44
Typical application circuit and block diagram L6740L
1 Typical application circuit and block diagram
1.1 Application circuit
Figure 1. Typical 4+1 application circuit
PVI / SVID Bus
R
OVP
R
OSC
R
LTBG
R
C
DEC
PVCC*
VCC
PWM
EN*
GND
PWM
EN*
GND
PWM
EN*
GND
VCC
VCC
BOOT
UGATE
PHASE
L6741/3
LGATE
PVCC*
BOOT
UGATE
PHASE
L6741/3
LGATE
PVCC*
BOOT
UGATE
PHASE
L6741/3
LGATE
HS1
HS2
HS3
C
LS1
C
LS2
C
LS3
1
GND2 VCC
PWRGOOD
41
PWROK
37
EN
38
VID0
35
VID1
36
VID2/SVD
40
VID3/SVC
39
VID4
25
VID5
26
OVP / V_FIX
10
OSC / FLT
27
OS
8
NB_OS
29
LTB_GAIN
11
PSI_L
12
COMP
3
C
F
R
F
DROOP
5
FB
4
LTB
9
C
LTB
FB
34
R
LTB
NB_COMP
C
F_NBRF_NB
ST L6740L
Hybrid PVID / SVID Controller (**)
NB_DROOP
NB_FB
32
33
PWM1
PWM2
PWM3
PWM4
NB_PWM
OC_PHASE
OC_AVG / LI
CS1+
CS1-
CS2+
CS2-
CS3+
CS3-
CS4+
CS4-
NB_ISEN
FBG
VSEN
NB_VSEN
NB_FBG
ENDRV
NB_ENDRV
R
FB_NB
48
47
46
45
44
R
OC_TH
21
R
OC_AVG
28
13
14
R
G
15
16
R
G
17
18
R
G
19
20
R
G
23
R
ISEN
7
6
31
30
43
42
C
DEC
C
DEC
C
BULK_IN
HF
L1
R
C
HF
L2
R
C
HF
L3
R
V
L
IN
IN
C
DEC_NB
C
BULK_NB
C
HF_NB
HS
NB
L
NB
LS
NB
BOOT
UGATE
PHASE
LGATE
VCC
PVCC*
PWM
EN*
L6741/3
GND
PVI / SVID AM2 CPU
C
OUT_NBCMLCC_NB
(*) PVCC Only applies to L6741; EN Only applies to L6743. See related DS for further details
(**) Pin not listed to be considered as Not Connected
ST L6740L (4+1) Reference Schematic
NB
SVID / PVID Interface
4/44
CORE
C
C
DEC
VCC
PVCC*
PWM
EN*
GND
BOOT
UGATE
PHASE
L6741/3
LGATE
C
MLCC
C
OUT
HS4
HF
C
L4
LS4
R
C
L6740L Typical application circuit and block diagram
Figure 2. Typical 3+1 application circuit
PVI / SVID Bus
R
OVP
R
OSC
R
LTBG
R
C
DEC
PVCC*
VCC
PWM
EN*
GND
PWM
EN*
GND
PWM
EN*
GND
VCC
VCC
BOOT
UGATE
PHASE
L6741/3
LGATE
PVCC*
BOOT
UGATE
PHASE
L6741/3
LGATE
PVCC*
BOOT
UGATE
PHASE
L6741/3
LGATE
HS1
LS1
HS2
LS2
HS3
LS3
C
C
C
1
GND2 VCC
PWRGOOD
41
PWROK
37
EN
38
VID0
35
VID1
36
VID2/SVD
40
VID3/SVC
39
VID4
25
VID5
26
OVP / V_FIX
10
OSC / FLT
27
OS
8
NB_OS
29
LTB_GAIN
11
PSI_L
12
COMP
3
C
F
R
F
DROOP
5
FB
4
LTB
9
C
LTB
FB
34
R
LTB
NB_COMP
C
F_NBRF_NB
ST L6740L
Hybrid PVID / SVID Controller (**)
NB_DROOP
NB_FB
32
33
PWM1
PWM2
PWM3
PWM4
NB_PWM
OC_PHASE
OC_AVG / LI
CS1+
CS1-
CS2+
CS2-
CS3+
CS3-
CS4+
CS4-
NB_ISEN
FBG
VSEN
NB_VSEN
NB_FBG
ENDRV
NB_ENDRV
R
FB_NB
48
47
46
45
44
21
R
OC_TH
28
R
OC_AVG
13
14
R
G
15
16
R
G
17
18
R
G
19
20
R
G
23
R
ISEN
7
6
31
C
DEC
30
43
42
C
DEC
C
BULK_IN
HF
L1
R
C
HF
L2
R
C
HF
L3
R
V
L
IN
IN
C
DEC_NB
C
BULK_NB
C
HF_NB
HS
NB
L
NB
LS
NB
C
OUT_NBCMLCC_NB
(*) PVCC Only applies to L6741; EN Only applies to L6743. See related DS for further details
(**) Pin not listed to be considered as Not Connected
BOOT
UGATE
PHASE
LGATE
VCC
PVCC*
PWM
EN*
L6741/3
GND
ST L6740L (3+1) Reference Schematic
PVI / SVID AM2 CPU
NB
SVID / PVID Interface
CORE
C
C
MLCC
C
OUT
5/44
Typical application circuit and block diagram L6740L
Figure 3. Typical 2+1 application circuit
PVI / SVID Bus
R
OVP
R
OSC
R
LTBG
R
C
DEC
PVCC*
VCC
PWM
EN*
GND
PWM
EN*
GND
VCC
BOOT
UGATE
PHASE
L6741/3
LGATE
PVCC*
BOOT
UGATE
PHASE
L6741/3
LGATE
HS1
LS1
HS2
LS2
C
C
1
GND2 VCC
PWRGOOD
41
PWROK
37
EN
38
VID0
35
VID1
36
VID2/SVD
40
VID3/SVC
39
VID4
25
VID5
26
OVP / V_FIX
10
OSC / FLT
27
OS
8
NB_OS
29
LTB_GAIN
11
PSI_L
12
COMP
3
C
F
R
F
DROOP
5
FB
4
LTB
9
C
LTB
FB
NB_COMP
34
R
LTB
C
F_NBRF_NB
OC_AVG / LI
ST L6740L
Hybrid PVID / SVID Controller (**)
NB_ENDRV
NB_DROOP
NB_FB
32
33
PWM1
PWM2
PWM3
PWM4
NB_PWM
OC_PHASE
CS1+
CS1-
CS2+
CS2-
CS3+
CS3-
CS4+
CS4-
NB_ISEN
FBG
VSEN
NB_VSEN
NB_FBG
ENDRV
R
FB_NB
48
47
46
45
44
21
R
OC_TH
R
OC_AVG
28
13
14
R
G
15
16
R
G
17
18
R
G
19
20
R
G
23
R
ISEN
7
6
31
C
DEC
30
43
42
C
BULK_IN
HF
L1
R
C
HF
L2
R
C
V
L
IN
IN
C
DEC_NB
C
BULK_NB
C
HF_NB
HS
NB
L
NB
LS
NB
BOOT
UGATE
PHASE
LGATE
VCC
PVCC*
PWM
EN*
L6741/3
GND
PVI / SVID AM2 CPU
C
OUT_NBCMLCC_NB
(*) PVCC Only applies to L6741; EN Only applies to L6743. See related DS for further details
(**) Pin not listed to be considered as Not Connected
NB
SVID / PVID Interface
ST L6740L (2+1) Reference Schematic
6/44
CORE
C
MLCC
C
OUT
L6740L Typical application circuit and block diagram
1.2 Block diagram
Figure 4. Block diagram
VID4
V_FIX / OVP
OC_PHASE
VID0
VID2 / SVD
VID1
VID5ENPWROK
VID3 / SVC
PWRGOOD
PSI_L
OC_AVG / LI
LT B
LTB_GAIN
NB_ISEN
NB_PWM
CS1+
CS1-
CS2+
CS2-
CS3+
CS3-
CS4+
CS4-
PWM1
PWM2
PWM3
PWM4
OSC
VCC
SGND
PWM1
PWM2
PWM3
PWM4
DIFFERENTIAL
CURRENT SENSE
Σ
Σ
Σ
Σ
OSC
VCC
SGND
AMD SVI / PVI FLEXIBLE
11 μA
CURRENT
BALANCE
1.24V
OFFSET
INTERFACE
CORE_REF
& NB_REF
ENDRV
NB_ENDRV
OSC
DUAL CHANNEL
OSCILLATOR (4+1)
CORE - TOT CURRENT
I
OS
ERROR
AMPLIFIER
DROOP
I
L6740L
CONTROL LOGIC
OUTPUT VOLTAGE
MONITOR AND PROTECTION
MANAGEMENT
CS1-
I
I
OS
DROOP
64k
BUFFER
30μA
I
64k
NB CURR
SENSE
NB_DROOP
50μA +I
NB_OS
I
NB - TOT CURRENT
NB_OS
I
NB_OS
64k
64kREMOTE
VCORE_REF
(from SVI/PVI decoding)
NB_PWM
64k64k
NB_REF
1.24V
ERROR
AMPLIFIER
BUFFER
REMOTE
64k
64k
ENDRV
NB_ENDRV
OFFSET
NB_OS
NB_COMP
NB_FB
NB_DROOP
NB_FBG
NB_VSEN
ENDRV
NB_ENDRV
OS
COMP
FB
DROOP
FBG
VSEN
7/44
Pins description and connection diagrams L6740L
2 Pins description and connection diagrams
Figure 5. Pins connection (top view)
VID1
VID0
NB_COMP
NB_FB
NB_DROOP
NB_VSEN
NB_FBG
NB_OS
OC_AVG / LI
OSC / FLT
VID5
VID4
36 35 34 33 32 31 30 29 28 27 26 25
PWROK
EN
SVC
SVD
PWRGOOD
NB_ENDRV
ENDRV
NB_PWM
PWM4
PWM3
PWM2
PWM1
37
38
39
40
41
42
43
44
45
46
47
48
123456789101112
L6740L
24
23
22
21
20
19
18
17
16
15
14
13
N.C.
NB_ISEN
N.C.
OC_PHASE
CS4-
CS4+
CS3-
CS3+
CS2-
CS2+
CS1-
CS1+
2.1 Pin descriptions
Table 2. Pin description
Pin# Name Function
1VCC
2SGND
3
4FB
5DROOP
COMP
Core section
VCC
GND
COMP
FB
DROOP
VSEN
FBG
OS
LTB
LTB_GAIN
OVP/V_FIX
PSI_L
Device power supply.
Operative voltage is 12V ±15%. Filter with 1μF MLCC to SGND.
All the internal references are referred to this pin. Connect to the PCB
signal ground.
Error amplifier output.
Connect with an R
- CF to FB. The CORE section or the device cannot
F
be disabled by grounding this pin.
Error amplifier inverting input.
Connect with a resistor R
to VSEN and with an RF - CF to COMP.
FB
Offset current programmed by OS is sunk through this pin.
A current proportional to the total current read is sourced from this pin
according to the current reading gain.
Short to FB to implement droop function, if not used, short to SGND.
Output voltage monitor.
6 VSEN
It manages OVP and UVP protections and PWRGOOD. Connect to the
positive side of the load for remote sensing. See Section 7 for details.
8/44
L6740L Pins description and connection diagrams
Table 2. Pin description (continued)
Pin# Name Function
Remote ground sense.
7
8OS
Core section
9LTB
10 OVP / V_FIX
11
Core
12 PSI_L
13
LT B_ GA IN
section
FBG
CS1+
Connect to the negative side of the load for remote sensing. See
Section 9 for proper layout of this connection.
Offset programming pin.
Internally set to 1.24 V. Connecting a R
resistor to SGND allows to
OS
set a current that is mirrored into FB pin in order to program a positive
offset according to the selected R
FB
.
Short to SGND to disable the function. See Section 6.4 for details.
TM
LTB Te c h n o lo g y
Connect through an R
input pin.
- C
LT B
network to the regulated voltage
LT B
(CORE section) to detect load transient. See Section 10 for details.
OVP. Overvoltage programming pin. Internally pulled-up to 3.3 V by
11 μA. Connect to SGND through a R
(typ) to set a fixed voltage according to the R
resistor and filter with 10 nF
OVP
resistor. If floating it
OVP
will program 3.3 V threshold. See Section 7 for details.
V_FIX - Hardware override. Short to SGND to enter VFIX mode
(WARNING: this condition overrides any code programmed on the VIDx
lines). In this case, the device will use SVI inputs as static VIDs and
OVP threshold will be set to 1.8 V. See Section 5.4.5 for details.
TM
LTB Te c h n o lo g y
Connect to SGND through a resistor R
gain pin.
to program the LTB
LTBGAIN
Gain. See Section 10 for details.
Power saving indicator (SVI mode).
Open-drain input/output pin. See Section 5.4.3 for details.
Channel 1 current sense positive Input. Connect through an R-C filter to
the phase-side of the channel 1 inductor.
See Section 9 for proper layout of this connection.
14 CS1-
15 CS2+
16 CS2-
Core section
17 CS3+
18 CS3-
Channel 1 current sense negative input. Connect through a R
resistor
G
to the output-side of the channel inductor.
See Section 9 for proper layout of this connection.
Channel 2 current sense positive input. Connect through an R-C filter to
the phase-side of the channel 2 inductor.
See Section 9 for proper layout of this connection.
Channel 2 current sense negative input. Connect through a R
resistor
G
to the output-side of the channel inductor.
See Section 9 for proper layout of this connection.
Channel 3 current sense positive input. Connect through an R-C filter to
the phase-side of the channel 3 inductor. When working at 2 phase,
directly connect to V
out_CORE
.
See Section 9 for proper layout of this connection.
Channel 3 current sense negative input. Connect through a R
resistor
G
to the output-side of the channel inductor. When working at 2 phase,
connect through R
to CS3+.
G
See Section 9 for proper layout of this connection.
9/44
Pins description and connection diagrams L6740L
Table 2. Pin description (continued)
Pin# Name Function
Channel 4 current sense positive input. Connect through an R-C filter to
19
CS4+
20 CS4-
Core section
21 OC_PHASE
22 NC Not internally connected.
NB
NB_ISEN
section
23
24 NC Not internally connected.
25,
26
PVI
VID4, VID5
interface
27 OSC / FLT
28
OC_AVG /
LI
Core section
29
NB_OS
NB section
30 NB_FBG
the phase-side of the channel 4 inductor. When working at 2 or 3
phase, directly connect to V
out_CORE
.
See Section 9 for proper layout of this connection.
Channel 4 current sense negative input. Connect through a R
resistor
G
to the output-side of the channel inductor. When working at 2 or 3
phase, connect through R
to CS4+.
G
See Section 9 for proper layout of this connection.
Per-phase over-current (CORE section).
Internally set to 1.24 V, connecting to SGND with a resistor R
OC_TH
it
programs the OC threshold per-phase. See Section 7.4.1 for details.
NB current sense pin.
Used for NB voltage positioning and NB_OCP. Connect through a
resistor R
to the relative LS Drain. See Section 7.4 for details.
ISEN
Voltage IDentification pins.
Internally pulled-low by 10 μA, they are used to program the output
voltage. Used only in PVI-mode, ignored when in SVI-mode.
See Section 5 for details.
OSC: It allows programming the switching frequency F
of both
SW
sections. Switching frequency can be increased according to the
resistor R
connected from the pin to. SGND with a gain of
OSC
6.8 kHz/µA (see Section 8 for details). If floating, the switching
frequency is 150 kHz per phase.
FLT: The pin is forced high (3.3 V) in case of an OV / UV fault. To
recover from this condition, cycle VCC or the EN pin. See Section 7 for
details.
Average over-current and load indicator pin.
A current proportional to the current delivered by the CORE section (a
copy of the DROOP current) is sourced through this pin.
The average-OC threshold is programmed by connecting a resistor
R
threshold (V
to SGND. When the generated voltage crosses the OC_AVG
OC_AVG
OC_AVGTH
= 2.5 V Typ) the device latches with all mosfets
OFF (to recover, cycle VCC or the EN pin).
A load indicator with 2.5 V end-of-scale is then implemented.
See Section 7.4.1 for details.
Offset programming pin.
Internally set to 1.24 V, connecting a R
resistor to SGND allows
OS_NB
setting a current that is mirrored into NB_FB pin in order to program a
positive offset according to the selected R
. Short to SGND to
FB_NB
disable the function. See Section 6.7 for details.
Remote ground sense.
Connect to the negative side of the load to perform remote sense. See
Section 9 for proper layout of this connection.
10/44
L6740L Pins description and connection diagrams
Table 2. Pin description (continued)
Pin# Name Function
NB output voltage monitor.
31
NB_VSEN
32 NB_DROOP
It manages OVP and UVP protections and PWRGOOD. Connect to the
positive side of the NB load to perform remote sensing. See Section 9
for proper layout of this connection.
A current proportional to the total current read by the NB section is
sourced through this pin according to the current reading gain (R
ISEN
).
Short to NB_FB to implement Droop Function or connect to SGND
through a resistor and filter with 1nF capacitor to implement NB LOAD
Indicator. If not used, short to SGND.
NB section
33 NB_FB
34 NB_COMP
35,
36
37 PWROK
VID0, VID1
SVI / PVI interface
38 EN
39
SVC / VID3
NB error amplifier inverting input.
Connect with a resistor R
to NB_VSEN and with an R
FB_NB
F_NB
- C
F_NB
to NB_COMP. Offset current programmed by NB_OS is sunk through
this pin.
Error amplifier output.
Connect with an R
F_NB
- C
to NB_FB. The NB section or the device
F_NB
cannot be disabled by grounding this pin.
Voltage IDentification pins.
Internally pulled-low by 10 μA, they are used to program the output
voltage. VID1 is monitored on the EN pin rising-edge to define the
operative mode of the controller (SVI or PVI). When in SVI mode, VID0
is ignored. See Section 5 for details.
System-wide Power Good input (SVI mode).
Internally pulled-low by 10 μA. When low, the device will decode the two
SVI bits (SVC, SVD) to determine the Pre-PWROK Metal VID (default
condition when pin is floating).
When high, the device will actively run the SVI protocol.
Pre-PWROK Metal VID are latched after EN is asserted and re-used in
case of PWROK de-assertion. Latch is reset by VCC or EN cycle.
VR Enable. Internally pulled-up to 3.3 V by 10 μA.
Pull-low to disable the device. When set free, the device immediately
checks for the VID1 status to determine the SVI / PVI protocol to be
adopted and configures itself accordingly. See Section 5 for details.
Voltage IDentification pin - SVI clock pin.
Internally pulled-low by 10 μA, it is used to program the output voltage.
When in SVI-mode, it is considered as Serial-VID-data (input / open
drain output). See Section 5 for details.
40 SVD / VID2
SVI / PVI interface
41 PWRGOOD
Voltage IDentification pins - SVI data pin.
Internally pulled-low by 10 μA, it is used to program the output voltage.
When in SVI-mode, it is considered as Serial-VID-data (input / open
drain output). See Section 5 for details.
VCORE and NB Power Good.
It is an open-drain output set free after SS as long as both the voltage
planes are within specifications. Pull-up to 3.3V (typ) or lower, if not
used it can be left floating.
When in PVI mode, it monitors the CORE section only.
11/44
Pins description and connection diagrams L6740L
Table 2. Pin description (continued)
Pin# Name Function
External driver enable.
Open drain output used to control NB section external driver status:
42
43
44
45 to
48
NB
section
CORE
section
NB
section
CORE
section
Thermal pad
NB_ENDRV
ENDRV
NB_PWM
PWM1 to
PWM4
pulled-low to manage HiZ conditions or pulled-high to enable the driver.
Pull up to 3.3 V (typ) or lower.
When in PVI mode, NB section is always kept in HiZ.
External driver enable.
Open drain output used to control CORE section external driver status:
pulled-low to manage HiZ conditions or pulled-high to enable the driver.
Pull up to 3.3 V (typ) or lower.
PWM output.
Connect to external driver PWM input. The device is able to manage
HiZ status by setting the pin floating. When in PVI mode, NB section is
kept in HiZ. See Section 5.4.4 for details about HiZ management.
PWM outputs.
Connect to external drivers PWM inputs. The device is able to manage
HiZ status by setting the pins floating.
By shorting to SGND PWM4 or PWM3 and PWM4, it is possible to
program the CORE section to work at 3 or 2 phase respectively.
See Section 5.4.4 for details about HiZ management.
Thermal pad connects the silicon substrate and makes good thermal
contact with the PCB. Connect to the PGND plane.
2.2 Thermal data
Table 3. Thermal data
Symbol Parameter Value Unit
R
R
T
T
thJA
thJC
MAX
STG
T
J
Thermal resistance junction to ambient
(device soldered on 2s2p PC board)
Thermal resistance junction to case 1 °C/W
Maximum junction temperature 150 °C
Storage temperature range -40 to 150 °C
Junction temperature range 0 to 125 °C
40 °C/W
12/44
L6740L Electrical specifications
3 Electrical specifications
3.1 Absolute maximum ratings
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
V
CC
to PGND 15 V
All other pins to PGNDx -0.3 to 3.6 V
3.2 Electrical characteristics
Table 5. Electrical characteristics
(V
= 12 V ± 15%, TJ = 0 °C to 70 °C unless otherwise specified).
CC
Symbol Parameter Test conditions Min. Typ. Max. Unit
Supply current and power-ON
I
CC
UVLO
Oscillator
F
SW
ΔV
OSC
FAULT Voltage at pin OSC OVP, UVP latch active 3 3.6 V
d
MAX_NB
PVI / SVI interface
VCC supply current 20 mA
VCC turn-ON VCC rising 9 V
VCC
VCC turn-OFF VCC falling 7 V
Main oscillator accuracy 135 150 165 kHz
Oscillator adjustability R
PWM ramp amplitude CORE and NB section 2 V
NB duty-cycle limit
= 27 kΩ 380 465 550 kHz
OSC
I
NB_DROOP
I
NB_DROOP
= 0 μA80%
= 35 μA40%
Input high 2 V
EN,
PWROK
VID2,/SVD
VID3/SVC
SVD Voltage low (ACK) I
VID0 to
VID5
V_FIX Entering V_FIX mode 0.90 V
Input low 0.80 V
Pull-up current EN pin 10 μA
Pull-down current PWORK pin 10 μA
Input high (SVI mode) 0.95 V
Input low (SVI mode) 0.65 V
= -5 mA 250 mV
SINK
Input high (PVI mode) 1.3 V
Input low (PVI mode) 0.80 V
Pull-down current 10 μA
13/44
Electrical specifications L6740L
Table 5. Electrical characteristics (continued)
(V
= 12 V ± 15%, TJ = 0 °C to 70 °C unless otherwise specified).
CC
Symbol Parameter Test conditions Min. Typ. Max. Unit
PSI_L Voltage low I
= -5 mA 250 mV
SINK
Voltage positioning (CORE and NB section)
CORE
Output voltage accuracy
NB NBVSEN to V
OFFSET bias voltage I
OS, NB_OS
OFFSET current range 0 250 μA
VSEN to V
= 0 to 250 μA 1.190 1.24 1.290 V
OS
; FBG to GND
CORE
; NBFBG to GND
NB
CORE
-8 8 mV
-10 10 mV
FB
OFFSET - IFB accuracy IOS = 0 to 250 μA -15 15 %
DROOP
DROOP accuracy
NB_DROOP I
A
0
EA DC gain 100 dB
= 0 to 140 μA; OS = OFF -9 9 μA
I
DROOP
NB_DROOP
= 0 to 35 μA; OS = OFF -4 4 μA
SR Slew rate COMP, NB_COMP to SGND = 10pF 20 V/μs
PWM outputs (CORE and NB section)
PWMx,
NB_PWM
I
PWMx
ENDRV,
NB_ENDRV
Output high I = 1 mA 3 3.6 V
Output low I = -1 mA 0.2 V
Test current 10 μA
Output low I = -5 mA 0.4 V
Protections
V_FIX mode (V_FIX = SGND);
VSEN, NB_VSEN rising
= 180 kΩ 1.730 1.800 1.870 V
OVP
1.720 1.800 1.880 V
OVP
Overvoltage protection
Bias current 7 11 15 μA
OV programmability R
UVP Under voltage protection VSEN, NB_VSEN falling; wrt Ref. -470 -400 -330 mV
PGOOD threshold VSEN, NB_VSEN falling; wrt Ref -300 -250 -200 mV
PWRGOOD
Voltage low I
PWRGOOD
= -4 mA 0.4 V
Sourced from NB_VSEN; OS = OFF 50 μA
I
VSEN-DISC
V
FB-DISC
VSEN disconnection
FB disconnection
Sunk from VSEN; OS = OFF 30 μA
CORE - V
rising, above VSEN
CS-
500 600 700 mV
FBG DISC FBG disconnection EA NI input wrt VID 350 450 550 mV
OC_PHASE Per-phase OC CORE section; bias voltage 1.200 1.240 1.280 V
kV
OC_AVGTH
kI
OC_AVGTH
I
OCTH_NB
Average OC
OC threshold NB section 32 37.5 43 μA
CORE section 2.430 2.500 2.570 V
I
= 0 to 140 μA; OS = OFF -11 11 μA
DROOP
14/44
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