Features
■ Flexible power supply from 5 V to 12 V bus
■ Power conversion input as low as 1.5 V
■ Light-load efficiency optimization
■ Embedded bootstrap diode
■ VIN detector
■ 0.8 V internal reference
■ 0.5% output voltage accuracy
■ Remote GND recovery
■ High-current integrated drivers
■ Sensorless and programmable precise-OC
sense across Inductor DCR
■ OV protection
■ Programmable oscillator up to 600 kHz
■ LS-less to manage pre-bias startup
■ Adjustable output voltage
■ Disable function
■ Internal soft-start
■ VFQFPN 16 3x3 mm package
Applications
■ Memory and termination supply
■ Subsystem power supply (MCH, IOCH, PCI)
■ CPU and DSP power supply
■ Distributed power supply
■ General DC-DC converter
L6738A
Single-phase PWM controller
with light-load efficiency optimization
VFQFPN16
and the device supply voltage ranging from 5 V to
12 V bus.
The L6738A features a proprietary algorithm that
allows Light-Load efficiency optimization,
boosting efficiency without compromising the
output voltage ripple.
The integrated 0.8 V reference allows generation
of output voltages with ±0.5% accuracy over line
and temperature variations.
The oscillator is programmable up to 600 kHz.
The L6738A provides a programmable
overcurrent protection and overvoltage protection.
The current information is monitored across the
inductor DCR.
The L6738A is available in a VFQFPN 16 3x3 mm
package.
Table 1. Device summary
Order code Package Packing
L6738A VFQFPN16 Tube
Description
L6738ATR VFQFPN16 Tape and reel
The L6738A is a single-phase step-down
controller with integrated high-current drivers that
provides complete control logic and protection to
realize a DC-DC converter.
The device flexibility allows to manage
conversions with power input V
January 2012 Doc ID 18134 Rev 2 1/32
as low as 1.5V
IN
www.st.com
32
Contents L6738A
Contents
1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 5
1.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Pin description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 LS-less startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 Output voltage setting and protections . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1 Overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Overcurrent threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8 High Current embedded drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.1 Boot capacitor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.2 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9 Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.1 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.2 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.1 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.2 Output capacitor(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/32 Doc ID 18134 Rev 2
L6738A Contents
10.3 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Doc ID 18134 Rev 2 3/32
List of tables L6738A
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. L6738A Protection at a glance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4/32 Doc ID 18134 Rev 2
L6738A List of figures
List of figures
Figure 1. Typical application circuit (fast protections) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. LS-less startup (left) vs. non-LS-less startup (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Current reading network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. ROSC vs. switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8. Bootstrap capacitor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. PWM control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. Example of type III compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11. Power connections (heavy lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12. Drivers turn-on and turn-off paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 13. Inductor current ripple vs. output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 14. VFQFPN16 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Doc ID 18134 Rev 2 5/32
Typical application circuit and block diagram L6738A
1 Typical application circuit and block diagram
1.1 Application circuit
Figure 1. Typical application circuit (fast protections)
VCC = 5V to 12V
C
DEC
C
HF
R
VIN = 1.5V to 19V
C
BULK
L
C
Vout
C
OUT
LOAD
C
C
R
P
I
I
PGOOD
EN
C
F
R
F
GND
VSEN
VCC
VCCDR
BOOT
UGATE
PHASE
L6738A
LGATE
CSP
CSN
R
OSC
R
FB
OSC
PGOOD
EN
COMP
FB
R
OS
FBG
C
DEC
HS
LS
L6738A Reference Schematic
6/32 Doc ID 18134 Rev 2
L6738A Typical application circuit and block diagram
Figure 2. Typical application circuit
VCC = 5V to 12V
CDEC
CHF
R
VIN = 1.5V to 19V
CBULK
L
C
COUT
Vout
LOAD
C
C
R
P
I
I
PGOOD
EN
C
F
R
F
OSC
OSC
GND
VCCDR
CDECR
VCC
PGOOD
EN
BOOT
COMP
UGATE
PHASE
FB
R
R
FB
OS
FBG
L6738A
LGATE
CSP
CSN
HS
LS
VSEN
L6738A Reference Schematic
R
OS
R
FB
Doc ID 18134 Rev 2 7/32
Typical application circuit and block diagram L6738A
1.2 Block diagram
Figure 3. Block diagram
CSN
CSP
OSC
EN
OVER CURRENT
PROGRAMMABLE
OSCILLATOR
OVP
UVP
OCP
CLOCK
VSEN
OVP UVP
CONTROL LOGIC,
MONITOR, PROTECTIONS
&
EFFICIENCY OPTIMIZATION
+25%
ERROR AMPLIFIER
-25%
COMP
PGOOD
PWM
FB
CROSS CONDUCTION
ADAPTIVE ANTI
+
0.80V
-
FBG
VCC
2.2
HS
LS
L6738A
10k 10k
BOOT
UGATE
PHASE
VCCDR
LGATE
GND
8/32 Doc ID 18134 Rev 2
L6738A Pin description and connection diagrams
2 Pin description and connection diagrams
Figure 4. Pin connection (top view)
GND
VCC
OSC
CSP
16 15 14
VCCDR
LGATE
PHASE
BOOT
1
2
3
4
L6738A
6
UGATE
PGOOD
7 5
EN
2.1 Pin descriptions
Table 2. Pin description
Pin# Name Function
1 VCCDR
2LGATE
Low side driver section power supply.
Operative voltage is 5 V to 12 V bus. Filter with 1µF MLCC to GND.
Low-side driver output.
Connect directly to the low-side MOSFET gate. A small series resistor can be useful to
reduce dissipated power especially in high frequency applications.
13
12
11
10
9
8
COMP
CSN
FBG
VSEN
FB
High-side driver return path.
3 PHASE
4BOOT
5UGATE
6 PGOOD
7EN
Connect to the high-side MOSFET source. This pin is also monitored for the adaptive
dead-time management.
High-side driver supply.
This pin supplies the high-side floating driver. Connect through the C
PHASE pin. The pin is internally connected through a boot diode to the VCCDR pin. A
2.2Ohm series resistor is also provided. See Section 8 for guidance in designing the
capacitor value.
High-side driver output.
Connect to high-side MOSFET gate. A small series resistor may help in reducing the
PHASE pin negative spike as well as cooling the device.
Power Good.
It is an open-drain output set free after SS (with 3x clock cycle delay) as long as the out-
put voltage monitored through VSEN is within specifications. Pull-up to 3.3 V (typ) or
lower, if not used it can be left floating.
Enable Pin.
Pull-high to <5 V to enable conversion, 10 µA pull-down provided.
capacitor to the
BOOT
Doc ID 18134 Rev 2 9/32
Pin description and connection diagrams L6738A
Table 2. Pin description (continued)
Pin# Name Function
8COMP
9FB
Error amplifier output.
Connect with an RF - CF to FB. The device cannot be disabled by grounding this pin.
Error amplifier inverting input.
Connect with a resistor R
Output voltage monitor.
10 VSEN
It manages OVP and UVP protections and PGOOD. Connect to the positive side of the
load for remote sensing. See Section 6 for details.
11 FBG
12 CSN
13 CSP
Remote ground sense.
Connect to the negative side of the load for remote sensing.
Current sense negative input.
Connect to the output-side of the main inductor. Filter with 100 nF (Typ.) to GND.
Current sense positive input.
Connect through an R-C filter to the phase-side of the main inductor.
OSC: Internally set to 1.24 V, it allows programming the switching frequency F
14 OSC
device. Switching frequency can be increased according to the resistor R
to SGND with a gain of 10 kHz/µA (see Section 7 for details). If floating, the switching frequency is 200 kHz.
Device power supply. The embedded bootstrap diode is internally connected to this pin.
15 VCC
Operative voltage is 5 V to 12 V bus. Filter with 1 µF MLCC to GND.
For proper operations, VCC needs to be >1.5 V higher than the programmed V
16 GND
All internal references, logic and driver return path are referenced to this pin. Connect to
the PCB GND ground plane and filter to VCC and VCCDR.
to VSEN and with an RF - CF to COMP.
FB
OSC
of the
SW
connected
.
OUT
Thermal
PA D
The thermal pad connects the silicon substrate and makes good thermal contact with the
PCB. Use VIAs to connect to the PGND plane.
2.2 Thermal data
Table 3. Thermal data
Symbol Parameter Value Unit
R
R
T
T
THJA
THJC
MAX
STG
T
Thermal resistance junction to ambient
(Device soldered on 2s2p PC Board)
Thermal resistance junction to case 1 °C/W
Maximum junction temperature 150 °C
Storage temperature range -40 to 150 °C
Junction temperature range -40 to 125 °C
J
45 °C/W
10/32 Doc ID 18134 Rev 2
L6738A Electrical specifications
3 Electrical specifications
3.1 Absolute maximum ratings
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
V
CC,VCCDR
V
, V
BOOT
UGATE
V
PHASE
V
LGATE
EN
CSP, CSN to GND
to GND -0.3 to 15 V
to GND
to PHASE
to GND, VCCDR = 12 V, t < 200 nsec.
to GND
to GND, VCCDR = 12 V, t < 200 nsec.
-0.3 to 41
15
45
-5 to 26
-8 to 30
to GND -0.3 to VCCDR + 0.3 V
to GND, VCC < 7 V
to GND, VCC > 7 V
(1)
-0.3 to VCC + 0.3
-0.3 to 7
-0.3 to VCC - 1.5 V
All other pins to GND -0.3 to 3.6 V
1. Current sense network needs to be properly bias and loop closed.
3.2 Electrical characteristics
(VCC = 5 V to 12 V; T
Table 5. Electrical characteristics
Symbol Parameter Test conditions Min. Typ. Max. Unit
= 0° to 70 °C unless otherwise specified).
j
V
V
V
Supply current and power-on
EN = HIGH 9 mA
I
CC
VCC supply current
EN = GND 8 mA
UGATE and LGATE = Open 2.6 mA
I
CCDR
UVLO
UVLO
VCC,
VCCDR
VCCDR supply current
EN = GND
UGATE and LGATE = Open
0.3 mA
Turn-ON threshold VCC, VCCDR rising 4.1 V
Hysteresis 0.2 V
Oscillator enable and soft-start
F
k
SW
OSC
Main oscillator accuracy OSC = open 180 200 220 kHz
Oscillator gain Current sink/source from OSC 10 kHz/µA
Tss Soft-start time OSC = open 4.5 5.12 5.7 msec
Tssdelay SS delay OSC = open, before SS 4.5 5.12 5.7 msec
Doc ID 18134 Rev 2 11/32
Electrical specifications L6738A
Table 5. Electrical characteristics (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
∆V
OSC
PWM ramp amplitude 2 V
d Duty cycle 0 100 %
Input logic high EN rising 0.9 V
EN
Input logic low EN falling 0.5 V
Reference and error amplifier
Output voltage accuracy Vout to FBG -0.5 - 0.5 %
A
0
DC gain
GBWP Gain-bandwidth product
SR Slew-rate
(1)
(1)
(1)
120 dB
15 MHz
8V/µs
Gate driver
I
UGATE
R
UGATE
I
LGATE
R
LGATE
HS Source current
(1)
HS sink resistance BOOT - PHASE = 12 V; 100 mA 2 2.5 Ω
LS source current
(1)
LS sink resistance 100 mA 1 1.5 Ω
BOOT - PHASE = 12 V;
to PHASE = 3.3 nF
C
UGATE
C
to GND = 5.6 nF 3 A
LGATE
2A
Current sense amplifier
V
OCTH
OC current threshold CSP - CSN; 7x masking 17 20 23 mV
PGOOD and protection
PGOOD
OVP threshold
UVP threshold VSEN falling 0.570 0.600 0.630 V
1. Guaranteed by design, not subject to test.
VSEN rising 0.870 0.900 0.930 V
Un-latch, VSEN falling 0.350 0.400 0.450 V
12/32 Doc ID 18134 Rev 2
L6738A Device description and operation
4 Device description and operation
The L6738A is a single-phase PWM controller with embedded high-current drivers that
provides complete control logic and protections to realize a general DC-DC step-down
converter. Designed to drive N-channel MOSFETs in a synchronous buck topology, with its
high level of integration, this 16-pin device allows a reduction of cost and size of the power
supply solution and also provides real-time PGOOD in a compact VFQFPN16 3x3 mm.
The L6738A is designed to operate from a 5 V or 12 V supply. The output voltage can be
precisely regulated to as low as 0.8 V with ±0.5% accuracy over line and temperature
variations. The controller performs remote GND recovery to prevent losses and GND drops
to affect the regulation.
The switching frequency is internally set to 200 kHz and adjustable through the OSC pin.
The IC can be disabled by pulling the OSC pin low.
The L6738A provides a simple control loop with a voltage-mode error-amplifier. The erroramplifier features a 15 MHz gain-bandwidth product and 8 V/µs slew rate, allowing high
regulator bandwidth for fast transient response.
To avoid load damages, the L6738A provides overcurrent protection, and overvoltage and
undervoltage protection. The overcurrent trip threshold is monitored through the inductor
DCR, assuring optimum precision, saving the use of an expensive and space-consuming
sense resistor. The output voltage is monitored through the dedicated VSEN pin.
The L6738A implements soft-start by increasing the internal reference in closed loop
regulation. The low-side-less feature allows the device to perform the soft-start over prebiased output avoiding high current return through the output inductor and dangerous
negative spikes at the load side.
The L6738A is available in a compact VFQFN16 3x3 mm package with exposed pad.
Doc ID 18134 Rev 2 13/32
Soft-start L6738A
5 Soft-start
The L6738A implements a soft-start to smoothly charge the output filter avoiding high inrush currents to be required to the input power supply. During this phase, the device
increases the internal reference from zero up to 0.8 V in closed loop regulation. The softstart is implemented only when VCC and VCCDR are above their own UVLO threshold and
the EN pin is set free.
When SS takes place, the IC initially waits for 1024 clock cycles and then starts ramping-up
the reference in 1024 clock cycles in closed-loop regulation. At the end of the digital softstart, the PWRGOOD signal is set free with 3x clock cycles delay.
Protections are active during this phase as follows:
● undervoltage is enabled when the reference voltage reaches 80% of the final value
● overvoltage is always enabled
● FB disconnection is enabled
Soft-start time depends on the programmed frequency, initial delay and reference ramp-up
lasts for 1024 clock cycles. SS time and initial delay can be determined as follows:
5.1 LS-less startup
In order to avoid any kind of negative undershoot on the load side during startup, the
L6738A performs a special sequence in enabling the drivers for both sections: during the
soft-start phase, the LS MOSFET is kept OFF until the first PWM pulse. This particular
sequence avoids the dangerous negative spike on the output voltage that can happen if
starting over a pre-biased output.
Low-side MOSFET turn-on is masked only from the control loop point of view: protections
are still allowed to turn on the low-side MOSFET in the case of overvoltage, if needed.
TSSms[]
1024
------------ ------------- -----=
Fsw kHz][]
14/32 Doc ID 18134 Rev 2
L6738A Soft-start
Figure 5. LS-less startup (left) vs. non-LS-less startup (right)
Doc ID 18134 Rev 2 15/32
Output voltage setting and protections L6738A
6 Output voltage setting and protections
The L6738A is capable of precisely regulating an output voltage as low as 0.8 V. In fact, the
device comes with a fixed 0.8 V internal reference that guarantees the output regulated
voltage to be within ±0.5% tolerance over line and temperature variations (excluding output
resistor divider tolerance, when present).
Output voltage higher than 0.8 V can be easily achieved by adding a resistor R
between
OS
the FB pin and ground. Referring to Figure 1, the steady-state DC output voltage is:
R
FB
⎛⎞
1
-----------+
⋅=
⎝⎠
R
OS
where V
REF
is 0.8 V.
V
OUTVREF
The L6738A monitors the voltage at the VSEN pin and compares it to the internal reference
voltage in order to provide undervoltage and overvoltage protections, as well as PGOOD
signal. According to the level of VSEN, different actions are performed from the controller:
● PGOOD
If the voltage monitored through VSEN exits from the PGOOD window limits, the device
de-asserts the PGOOD signal.
PGOOD is asserted at the end of the soft-start phase with 3x clock cycles delay.
● Undervoltage protection (UV)
If the voltage at the VSEN pin drops below the UV threshold, the device turns off both
HS and LS MOSFETs, latching the condition. Cycle VCC or EN to recover.
UV is also active during SS acting as VIN detection protection. See description below.
● Overvoltage protection (OV)
If the voltage at the VSEN pin rises over the OV threshold, overvoltage protection turns
off the HS MOSFET and turns on the LS MOSFET. The LS MOSFET is turned off as
soon as VSEN goes below Vref/2. The condition is latched, cycle VCC/EN to recover.
Note that, even if the device is latched, the device still controls the LS MOSFET and
can switch it on whenever VSEN rises above the OV threshold.
● PreOVP protection
Monitors VSEN when IC is disabled. If VSEN surpasses the OV threshold, IC turns on
the low-side MOSFET to protect the load. On the EN rising edge, the protection is
disabled and the IC implements the SS procedure.
PreOVP is disabled when EN is high but the OV protection becomes operative.
● VIN detection
UV Protection active during SS allows the IC to detect whether input voltage VIN is
present. If UV is triggered during the soft-start, it resets the SS procedure: the
controller re-implements the initial delay and re-ramps-up the reference with the same
SS timings described in Section 5.
The UV protection is then avoiding that IC starts-up if VIN is not present.
Protections are active also during soft-start (See Section 5).
16/32 Doc ID 18134 Rev 2
L6738A Output voltage setting and protections
For proper operations, VCC needs to be at least 1.5 V higher than the programmed output
voltage.
Table 6. L6738A Protection at a glance.
L6738A Comments
Overvoltage
(OV)
Undervoltage (UV)
PGOOD
Overcurrent (OC)
VSEN = +12.5% above reference.
Action: IC Latch; LS=ON until VSEN = 50% of Vref; PGOOD = GND.
Action (EN=0): IC Latch; LS=ON; reset by EN rising edge (PreOVP).
VSEN = -25% below reference.
Action: IC Latch; HiZ; PGOOD = GND.
Action (SS): SS reset (VIN Detection).
PGOOD is set to zero whenever VSEN falls outside the +12.5% / -25% of Vref.
Action: PGOOD transition coincides with OV/UV protection set.
Current Monitor across Inductor DCR.
Action: 1st Threshold (20 mV): IC latch after 7 consecutive constant current
events.
6.1 Overcurrent
The overcurrent function protects the converter from a shorted output or overload, by
sensing the output current information across the inductor DCR. This method reduces cost
and enhances converter efficiency by avoiding the use of expensive and space-consuming
sense resistors.
The inductor DCR current sense is implemented by comparing and monitoring the
difference between the CSP and CSN pins. If the monitored voltage is bigger than the
internal thresholds, an overcurrent event is detected.
DCR current sensing requires time constant matching between the inductor and the reading
network:
L
------------- RC V
DCR
CSP-CSN
DCR I
⋅=⇒⋅=
OUT
The L6738A monitors the voltage between CSP and CSN, when this voltage exceeds the
OC threshold, an overcurrent is detected. The IC works in constant current mode, turning on
the low-side MOSFET immediately while the OC persists and, in any case, until the next
clock cycle. After seven consecutive OC events, overcurrent protection is triggered and the
IC latches.
When overcurrent protection is triggered, the device turns off both LS and HS MOSFETs in
a latched condition.
To recover from an overcurrent protection triggered condition, VCC power supply or EN
must be cycled.
For proper current reading, the CSN pin must be filtered by 100 nF (Typ.) MLCC to GND.
Doc ID 18134 Rev 2 17/32
Output voltage setting and protections L6738A
6.2 Overcurrent threshold setting
The L6738A detects OC when the difference between CSP and CSN is equal to 20 mV
(typ). By properly designing the current reading network, it is possible to program the OC
threshold as desired (See Figure 6).
I
OCP
20m V
------------- ---
DCR
R1 R2+
------------ ----------
⋅=
R2
Time constant matching is, in this case, designed considering:
L
------------- R1//R2()C⋅=
DCR
This means that once inductor has been chosen, the two conditions above define the proper
values for R1 and R2.
Figure 6. Current reading network
DCR
L
R1
R2 (Opt)
CSP
CSN
18/32 Doc ID 18134 Rev 2
C
L6738A Main oscillator
7 Main oscillator
The controller embeds a programmable oscillator. The internal oscillator generates the
sawtooth waveform for the PWM charging with a constant current and resetting an internal
capacitor. The switching frequency, F
The current delivered to the oscillator is typically 20 µA (corresponding to the free running
frequency F
=200 kHz) and it may be varied using an external resistor (R
SW
connected between the OSC pin and GND. As the OSC pin is fixed at 1.240 V, the
frequency is varied proportionally to the current sunk from the pin considering the internal
gain of 10 KHz/µA (see Figure 7).
, is internally fixed at 200 kHz.
SW
) typically
OSC
Figure 7. R
Connecting R
to GND, the frequency is increased (current is sunk from the pin),
OSC
according to the following relationships:
Connecting R
F
to a positive voltage, the frequency is reduced (current is forced into the
OSC
SW
200kHz
pin), according to the following relationships:
+V 1.240–
F
SW
200kH z
------------ ------------- ---
where +V is the positive voltage to which the R
vs. switching frequency
OSC
1.240V
------------- ------
R
OSC
R
OSC
resistor is connected.
OSC
kHz
-----------
10
⋅+=
µA
kHz
-----------
10
⋅–=
µA
Doc ID 18134 Rev 2 19/32
High Current embedded drivers L6738A
8 High Current embedded drivers
The L6738A provides high-current driving control. The driver for the high-side MOSFET
uses the BOOT pin for supply and the PHASE pin for return. The driver for the low-side
MOSFET uses the VCCDR pin for supply and the GND pin for return.
The embedded driver embodies an anti-shoot-through and adaptive dead-time control to
minimize the low-side body diode conduction time maintaining good efficiency and saving
the use of Schottky diodes: when the high-side MOSFET turns off, the voltage on its source
begins to fall; when the voltage reaches about 2 V, the low-side MOSFET gate drive voltage
is suddenly applied. When the low-side MOSFET turns off, the voltage at the LGATE pin is
sensed. When it drops below about 1 V, the high-side MOSFET gate drive voltage is
suddenly applied. If the current flowing in the inductor is negative, the source of the highside MOSFET never drops. To allow the low-side MOSFET to turn on even in this case, a
watchdog controller is enabled: if the source of the high-side MOSFET doesn't drop, the lowside MOSFET is switched on, so allowing the negative current of the inductor to recirculate.
This mechanism allows the system to regulate even if the current is negative.
8.1 Boot capacitor design
The bootstrap capacitor needs to be designed in order to show a negligible discharge due to
the high-side MOSFET turn on. In fact, it must give a stable voltage supply to the high-side
driver during the MOSFET turn on, also minimizing the power dissipated by the embedded
boot diode. Figure 8 gives some guidelines on how to select the capacitance value for the
bootstrap according to the desired discharge and depending on the selected MOSFET.
To prevent the bootstrap capacitor to extra-charge as a consequence of large negative
spikes, an internal 2.2 Ohms series resistance R
is provided in series to the BOOT
BOOT
diode pin.
Figure 8. Bootstrap capacitor design
2.5
Cboot = 47nF
Cboot = 100nF
2.0
Cboot = 220nF
Cboot = 330nF
Cboot = 470nF
1.5
1.0
BOOT Cap discharge [V]
0.5
0.0
0102030405060708090100
High -Side MOSFET Gate Charge [nC]
2500
Qg = 10nC
2000
1500
1000
Bootstrap Cap [uF]
500
0
0.0 0.2 0.4 0.6 0.8 1.0
Boot Cap Delta Vo ltage [V]
Qg = 25nC
Qg = 50nC
Qg = 100nC
8.2 Power dissipation
It is important to consider the power that the device is going to dissipate in driving the external MOSFETs in order to avoid surpassing the maximum junction operative temperature.
20/32 Doc ID 18134 Rev 2
L6738A High Current embedded drivers
Two main terms contribute in the device power dissipation: bias power and drivers' power.
● Device Power (P
) depends on the static consumption of the device through the
DC
supply pins and it is simply quantifiable as follows:
P
DCVCCICCVVCCDRIVCCDR
● Drivers' power is the power needed by the driver to continuously switch ON and OFF
⋅+⋅=
the external MOSFETs; it is a function of the switching frequency and total gate charge
of the selected MOSFETs. It can be quantified considering that the total power P
SW
,
dissipated to switch the MOSFETs, is dissipated by three main factors: external gate
resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance.
This last term is the important one to be determined to calculate the device power
dissipation.
The total power dissipated to switch the MOSFETs for each phase featuring embedded
driver results:
where Q
P
is the total gate charge of the HS MOSFETs and Q
GHS
SW
F
SW
Q
GHS
VCCDR⋅ Q
GLS
VCCDR⋅+()⋅=
is the total gate
GLS
charge of the LS MOSFETs.
Doc ID 18134 Rev 2 21/32
Application details L6738A
9 Application details
9.1 Compensation network
The control loop shown in Figure 9 is a voltage mode control loop. The output voltage is
regulated to the internal reference (when present, an offset resistor between FB node and
GND can be neglected in control loop calculation).
Error amplifier output is compared to the oscillator sawtooth waveform to provide a PWM
signal to the driver section. The PWM signal is then transferred to the switching node with
V
amplitude. This waveform is filtered by the output filter.
IN
The converter transfer function is the small signal transfer function between the output of the
EA and V
resonance and a zero at F
modulator is simply the input voltage V
∆V
OSC
Figure 9. PWM control loop
. This function has a double pole at frequency FLC depending on the L-C
OUT
depending on the output capacitor ESR. The DC gain of the
ESR
divided by the peak-to-peak oscillator voltage
IN
.
V
OSC
IN
OUT
∆V
OSC
The compensation network closes the loop joining V
function ideally equal to -Z
_
+
PWM
COMPARATOR
ERROR
AMPLIFIE R
C
F
C
P
.
F/ZFB
L R
C
OUT
ESR
V
REF
+
_
R
F
R
FB
C
R
S
S
Z
FB
Z
F
and EA output with transfer
OUT
V
OUT
Compensation goal is to close to the control loop assuring high DC regulation accuracy,
good dynamic performance and stability. To achieve this, the overall loop needs high DC
gain, high bandwidth and good phase margin.
High DC gain is achieved giving an integrator shape to compensation network transfer
function. Loop bandwidth (F
stability, it should not exceed F
) can be fixed choosing the right RF/RFB ratio, however, for
0dB
/2π. To achieve a good phase margin, the control loop gain
SW
has to cross the 0dB axis with -20dB/decade slope.
For example, Figure 10 shows an asymptotic bode plot of a type III compensation.
22/32 Doc ID 18134 Rev 2
L6738A Application details
Figure 10. Example of type III compensation.
Gain
[dB]
open loop
EA gain
FZ1F
Z2
F
F
P1
P2
closed
loop ga in
compensation
gain
open loop
converter gain
0dB
F
LC
● Open loop converter singularities:
a)
F
LC
b)
F
ESR
● Compensation Network singularities frequencies:
1
------------- ------------ ------------=
⋅
2π LC
------------- ------------- ------------- ----------=
2π C
OUT
1
OUT
ESR⋅⋅
F
0dB
F
ESR
20log (RF/RFB)
20log (V
/∆V
IN
Log (Freq)
OSC
)
a)
b)
c)
d)
F
Z1
F
Z2
F
P1
F
P2
1
------------- ------------- ----------=
2π R
⋅⋅
FCF
------------ ------------- ------------- ------------ --------=
2π R
------------- ------------- ------------- ------------ -----=
2π R
------------- ------------- ----------=
2π R
1
⋅⋅
+()C
FBRS
S
1
CFCP⋅
⎛⎞
⋅⋅
--------------------- -
F
⎝⎠
C
+
FCP
1
⋅⋅
SCS
To place the poles and zeros of the compensation network, the following suggestions may
be followed:
Doc ID 18134 Rev 2 23/32
Application details L6738A
a) Set the gain RF/RFB in order to obtain the desired closed loop regulator bandwidth
according to the approximated formula (suggested values for R
are in the range
FB
of some kΩ):
R
F
----------
R
FB
b) Place F
C
F
c) Place F
C
P
d) Place F
R
S
C
S
F
------------
Z1
------------ ------------- ----------=
⋅⋅
π R
P1
------------ ------------- ------------- ------------- ------------ --- -=
2π RFCFF
Z2
------------- ------------ -----=
F
-------------------- 1–
2F⋅
------------- ------------- -----------=
⋅⋅
π R
∆V
F
0dB
LC
------------ ------ -
⋅=
V
OSC
IN
below FLC (typically 0.5*FLC):
1
FFLC
at F
ESR
:
C
F
1–⋅⋅⋅
ESR
at FLC and FP2 at half of the switching frequency:
R
FB
SW
LC
1
SFSW
e) Check that compensation network gain is lower than open loop EA gain before
;
F
0dB
f) Check phase margin obtained (it should be greater than 45°) and repeat if
necessary.
9.2 Layout guidelines
The L6738A provides control functions and high current integrated drivers to implement
high-current step-down DC-DC converters. In this kind of application, a good layout is very
important.
The first priority when placing components for these applications has to be reserved to the
power section, minimizing the length of each connection and loop as much as possible. To
minimize noise and voltage spikes (EMI and losses) power connections (highlighted in
Figure 11) must be a part of a power plane and realized by wide and thick copper traces:
loop must be minimized. The critical components, i.e. the power MOSFETs, must be close
to one another. The use of a multi-layer printed circuit board is recommended.
The input capacitance (C
placed close to the power section in order to eliminate the stray inductance generated by the
copper traces. Low ESR and ESL capacitors are preferred, MLCCs are recommended to be
connected near the HS drain.
Use a proper number of VIAs when power traces have to move between different planes on
the PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing
the same high-current trace on more than one PCB layer reduces the parasitic resistance
associated to that connection.
24/32 Doc ID 18134 Rev 2
), or at least a portion of the total capacitance needed, has to be
IN
L6738A Application details
Connect output bulk capacitors (C
) as near as possible to the load, minimizing parasitic
OUT
inductance and resistance associated to the copper trace, also adding extra decoupling
capacitors along the way to the load when this results in being far from the bulk capacitors
bank.
Remote Sense Connection must be routed as parallel nets from the FBG/VSEN pins to the
load in order to avoid the pick-up of any common mode noise. Connecting these pins in
points far from the load causes a non-optimum load regulation, increasing output tolerance.
Locate current reading components close to the device. The PCB traces connecting the
reading point must use dedicated nets, routed as parallel traces in order to avoid the pick-up
of any common mode noise. It's also important, to avoid any offset in the measurement and,
to get a better precision, to connect the traces as close as possible to the sensing elements.
A small filtering capacitor can be added, near the controller, between VOUT and GND, on
the CSN line to allow higher layout flexibility.
Figure 11. Power connections (heavy lines)
V
IN
UGATE
PHASE
C
IN
L
L6738
C
LGATE
GND
OUT
LOAD
Gate traces and phase trace must be sized according to the driver RMS current delivered to
the power MOSFET. The device robustness allows the managing of applications with the
power section far from the controller without losing performance. However, when possible, it
is recommended to minimize the distance between the controller and power section.
Small signal components and connections to critical nodes of the application, as well as
bypass capacitors for the device supply, are also important. Locate the bypass capacitor
(VCC and bootstrap capacitor) and feedback compensation components as close to the
device as practical.
Figure 12. Drivers turn-on and turn-off paths
LS DRIVER LS MOSFET
VCCDR
CGD
RGATE RINT
LGATE
CGS CDS
GND
HS DRIVER HS MOSFET
BOOT
CGD
RGATE RINT
UGATE
CGS CDS
PHASE
Doc ID 18134 Rev 2 25/32
Application information L6738A
10 Application information
10.1 Inductor design
The inductance value is defined by a compromise between the dynamic response time, the
efficiency, the cost, and the size. The inductor must be calculated to maintain the ripple
current (∆I
value can be calculated with the following relationship:
) between 20% and 30% of the maximum output current (typ). The inductance
L
–
L
V
INVOUT
------------ ------------ ----- -
F
⋅
SW∆IL
⋅=
V
OUT
--------------
V
IN
where FSW is the switching frequency, VIN is the input voltage and V
is the output
OUT
voltage. Figure 13 shows the ripple current vs. the output voltage for different values of the
inductor, with V
= 5 V and VIN = 12 V.
IN
Increasing the value of the inductance reduces the current ripple but, at the same time,
increases the converter response time to a dynamic load change. The response time is the
time required by the inductor to change its current from initial to final value. Until the inductor
has finished its charging time, the output current is supplied by the output capacitors.
Minimizing the response time can minimize the output capacitance required. If the
compensation network is well designed, during a load variation the device is able to set a
duty cycle value very different (0% or 80%) from the steady-state one. When this condition
is reached, the response time is limited by the time required to change the inductor current.
Figure 13. Inductor current ripple vs. output voltage
26/32 Doc ID 18134 Rev 2
L6738A Application information
10.2 Output capacitor(s)
The output capacitors are basic components to define the ripple voltage across the output
and for the fast transient response of the power supply. They depend on the output voltage
ripple requirements, as well as any output voltage deviation requirement during a load
transient.
During steady-state conditions, the output voltage ripple is influenced by both the ESR and
capacitive value of the output capacitors as follows:
∆V
OUT_ESR
∆V
OUT_C
where ∆IL is the inductor current ripple. In particular, the expression that defines ∆V
∆ILESR⋅=
----------- ------------- ------------- -------
∆I
⋅=
L
⋅⋅
8C
1
OUTFSW
OUT_C
takes into consideration the output capacitor charge and discharge as a consequence of the
inductor current ripple.
During a load variation, the output capacitors supply the current to the load or absorb the
current stored in the inductor until the converter reacts. In fact, even if the controller
immediately recognizes the load transient and sets the duty cycle at 80% or 0%, the current
slope is limited by the inductor value. The output voltage has a drop that, also in this case,
depends on the ESR and capacitive charge/discharge as follows:
∆V
OUT_ESR
∆I
OUT
ESR⋅=
L ∆I
⋅
∆V
OUT_C
∆I
------------ ------------- ------------- -----
⋅=
OUT
2C
⋅⋅
OUT
OUT
∆V
L
where ∆VL is the voltage applied to the inductor during the transient response
( for the load appliance or V
MAXVINVOUT
–⋅
for the load removal).
OUT
MLCC capacitors have typically low ESR to minimize the ripple but also have low
capacitance which does not minimize the voltage deviation during dynamic load variations.
On the contrary, electrolytic capacitors have large capacitance to minimize voltage deviation
during load transients while they do not show the same ESR values as the MLCC resulting
Doc ID 18134 Rev 2 27/32
Application information L6738A
therefore in higher ripple voltages. For these reasons, a mix between electrolytic and MLCC
capacitors is suggested to minimize ripple as well as reduce voltage deviation in dynamic
mode.
10.3 Input capacitors
The input capacitor bank is designed considering mainly the input RMS current that
depends on the output deliverable current (I
follows:
) and the duty-cycle (D) for the regulation as
OUT
I
rmsIOUT
The equation reaches its maximum value, I
OUT
input capacitor ESR and, in the worst case, are:
P ESR I
⋅=
D1D–()⋅⋅=
/2, with D = 0.5. The losses depend on the
2
2⁄()
OUT
28/32 Doc ID 18134 Rev 2
L6738A Package mechanical data
11 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions, and product status are available at www.st.com. ECOPACK
is an ST registered trademark.
®
packages, depending on their level of environmental compliance. ECOPACK
Doc ID 18134 Rev 2 29/32
Package mechanical data L6738A
Figure 14. VFQFPN16 mechanical data and package dimensions
mm mils
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
0.80 0.90 1.00 31.49 35.43 39.37
A
A1 0.02 0.05 0.78 1.96
A2 0.65 1.00 25.59 39.37
A3 0.20 7.87
b 0.18 0.25 0.30 7.08 9.84 11.81
D 2.85 3.00 3.15 112.2 118.1 124.0
D1 1.50 59.05
D2 1.60 62.99
E 2.85 3.00 3.15 112.2 118.1 124.0
E1 1.50 59.05
E2 1.60 62.99
e 0.45 0.50 0.55 17.71 19.68 21.65
L 0.30 0.40 0.50 11.81 15.74 19.68
ddd 0.08 3.15
OUTLINE AND
MECHANICAL DATA
VFQFPN-16 (3x3x1.0mm)
Very Fine Quad Flat Package No lead
30/32 Doc ID 18134 Rev 2
L6738A Revision history
12 Revision history
Table 7. Document revision history
Date Revision Changes
03-Nov-2010 1 Initial release.
23-Jan-2012 2 Updated PGOOD limits in Ta bl e 5
Doc ID 18134 Rev 2 31/32
L6738A
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32/32 Doc ID 18134 Rev 2
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