ST L6731D User Manual

L6731D

Adjustable step-down controller with synchronous rectification dedicated to DDR memory

Features

■Input voltage range from 1.8 V to 14 V

■Supply voltage range from 4.5 V to 14 V

■Adjustable output voltage down to 0.6 V with ±0.8 % Accuracy over line voltage and temperature (0 °C~125 °C)

■Fixed frequency voltage mode control

■TON lower than 100 ns

■0 % to 100 % duty cycle

■VDDR input sense

■Regulates VTT and VTTREF within 1 % of VDDQ

■Soft-start and inhibit

■High current embedded drivers

■Predictive anti-cross conduction control

■Programmable high-side and low-side RDS(on) sense over-current-protection

■Selectable switching frequency 250 kHz / 500 kHz

■Power good output

■Sink/source capability for DDR memory and termination supply

■Over-voltage protection

■Thermal shutdown

■Package: HTSSOP16

HTSSOP16 (exposed pad)

Applications

■High performance / high density DC-DC modules

■Low voltage distributed DC-DC

■niPoL converters

■DDR memory supply

■DDR termination supply

■Graphic cards

Table 1.	Device summary
	Order codes	Package	Packaging
	L6731D	HTSSOP16	Tube
	L6731DTR	HTSSOP16	Tape and reel
June 2008		Rev 3	1/23
			www.st.com

Contents	L6731D

Contents

1	Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 3
	1.1	Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4
2	Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		5
	2.1	Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
	2.2	Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
3	Pin connections and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
4	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
5	Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		10
	5.1	Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
	5.2	Internal LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
	5.3	Bypassing the LDO to avoid the voltage drop with low Vcc . . . . . . . . . . .	11
	5.4	Internal and external references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	5.5	Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	5.6	Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	5.7	Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	5.8	Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	5.9	HICCUP mode during an OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	5.10	Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	5.11	Minimum on-time (TON, MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
6	Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
	6.1	Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	6.2	Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	6.3	Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	6.4	Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
7	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21
8	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		22

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L6731D	Summary description

1 Summary description

The controller is an integrated circuit realized in BCD5 (BiCMOS-DMOS, version 5) fabrication that provides complete control logic and protection for high performance step-down DC-DC and niPoL converters.

It is designed to drive N-channel MOSFETs in a synchronous rectified buck topology. The output voltage of the converter can be precisely regulated down to 600 mV with a maximum tolerance of ±0.8 %. If an external reference is used, it will be transferred divided by 2 to the N.I. input of the error-amplifier, in accordance to the DDR memory specifications.

An internal resistor divider and a voltage buffer allow to achieve an accuracy of 1 % on both Vtt and Vttref. It's possible to provide an external reference from 0V to 2.5 V in order to meet the specification for DDRI and DDRII. The input voltage can range from 1.8 V to 14 V, while the supply voltage can range from 4.5 V to 14 V. High peak current gate drivers provide for fast switching to the external power section, and the output current can be in excess of 20 A.

The PWM duty cycle can range from 0 % to 100 % with a minimum on-time (TON, MIN) lower than 100 ns making possible conversions with very low duty cycle at high switching

frequency. The device provides voltage-mode control that includes a selectable frequency oscillator (250 kHz or 500 kHz).

The error amplifier features a 10 MHz gain-bandwidth-product and 5 V/µs slew-rate that permits to realize high converter bandwidth for fast transient response. The device monitors

the current by using the RDS(on) of both the high-side and low-side MOSFET(s), eliminating the need for a current sensing resistor and guaranteeing an effective over-current-protection

in all the application conditions.

When necessary, two different current limit protections can be externally set through two external resistors. During the soft-start phase a constant current protection is provided while after the soft-start the device enters in hiccup mode in case of over-current. The converter can always sink current. Other features are power good, not latched over-voltage-protection, feed-back disconnection and thermal shutdown. The HTSSOP16 package allows the realization of really compact DC/DC converters.

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Summary description	L6731D

1.1Functional description

Figure 1. Block diagram

				VCC=4.5V to14V
							Vin=1.8V to14V
OCL			OCH			VCCDR
				VCC
				LDO			BOOT
SS/INH		Monitor					HGATE
Protection and Ref
			OSC			-	Vo
							PHASE
DDR-IN			L6731D
	R
							LGATE
		+	0.6V	-
	R
		-		+
PGOOD					PWM
							PGND
+	-					E/A
					+	-
							SGND
							VFB
VTTREF			COMP

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L6731D	Electrical data

2 Electrical data

2.1Maximum rating

Table 2.	Absolute maximum ratings
Symbol		Parameter	Value	Unit
VCC		VCC to GND and PGND, OCH, PGOOD	-0.3 to 18	V
VBOOT -		Boot voltage	0 to 6	V
VPHASE
VHGATE -			0 to VBOOT - VPHASE	V
VPHASE
VBOOT		BOOT	-0.3 to 24	V
		PHASE	-1 to 18
				V
VPHASE		PHASE spike, transient < 50 ns (FSW = 500 kHz)	-3
			+24
		SS, FB, DDR-IN, SYNC, VTTREF, OCL, LGATE,	-0.3 to 6	V
		COMP, VCCDR
OCH pin		Maximum withstanding voltage range	±1500
PGOOD pin		test condition: CDF-AEC-Q100-002 “human body	±1000	V
		model” acceptance criteria: “normal performance”
Other pins			±2000

2.2Thermal data

Table 3.	Thermal data
Symbol	Description	Value	Unit
(1)	Thermal resistance junction to ambient	50	°C/W
RthJA
TSTG	Storage temperature range	-40 to 150	°C
TJ	Junction operating temperature range	-40 to 125	°C
TA	Ambient operating temperature range	-40 to +85	°C

1. Package mounted on demonstration board

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Pin connections and functions	L6731D

3 Pin connections and functions

Figure 2. Pin connection (top view)

PGOOD	1	16	VCC
VTTREF	2	15	VCCDR
SGND	3	14	LGATE
FB	4	13	PGND
COMP	5	12	BOOT
SS/INH	6	11	HGATE
DDR-IN	7	10	PHASE
OCL	8	9	OCH
		HTSSOP16

	Table 4.	Pin functions
	Pin n.	Name	Function
			This pin is an open collector output and it is pulled low if the output voltage
	1	PGOOD	is not within the specified thresholds (90 %-110 %). If not used it may be left
			floating. Pull-up this pin to VCCDR with a 10 K resistor to obtain a logical
			signal.
			This pin is connected to the output of an internal buffer that provides ½ of
	2	VTTREF	DDR-IN. This pin can be connected to the VTTREF input of the DDR
			memory itself. Filter to GND with 10 nF capacitor.
	3	SGND	All the internal references are referred to this pin.
			This pin is connected to the error amplifier inverting input. Connect it to
	4	FB	VOUT through the compensation network. This pin is also used to sense the
			output voltage in order to manage the over voltage conditions and the
			PGood signal.
	5	COMP	This pin is connected to the error amplifier output and is used to
			compensate the voltage control feedback loop.
			The soft-start time is programmed connecting an external capacitor from
	6	SS/INH	this pin and GND. The internal current generator forces a current of 10 µA
			through the capacitor. When the voltage at this pin is lower than 0.5 V the
			device is disabled.
			By setting the voltage at this pin is possible to select the internal/external
			reference and the switching frequency:
			VEAREF 0-80 % of VCCDR -> External reference/FSW = 250 kHz
	7	DDR-IN	VEAREF = 80 %-95 % of VCCDR -> VREF = 0.6 V/FSW = 500 kHz
			VEAREF = 95 %-100 % of VCCDR -> VREF = 0.6 V/FSW = 250 kHz
			An internal clamp limits the maximum VEAREF at 2.5 V (typ.). The device
			captures the analog value present at this pin at the start-up when VCC
			meets the UVLO threshold.

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L6731D			Pin connections and functions
	Table 4.	Pin functions (continued)
	Pin n.	Name	Function
			A resistor connected from this pin to ground sets the valley- current-limit.
			The valley current is sensed through the low-side MOSFET(s). The internal
			current generator sources a current of 100 µA (IOCL) from this pin to ground
			through the external resistor (ROCL). The over-current threshold is given by
			the following equation:
	8	OCL	IOCL • ROCL
			IVALLEY = ---------------------------------
			2 • RDSONLS
			Connecting a capacitor from this pin to GND helps in reducing the noise
			injected from VCC to the device, but can be a low impedance path for the
			high-frequency noise related to the GND. Connect a capacitor only to a
			"clean" GND.
			A resistor connected from this pin and the high-side MOSFET(s) drain sets
			the peak-current-limit. The peak current is sensed through the high-side
			MOSFET(s). The internal 100 µA current generator (IOCH) sinks a current
	9	OCH	from the drain through the external resistor (ROCH). The over-current
			threshold is given by the following equation:
			IOCH • ROCH
			IPEAK = ---------------------------------
			RDSONHS
			This pin is connected to the source of the high-side MOSFET(s) and
	10	PHASE	provides the return path for the high-side driver. This pin monitors the drop
			across both the upper and lower MOSFET(s) for the current limit together
			with OCH and OCL.
	11	HGATE	This pin is connected to the high-side MOSFET(s) gate.
			Through this pin is supplied the high-side driver. Connect a capacitor from
	12	BOOT	this pin to the PHASE pin and a diode from VCCDR to this pin (cathode
			versus BOOT).
	13	PGND	This pin has to be connected closely to the low-side MOSFET(s) source in
			order to reduce the noise injection into the device.
	14	LGATE	This pin is connected to the low-side MOSFET(s) gate.
	15	VCCDR	5 V internally regulated voltage. It is used to supply the internal drivers.
			Filter it to ground with at least 1 µF ceramic cap.
	16	VCC	Supply voltage pin.
			The operative supply voltage range is from 4.5 V to 14 V.

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