ST L6731D User Manual

Adjustable step-down controller with synchronous rectification
Features
Input voltage range from 1.8 V to 14 V
Supply voltage range from 4.5 V to 14 V
±0.8 % Accuracy over line voltage and temperature (0 °C~125 °C)
Fixed frequency voltage mode control
T
0 % to 100 % duty cycle
V
Regulates V
High current embedded drivers
Predictive anti-cross conduction control
Programmable high-side and low-side R
Selectable switching frequency 250 kHz /
Power good output
Sink/source capability for DDR memory and
Over-voltage protection
Thermal shutdown
Package: HTSSOP16
lower than 100 ns
ON
input sense
DDR
and V
TT
within 1 % of V
TTREF
Soft-start and inhibit
sense over-current-protection
500 kHz
termination supply
DDQ
DS(on)
dedicated to DDR memory
HTSSOP16 (exposed pad)
Applications
High performance / high density DC-DC
modules
Low voltage distributed DC-DC
niPoL converters
DDR memory supply
DDR termination supply
Graphic cards
L6731D

Table 1. Device summary

Order codes Package Packaging
L6731D HTSSOP16 Tube
L6731DTR HTSSOP16 Tape and reel
June 2008 Rev 3 1/23
www.st.com
23
Contents L6731D
Contents
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Pin connections and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2 Internal LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3 Bypassing the LDO to avoid the voltage drop with low Vcc . . . . . . . . . . . 11
5.4 Internal and external references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.5 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.6 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.7 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.8 Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.9 HICCUP mode during an OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.10 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.11 Minimum on-time (TON, MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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L6731D Summary description

1 Summary description

The controller is an integrated circuit realized in BCD5 (BiCMOS-DMOS, version 5) fabrication that provides complete control logic and protection for high performance step-down DC-DC and niPoL converters.
It is designed to drive N-channel MOSFETs in a synchronous rectified buck topology. The output voltage of the converter can be precisely regulated down to 600 mV with a maximum tolerance of ±0.8 %. If an external reference is used, it will be transferred divided by 2 to the N.I. input of the error-amplifier, in accordance to the DDR memory specifications.
An internal resistor divider and a voltage buffer allow to achieve an accuracy of 1 % on both Vtt and Vttref. It's possible to provide an external reference from 0V to 2.5 V in order to meet the specification for DDRI and DDRII. The input voltage can range from 1.8 V to 14 V, while the supply voltage can range from 4.5 V to 14 V. High peak current gate drivers provide for fast switching to the external power section, and the output current can be in excess of 20 A.
The PWM duty cycle can range from 0 % to 100 % with a minimum on-time (T than 100 ns making possible conversions with very low duty cycle at high switching frequency. The device provides voltage-mode control that includes a selectable frequency oscillator (250 kHz or 500 kHz).
The error amplifier features a 10 MHz gain-bandwidth-product and 5 V/µs slew-rate that permits to realize high converter bandwidth for fast transient response. The device monitors the current by using the R the need for a current sensing resistor and guaranteeing an effective over-current-protection in all the application conditions.
When necessary, two different current limit protections can be externally set through two external resistors. During the soft-start phase a constant current protection is provided while after the soft-start the device enters in hiccup mode in case of over-current. The converter can always sink current. Other features are power good, not latched over-voltage-protection, feed-back disconnection and thermal shutdown. The HTSSOP16 package allows the realization of really compact DC/DC converters.
of both the high-side and low-side MOSFET(s), eliminating
DS(on)
ON, MIN
) lower
3/23
Summary description L6731D

1.1 Functional description

Figure 1. Block diagram

VCC=4.5V to14V
V
=1.8V to14V
in
SS/INH
DDR-IN
PGOOD
OCL
OCH
Monitor
Protection and Ref
OSC
R
0.6V
+
R
-
+
-
VTTREF
LDO
L6731D
-
+
COMP
VCC
PWM
+
VCCDR
BOOT
HGATE
­PHASE
LGATE
PGND
E/A
-
SGND
VFB
Vo
4/23
L6731D Electrical data

2 Electrical data

2.1 Maximum rating

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit
V
VCC to GND and PGND, OCH, PGOOD -0.3 to 18 V
CC
V
BOOT -
V
PHASE
V
HGATE -
V
PHASE
V
BOOT
Boot voltage 0 to 6 V
0 to V
BOOT
- V
PHASE
V
BOOT -0.3 to 24 V
PHASE -1 to 18
V
PHASE
PHASE spike, transient < 50 ns (F
SS, FB, DDR-IN, SYNC, VTTREF, OCL, LGATE, COMP, V
OCH pin
Maximum withstanding voltage range test condition: CDF-AEC-Q100-002 “human body
Other pins ±2000
model” acceptance criteria: “normal performance”

2.2 Thermal data

Table 3. Thermal data
Symbol Description Value Unit
(1)
R
thJA
T
STG
T
T
1. Package mounted on demonstration board
Thermal resistance junction to ambient 50 °C/W
Storage temperature range -40 to 150 °C
Junction operating temperature range -40 to 125 °C
J
Ambient operating temperature range -40 to +85 °C
A
CCDR
= 500 kHz)
SW
-3
+24
-0.3 to 6 V
±1500
V
VPGOOD pin ±1000
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Pin connections and functions L6731D

3 Pin connections and functions

Figure 2. Pin connection (top view)

PGOOD
VTTREF
SGND
FB
COMP
SS/INH
DDR-IN
OCL
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
HTSSOP16

Table 4. Pin functions

Pin n. Name Function
This pin is an open collector output and it is pulled low if the output voltage
1 PGOOD
2 V
TTREF
3 SGND All the internal references are referred to this pin.
4 FB
is not within the specified thresholds (90 %-110 %). If not used it may be left floating. Pull-up this pin to V
with a 10 K resistor to obtain a logical
CCDR
signal.
This pin is connected to the output of an internal buffer that provides ½ of DDR-IN. This pin can be connected to the V memory itself. Filter to GND with 10 nF capacitor.
This pin is connected to the error amplifier inverting input. Connect it to
through the compensation network. This pin is also used to sense the
V
OUT
output voltage in order to manage the over voltage conditions and the PGood signal.
VCC
VCCDR
LGATE
PGND
BOOT
HGATE
PHASE
OCH
TTREF
input of the DDR
5 COMP
This pin is connected to the error amplifier output and is used to compensate the voltage control feedback loop.
The soft-start time is programmed connecting an external capacitor from
6 SS/INH
this pin and GND. The internal current generator forces a current of 10 µA through the capacitor. When the voltage at this pin is lower than 0.5 V the device is disabled.
By setting the voltage at this pin is possible to select the internal/external reference and the switching frequency:
0-80 % of V
V
EAREF
7 DDR-IN
V V
= 80 %-95 % of V
EAREF
= 95 %-100 % of V
EAREF
An internal clamp limits the maximum V captures the analog value present at this pin at the start-up when VCC meets the UVLO threshold.
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-> External reference/F
CCDR
-> V
CCDR
CCDR -> VREF
REF
= 250 kHz
SW
= 0.6 V/F
= 0.6 V/F
EAREF
= 500 kHz
SW
= 250 kHz
SW
at 2.5 V (typ.). The device
L6731D Pin connections and functions
Table 4. Pin functions (continued)
Pin n. Name Function
A resistor connected from this pin to ground sets the valley- current-limit. The valley current is sensed through the low-side MOSFET(s). The internal current generator sources a current of 100 µA (I through the external resistor (R
). The over-current threshold is given by
OCL
the following equation:
I
8 OCL
I
VALLEY
OCLROCL
----------------------------------=
2R
DSONLS
Connecting a capacitor from this pin to GND helps in reducing the noise injected from VCC to the device, but can be a low impedance path for the high-frequency noise related to the GND. Connect a capacitor only to a "clean" GND.
A resistor connected from this pin and the high-side MOSFET(s) drain sets the peak-current-limit. The peak current is sensed through the high-side MOSFET(s). The internal 100 µA current generator (I
9 OCH
from the drain through the external resistor (R threshold is given by the following equation:
I
I
PEAK
OCHROCH
--------------------------------- -=
R
DSONHS
This pin is connected to the source of the high-side MOSFET(s) and
10 PHASE
provides the return path for the high-side driver. This pin monitors the drop across both the upper and lower MOSFET(s) for the current limit together with OCH and OCL.
11 HGATE This pin is connected to the high-side MOSFET(s) gate.
Through this pin is supplied the high-side driver. Connect a capacitor from
12 BOOT
this pin to the PHASE pin and a diode from V versus BOOT).
13 PGND
This pin has to be connected closely to the low-side MOSFET(s) source in order to reduce the noise injection into the device.
14 LGATE This pin is connected to the low-side MOSFET(s) gate.
15 V
16 V
CCDR
CC
5 V internally regulated voltage. It is used to supply the internal drivers. Filter it to ground with at least 1 µF ceramic cap.
Supply voltage pin. The operative supply voltage range is from 4.5 V to 14 V.
) from this pin to ground
OCL
) sinks a current
OCH
). The over-current
OCH
to this pin (cathode
CCDR
7/23
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