The controller is an integrated circuit realized in BCD5 (BiCMOS-DMOS, version 5)
fabrication that provides complete control logic and protection for high performance
step-down DC-DC and niPoL converters.
It is designed to drive N-channel MOSFETs in a synchronous rectified buck topology. The
output voltage of the converter can be precisely regulated down to 600 mV with a maximum
tolerance of ±0.8 %. If an external reference is used, it will be transferred divided by 2 to the
N.I. input of the error-amplifier, in accordance to the DDR memory specifications.
An internal resistor divider and a voltage buffer allow to achieve an accuracy of 1 % on both
Vtt and Vttref. It's possible to provide an external reference from 0V to 2.5 V in order to meet
the specification for DDRI and DDRII. The input voltage can range from 1.8 V to 14 V, while
the supply voltage can range from 4.5 V to 14 V. High peak current gate drivers provide for
fast switching to the external power section, and the output current can be in excess of 20 A.
The PWM duty cycle can range from 0 % to 100 % with a minimum on-time (T
than 100 ns making possible conversions with very low duty cycle at high switching
frequency. The device provides voltage-mode control that includes a selectable frequency
oscillator (250 kHz or 500 kHz).
The error amplifier features a 10 MHz gain-bandwidth-product and 5 V/µs slew-rate that
permits to realize high converter bandwidth for fast transient response. The device monitors
the current by using the R
the need for a current sensing resistor and guaranteeing an effective over-current-protection
in all the application conditions.
When necessary, two different current limit protections can be externally set through two
external resistors. During the soft-start phase a constant current protection is provided while
after the soft-start the device enters in hiccup mode in case of over-current. The converter
can always sink current. Other features are power good, not latched over-voltage-protection,
feed-back disconnection and thermal shutdown. The HTSSOP16 package allows the
realization of really compact DC/DC converters.
of both the high-side and low-side MOSFET(s), eliminating
DS(on)
ON, MIN
) lower
3/23
Summary descriptionL6731D
1.1 Functional description
Figure 1.Block diagram
VCC=4.5V to14V
V
=1.8V to14V
in
SS/INH
DDR-IN
PGOOD
OCL
OCH
Monitor
Protection and Ref
OSC
R
0.6V
+
R
-
+
-
VTTREF
LDO
L6731D
-
+
COMP
VCC
PWM
+
VCCDR
BOOT
HGATE
PHASE
LGATE
PGND
E/A
-
SGND
VFB
Vo
4/23
L6731DElectrical data
2 Electrical data
2.1 Maximum rating
Table 2.Absolute maximum ratings
Symbol Parameter Value Unit
V
VCC to GND and PGND, OCH, PGOOD-0.3 to 18V
CC
V
BOOT -
V
PHASE
V
HGATE -
V
PHASE
V
BOOT
Boot voltage0 to 6V
0 to V
BOOT
- V
PHASE
V
BOOT-0.3 to 24V
PHASE-1 to 18
V
PHASE
PHASE spike, transient < 50 ns (F
SS, FB, DDR-IN, SYNC, VTTREF, OCL, LGATE,
COMP, V
OCH pin
Maximum withstanding voltage range
test condition: CDF-AEC-Q100-002 “human body
Other pins±2000
model” acceptance criteria: “normal performance”
2.2 Thermal data
Table 3.Thermal data
SymbolDescriptionValueUnit
(1)
R
thJA
T
STG
T
T
1. Package mounted on demonstration board
Thermal resistance junction to ambient50°C/W
Storage temperature range-40 to 150°C
Junction operating temperature range-40 to 125°C
J
Ambient operating temperature range-40 to +85°C
A
CCDR
= 500 kHz)
SW
-3
+24
-0.3 to 6V
±1500
V
VPGOOD pin±1000
5/23
Pin connections and functionsL6731D
3 Pin connections and functions
Figure 2.Pin connection (top view)
PGOOD
VTTREF
SGND
FB
COMP
SS/INH
DDR-IN
OCL
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
HTSSOP16
Table 4.Pin functions
Pin n.Name Function
This pin is an open collector output and it is pulled low if the output voltage
1 PGOOD
2 V
TTREF
3 SGNDAll the internal references are referred to this pin.
4 FB
is not within the specified thresholds (90 %-110 %). If not used it may be left
floating. Pull-up this pin to V
with a 10 K resistor to obtain a logical
CCDR
signal.
This pin is connected to the output of an internal buffer that provides ½ of
DDR-IN. This pin can be connected to the V
memory itself. Filter to GND with 10 nF capacitor.
This pin is connected to the error amplifier inverting input. Connect it to
through the compensation network. This pin is also used to sense the
V
OUT
output voltage in order to manage the over voltage conditions and the
PGood signal.
VCC
VCCDR
LGATE
PGND
BOOT
HGATE
PHASE
OCH
TTREF
input of the DDR
5 COMP
This pin is connected to the error amplifier output and is used to
compensate the voltage control feedback loop.
The soft-start time is programmed connecting an external capacitor from
6 SS/INH
this pin and GND. The internal current generator forces a current of 10 µA
through the capacitor. When the voltage at this pin is lower than 0.5 V the
device is disabled.
By setting the voltage at this pin is possible to select the internal/external
reference and the switching frequency:
0-80 % of V
V
EAREF
7 DDR-IN
V
V
= 80 %-95 % of V
EAREF
= 95 %-100 % of V
EAREF
An internal clamp limits the maximum V
captures the analog value present at this pin at the start-up when VCC
meets the UVLO threshold.
6/23
-> External reference/F
CCDR
-> V
CCDR
CCDR -> VREF
REF
= 250 kHz
SW
= 0.6 V/F
= 0.6 V/F
EAREF
= 500 kHz
SW
= 250 kHz
SW
at 2.5 V (typ.). The device
L6731DPin connections and functions
Table 4.Pin functions (continued)
Pin n.Name Function
A resistor connected from this pin to ground sets the valley- current-limit.
The valley current is sensed through the low-side MOSFET(s). The internal
current generator sources a current of 100 µA (I
through the external resistor (R
). The over-current threshold is given by
OCL
the following equation:
I
•
8 OCL
I
VALLEY
OCLROCL
----------------------------------=
•
2R
DSONLS
Connecting a capacitor from this pin to GND helps in reducing the noise
injected from VCC to the device, but can be a low impedance path for the
high-frequency noise related to the GND. Connect a capacitor only to a
"clean" GND.
A resistor connected from this pin and the high-side MOSFET(s) drain sets
the peak-current-limit. The peak current is sensed through the high-side
MOSFET(s). The internal 100 µA current generator (I
9 OCH
from the drain through the external resistor (R
threshold is given by the following equation:
I
•
I
PEAK
OCHROCH
--------------------------------- -=
R
DSONHS
This pin is connected to the source of the high-side MOSFET(s) and
10 PHASE
provides the return path for the high-side driver. This pin monitors the drop
across both the upper and lower MOSFET(s) for the current limit together
with OCH and OCL.
11 HGATEThis pin is connected to the high-side MOSFET(s) gate.
Through this pin is supplied the high-side driver. Connect a capacitor from
12 BOOT
this pin to the PHASE pin and a diode from V
versus BOOT).
13 PGND
This pin has to be connected closely to the low-side MOSFET(s) source in
order to reduce the noise injection into the device.
14 LGATEThis pin is connected to the low-side MOSFET(s) gate.
15 V
16 V
CCDR
CC
5 V internally regulated voltage. It is used to supply the internal drivers.
Filter it to ground with at least 1 µF ceramic cap.
Supply voltage pin.
The operative supply voltage range is from 4.5 V to 14 V.
) from this pin to ground
OCL
) sinks a current
OCH
). The over-current
OCH
to this pin (cathode
CCDR
7/23
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