ST L6731D User Manual

Adjustable step-down controller with synchronous rectification

Features

■ Input voltage range from 1.8 V to 14 V

■ Supply voltage range from 4.5 V to 14 V

■ Adjustable output voltage down to 0.6 V with

±0.8 % Accuracy over line voltage and
temperature (0 °C~125 °C)

■ Fixed frequency voltage mode control

■ T

■ 0 % to 100 % duty cycle

■ V

■ Regulates V

■

■ High current embedded drivers

■ Predictive anti-cross conduction control

■ Programmable high-side and low-side R

■ Selectable switching frequency 250 kHz /

■ Power good output

■ Sink/source capability for DDR memory and

■ Over-voltage protection

■ Thermal shutdown

■ Package: HTSSOP16

lower than 100 ns

ON

input sense

DDR

and V

TT

within 1 % of V

TTREF

Soft-start and inhibit

sense over-current-protection

500 kHz

termination supply

DDQ

DS(on)

dedicated to DDR memory

HTSSOP16 (exposed pad)

Applications

■ High performance / high density DC-DC

modules

■ Low voltage distributed DC-DC

■ niPoL converters

■ DDR memory supply

■ DDR termination supply

■ Graphic cards

L6731D

Table 1. Device summary

Order codes Package Packaging

L6731D HTSSOP16 Tube

L6731DTR HTSSOP16 Tape and reel

June 2008 Rev 3 1/23

www.st.com

23

Contents L6731D

Contents

1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Pin connections and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.2 Internal LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.3 Bypassing the LDO to avoid the voltage drop with low Vcc . . . . . . . . . . . 11

5.4 Internal and external references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.5 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.6 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.7 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.8 Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.9 HICCUP mode during an OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.10 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.11 Minimum on-time (TON, MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.1 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.2 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.3 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2/23

L6731D Summary description

1 Summary description

The controller is an integrated circuit realized in BCD5 (BiCMOS-DMOS, version 5)
fabrication that provides complete control logic and protection for high performance
step-down DC-DC and niPoL converters.

It is designed to drive N-channel MOSFETs in a synchronous rectified buck topology. The
output voltage of the converter can be precisely regulated down to 600 mV with a maximum
tolerance of ±0.8 %. If an external reference is used, it will be transferred divided by 2 to the
N.I. input of the error-amplifier, in accordance to the DDR memory specifications.

An internal resistor divider and a voltage buffer allow to achieve an accuracy of 1 % on both
Vtt and Vttref. It's possible to provide an external reference from 0V to 2.5 V in order to meet
the specification for DDRI and DDRII. The input voltage can range from 1.8 V to 14 V, while
the supply voltage can range from 4.5 V to 14 V. High peak current gate drivers provide for
fast switching to the external power section, and the output current can be in excess of 20 A.

The PWM duty cycle can range from 0 % to 100 % with a minimum on-time (T
than 100 ns making possible conversions with very low duty cycle at high switching
frequency. The device provides voltage-mode control that includes a selectable frequency
oscillator (250 kHz or 500 kHz).

The error amplifier features a 10 MHz gain-bandwidth-product and 5 V/µs slew-rate that
permits to realize high converter bandwidth for fast transient response. The device monitors
the current by using the R
the need for a current sensing resistor and guaranteeing an effective over-current-protection
in all the application conditions.

When necessary, two different current limit protections can be externally set through two
external resistors. During the soft-start phase a constant current protection is provided while
after the soft-start the device enters in hiccup mode in case of over-current. The converter
can always sink current. Other features are power good, not latched over-voltage-protection,
feed-back disconnection and thermal shutdown. The HTSSOP16 package allows the
realization of really compact DC/DC converters.

of both the high-side and low-side MOSFET(s), eliminating

DS(on)

ON, MIN

) lower

3/23

Summary description L6731D

1.1 Functional description

Figure 1. Block diagram

VCC=4.5V to14V

V

=1.8V to14V

in

SS/INH

DDR-IN

PGOOD

OCL

OCH

Monitor

Protection and Ref

OSC

R

0.6V

+

R

-

+

-

VTTREF

LDO

L6731D

-

+

COMP

VCC

PWM

+

VCCDR

BOOT

HGATE

­PHASE

LGATE

PGND

E/A

-

SGND

VFB

Vo

4/23

L6731D Electrical data

2 Electrical data

2.1 Maximum rating

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

V

VCC to GND and PGND, OCH, PGOOD -0.3 to 18 V

CC

V

BOOT -

V

PHASE

V

HGATE -

V

PHASE

V

BOOT

Boot voltage 0 to 6 V

0 to V

BOOT

- V

PHASE

V

BOOT -0.3 to 24 V

PHASE -1 to 18

V

PHASE

PHASE spike, transient < 50 ns (F

SS, FB, DDR-IN, SYNC, VTTREF, OCL, LGATE,
COMP, V

OCH pin

Maximum withstanding voltage range
test condition: CDF-AEC-Q100-002 “human body

Other pins ±2000

model” acceptance criteria: “normal performance”

2.2 Thermal data

Table 3. Thermal data

Symbol Description Value Unit

(1)

R

thJA

T

STG

T

T

1. Package mounted on demonstration board

Thermal resistance junction to ambient 50 °C/W

Storage temperature range -40 to 150 °C

Junction operating temperature range -40 to 125 °C

J

Ambient operating temperature range -40 to +85 °C

A

CCDR

= 500 kHz)

SW

-3

+24

-0.3 to 6 V

±1500

V

VPGOOD pin ±1000

5/23

Pin connections and functions L6731D

3 Pin connections and functions

Figure 2. Pin connection (top view)

PGOOD

VTTREF

SGND

FB

COMP

SS/INH

DDR-IN

OCL

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

HTSSOP16

Table 4. Pin functions

Pin n. Name Function

This pin is an open collector output and it is pulled low if the output voltage

1 PGOOD

2 V

TTREF

3 SGND All the internal references are referred to this pin.

4 FB

is not within the specified thresholds (90 %-110 %). If not used it may be left
floating. Pull-up this pin to V

with a 10 K resistor to obtain a logical

CCDR

signal.

This pin is connected to the output of an internal buffer that provides ½ of
DDR-IN. This pin can be connected to the V
memory itself. Filter to GND with 10 nF capacitor.

This pin is connected to the error amplifier inverting input. Connect it to

through the compensation network. This pin is also used to sense the

V

OUT

output voltage in order to manage the over voltage conditions and the
PGood signal.

VCC

VCCDR

LGATE

PGND

BOOT

HGATE

PHASE

OCH

TTREF

input of the DDR

5 COMP

This pin is connected to the error amplifier output and is used to
compensate the voltage control feedback loop.

The soft-start time is programmed connecting an external capacitor from

6 SS/INH

this pin and GND. The internal current generator forces a current of 10 µA
through the capacitor. When the voltage at this pin is lower than 0.5 V the
device is disabled.

By setting the voltage at this pin is possible to select the internal/external
reference and the switching frequency:

0-80 % of V

V

EAREF

7 DDR-IN

V
V

= 80 %-95 % of V

EAREF

= 95 %-100 % of V

EAREF

An internal clamp limits the maximum V
captures the analog value present at this pin at the start-up when VCC
meets the UVLO threshold.

6/23

-> External reference/F

CCDR

-> V

CCDR

CCDR -> VREF

REF

= 250 kHz

SW

= 0.6 V/F

= 0.6 V/F

EAREF

= 500 kHz

SW

= 250 kHz

SW

at 2.5 V (typ.). The device

L6731D Pin connections and functions

Table 4. Pin functions (continued)

Pin n. Name Function

A resistor connected from this pin to ground sets the valley- current-limit.
The valley current is sensed through the low-side MOSFET(s). The internal
current generator sources a current of 100 µA (I
through the external resistor (R

). The over-current threshold is given by

OCL

the following equation:

I

•

8 OCL

I

VALLEY

OCLROCL

----------------------------------=

•

2R

DSONLS

Connecting a capacitor from this pin to GND helps in reducing the noise
injected from VCC to the device, but can be a low impedance path for the
high-frequency noise related to the GND. Connect a capacitor only to a
"clean" GND.

A resistor connected from this pin and the high-side MOSFET(s) drain sets
the peak-current-limit. The peak current is sensed through the high-side
MOSFET(s). The internal 100 µA current generator (I

9 OCH

from the drain through the external resistor (R
threshold is given by the following equation:

I

•

I

PEAK

OCHROCH

--------------------------------- -=

R

DSONHS

This pin is connected to the source of the high-side MOSFET(s) and

10 PHASE

provides the return path for the high-side driver. This pin monitors the drop
across both the upper and lower MOSFET(s) for the current limit together
with OCH and OCL.

11 HGATE This pin is connected to the high-side MOSFET(s) gate.

Through this pin is supplied the high-side driver. Connect a capacitor from

12 BOOT

this pin to the PHASE pin and a diode from V
versus BOOT).

13 PGND

This pin has to be connected closely to the low-side MOSFET(s) source in
order to reduce the noise injection into the device.

14 LGATE This pin is connected to the low-side MOSFET(s) gate.

15 V

16 V

CCDR

CC

5 V internally regulated voltage. It is used to supply the internal drivers.
Filter it to ground with at least 1 µF ceramic cap.

Supply voltage pin.
The operative supply voltage range is from 4.5 V to 14 V.

) from this pin to ground

OCL

) sinks a current

OCH

). The over-current

OCH

to this pin (cathode

CCDR

7/23

Electrical characteristics L6731D

4 Electrical characteristics

V

= 12 V, TA = 25 °C unless otherwise specified.

CC

Table 5. Electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit

V

supply current

CC

VCC stand by current OSC = open; SS to GND 4.5 6.5

I

CC

quiescent current

V

CC

Power-ON

V

CC

Tu r n -O N VCC threshold V

Tu r n -O F F V

Tu r n -O N V

Tu r n -O F F V

V

CCDR

V

CCDR

V

IN OK

V

IN OK

regulation

Soft-start and inhibit

I

SS

Soft start current

Oscillator

∆V

f

OSC

OSC

Accuracy

Ramp amplitude 2.1 V

Output voltage

CC

OCH

OCH

voltage

OSC= open;
HG = open, LG = open,

8.5 10

mA

PH = open

= 1.7 V 4.0 4.2 4.4 V

OCH

threshold V

= 1.7 V 3.6 3.8 4.0 V

OCH

threshold 1.1 1.25 1.47 V

threshold 0.9 1.05 1.27 V

VCC =5.5 V to 14 V
IDR = 1 mA to 100 mA

4.555.5V

SS = 2 V 7 10 13

SS = 0 to 0.5 V 20 30 45

237 250 263 kHz

450 500 550 kHz

µA

V

FB

Output voltage V

= 0 to Vth 0.597 0.6 0.603 V

DIS

Error amplifier

R

EAREF

I

FB

Ext Ref

Clamp

V

OFFSET

G

V

EAREF input resistance Vs. GND 70 100 150 kΩ

I.I. bias current VFΒ = 0 V 0.290 0.5 µA

2.3 V

Error amplifier offset Vref = 0.6 V -5 +5 mV

Open loop voltage gain Guaranteed by design 100 dB

GBWP Gain-bandwidth product Guaranteed by design 10 MHz

SR Slew-rate

COMP = 10 pF
Guaranteed by design

5V/µs

8/23

L6731D Electrical characteristics

Table 5. Electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit

Gate drivers

R

HGATE_ON

R

HGATE_OFF

R

LGATE_ON

R

LGATE_OFF

Protections

I

OCH

I

OCL

OVP

Power good

V

BPGOODB

High side source resistance V

High side sink resistance V

Low side source resistance V

Low side sink resistance V

OCH current source V

- V

BOOT

- V

BOOT

= 5 V 1.15 Ω

CCDR

= 5 V 0.6 Ω

CCDR

= 1.7 V 90 100 110 µΑ

OCH

= 5 V 1.7 Ω

PHASE

= 5 V 1.12 Ω

PHASE

OCL current source 90 100 110 µΑ

rising

V

Over voltage trip
(VFB / VEAREF)

Under voltage threshold
(V

B

FB

/ VB

B

EAREF

)

B

Upper threshold
(V

B

FB

/ VB

B

EAREF

)

B

Lower threshold
(V

B

FB

/ VB

B

EAREF

)

B

PGOOD voltage low IB

FB

= 0.6 V

V

EAREF

V

falling

FB

V

= 0.6 V

EAREF

VB

falling 80 %

B

FB

VB

rising 108 110 112 %

B

FB

VB

falling 88 90 92 %

B

FB

= -5 mA 0.5 V

B

PGOOD

120 %

117 %

Table 6. Thermal characteristics (VCC = 12 V)

Symbol Parameter Test condition Min Typ Max Unit

Output voltage

= 0 °C~ 125 °C 0.596 0.6 0.605

T

V

FB

Output voltage

J

= -40 °C~ 125 °C 0.593 0.6 0.605

T

J

9/23

V

Device description L6731D

5 Device description

5.1 Oscillator

The switching frequency can be fixed to two values: 250 kHz or 500 kHz by setting the
proper voltage at the EAREF pin (see Table 4. Pins function and section 4.3 Internal and
external reference).

5.2 Internal LDO

An internal LDO supplies the internal circuitry of the device. The input of this stage is the
V

pin and the output (5 V) is the V

CC

Figure 3. LDO block diagram

pin (Figure 3.).

CCDR

4.5V÷14V

The LDO can be by-passed, providing directly a 5 V voltage to V
V

pins must be shorted together as shown in Figure 4. V

CCDR

LDO

. In this case VCC and

CCDR

pin must be filtered with

CCDR

at least 1 µF capacitor to sustain the internal LDO during the recharge of the bootstrap
capacitor. V

also represents a voltage reference for PGOOD pin (see Table 4. Pins

CCDR

Function).

10/23

L6731D Device description

5.3 Bypassing the LDO to avoid the voltage drop with low Vcc

If V

≈ 5 V the internal LDO works in dropout with an output resistance of about 1 Ω. The

CC

maximum LDO output current is about 100 mA and so the output voltage drop is 100 mV, to
avoid this the LDO can be bypassed.

Figure 4. Bypassing the LDO

5.4 Internal and external references

It is possible to set the internal/external reference and the switching frequency by setting the
proper voltage at the DDR-IN pin. The maximum value of the external reference is 2.5 V
(typ.):

● V

● V

● V

Providing an external reference from 0V to 450mV the output voltage will be regulated but
some restrictions must be considered:

● OV threshold saturates to a minimum value of 300 mV (OV is tracking the

reference; tracking small references will result in a narrow threshold reducing
noise immunity)

● The under-voltage-protection doesn't work;

● The PGOOD signal remains low;

To set the resistor divider it must be considered that a 100 k pull-down resistor is integrated
into the device (see Figure 5.). Finally it must be taken into account that the voltage at the
DDR-IN pin is captured by the device at the start-up when V

from 0 % to 80 % of V

EAREF

from 80 % to 95 % of V

EAREF

from 95 % to 100 % of V

EAREF

CCDR

CCDR

-> External reference/FSW = 250 kHz

CCDR

-> V

-> V

REF

REF

= 0.6 V/F

SW

= 0.6 V/F

is about 4 V.

CC

= 500 kHz

= 250 kHz

SW

11/23

Device description L6731D

V

V

V

V

V

5.5 Error amplifier

Figure 5. Error amplifier reference

CCDR

0.6V/500KHz

5.6 Soft-start

When both VCC and VIN are above their turn-ON thresholds (VIN is monitored by the OCH
pin) the start-up phase takes place. Otherwise the SS pin is internally shorted to GND. At
start-up, a ramp is generated charging the external capacitor C
generator. The initial value for this current is 35 µA and charges the capacitor up to 0.5V.
After that it becomes 10 µA until the final charge value of approximately 4 V (see Figure 6.).

Figure 6. Device start-up: voltage at the SS pin

DDR-IN

100K

0.6V/250KHz

DDR-IN/2
250KHz

2.5

Error Amplifier Ref.

with an internal current

SS

ss

12/23

0.5V

4V

4.2V

1.25V

cc

in

V

CC

V

IN

t

t

L6731D Device description

The reference of the error amplifier is clamped with this voltage (Vss) until it reaches the
programmed value. The L6731D can always sink or source current. If an over current is
detected during the soft-start phase, the device provides a constant-current-protection. In
this way, in case of short soft-start time and/or small inductor value and/or high output
capacitors value and so, in case of high ripple current during the soft-start, the converter can
start in any case, limiting the current (see 5.8: Monitoring and protections) but not entering
in HICCUP mode. During normal operation, if any under-voltage is detected on one of the
two supplies, the SS pin is internally shorted to GND and so the SS capacitor is rapidly
discharged.

5.7 Driver section

The high-side and low-side drivers allow using different types of power MOSFETs (also
multiple MOSFETs to reduce the R
side driver is supplied by V

while the high-side driver is supplied by the BOOT pin. A

CCDR

predictive dead time control avoids MOSFETs cross-conduction maintaining very short
dead time duration in the range of 20 ns. The control monitors the phase node in order to
sense the low-side body diode recirculation. If the phase node voltage is less than a certain
threshold (-350 mV typ.) during the dead time, it will be reduced in the next PWM cycle. The
predictive dead time control does not work when the high-side body diode is conducting
because the phase node does not go negative. This situation happens when the converter
is sinking current for example and, in this case, an adaptive dead time control operates.

), maintaining fast switching transitions. The low-

DS(on)

5.8 Monitoring and protections

The output voltage is monitored by means of pin FB. If it is not within ±10 % (typ.) of the
programmed value, the power good (PGOOD) output is forced low. The device provides
over-voltage-protection: when the voltage sensed on FB pin reaches a value 20 % (typ.)
greater than the reference, the low-side driver is turned on as long as the over voltage is
detected (see Figure 7.).

Figure 7. OVP

LGate

FB

It must be taken into account that there is an electrical network between the output terminal
and the FB pin and therefore the voltage at the pin is not a perfect replica of the output
voltage. However due to the fact that the converter can sink current, in the most of cases the

13/23

Device description L6731D

low-side will turn-on before the output voltage exceeds the over-voltage threshold, because
the error amplifier will throw off balance in advance. Even if the device doesn't report an
over-voltage, the behavior is the same, because the low-side is turned-on immediately. The
following figure shows the device behavior during an over-voltage event. The output voltage
rises with a slope of 100 mV/µs, emulating in this way the breaking of the high-side
MOSFET as an over-voltage cause.

Figure 8. OVP: the low-side MOSFET is turned-on in advance

V

OUT

109%

V

FB

LGate

The device realizes the over-current-protection (OCP) sensing the current both on the high­side MOSFET(s) and the low-side MOSFET(s) and so 2 current limit thresholds can be set
(see OCH pin and OCL pin in Table 4. Pins function):

● Peak current limit

● Valley current limit

The peak current protection is active when the high-side MOSFET(s) is turned on, after a
masking time of about 100 ns. The valley-current-protection is enabled when the low-side
MOSFET(s) is turned on after a masking time of about 400 ns. If, when the soft-start phase
is completed, an over current event occurs during the on time (peak-current-protection) or
during the off time (valley-current-protection) the device enters in HICCUP mode: the high­side and low-side MOSFET(s) are turned OFF, the soft-start capacitor is discharged with a
constant current of 10 µA and when the voltage at the SS pin reaches 0.5 V the soft-start
phase restarts. During the soft-start phase the OCP provides a constant-current-protection.
If during the T

the OCH comparator triggers an over current the high-side MOSFET(s) is

ON

immediately turned OFF (after the masking time and the internal delay) and returned on at
the next PWM cycle. The limit of this protection is that the T

can't be less than masking

ON

time plus propagation delay because during the masking time the peak-current-protection is
disabled. In case of very hard short circuit, even with this short T

, the current could

ON

escalate.

The valley-current-protection is very helpful in this case to limit the current. If during the off­time the OCL comparator triggers an over current, the high-side MOSFET(s) is not turned
on until the current is over the valley-current-limit.

This implies that, if it is necessary, some pulses of the high-side MOSFET(s) will be skipped,
guaranteeing a maximum current due to the following formula:

14/23

L6731D Device description

−

Equation 1

VoutVin

II

+=

L

During soft-start the OC acts in constant current mode: a current control loop limits the value
of the error amplifier output (comp), in order to avoid its saturation and thus recover faster
when the output returns in regulation. Figure 9. shows the behavior of the device during an
over current condition that persists also in the soft-start phase.

L6732 provides Under Voltage (UV) protection: when the voltage on FB pin falls below 80%
of the reference, the IC will enter HICCUP mode.

Feedback disconnection is also provided by sourcing a 100 nA current from FB pin. if FB
results being floating, the IC will detect and OV so latching its condition with low side
MOSFET firmly ON.

T

⋅

MINONVALLEYMAX

,

5.9 HICCUP mode during an OCP

Figure 9. Constant current and hiccup mode during an OCP

VSS

5.10 Thermal shutdown

When the junction temperature reaches 150 °C ±10 °C the device enters in thermal
shutdown. Both MOSFETs are turned off and the soft-start capacitor is rapidly discharged
with an internal switch. The device doesn't restart until the junction temperature goes down
to 120 °C and, in any case, until the voltage at the soft-start pin reaches 500 mV.

5.11 Minimum on-time (TON,

The device can manage minimum on-times lower than 100ns. This feature comes down
from the control topology and from the particular over-current-protection system of the
L6731D. In fact, in a voltage mode controller the current has not to be sensed to perform the
regulation and, in the case of L6731D, neither for the over-current protection, given that

MIN

VCOMP

I

L

)

15/23

Device description L6731D

during the off-time the valley-current-protection can operate in every case. The first
advantage related to this feature is the possibility to realize extremely low conversion ratios.

Figure 10. shows a conversion from 14 V to 0.3 V at 500 kHz with a T

Figure 10. 14 V -> 0.3 V @ 500 kHz, 5 A

of about 50 ns.

ON

V

OUT

I

L

VPHASE

50ns

The on-time is limited by the turn-on and turn-off times of the MOSFETs.

16/23

L6731D Application details

−

⋅∆=

∆

6 Application details

6.1 Inductor design

The inductance value is defined by a compromise between the transient response time, the
efficiency, the cost and the size. The inductor has to be calculated to sustain the output and
the input voltage variation to maintain the ripple current (∆I
maximum output current. The inductance value can be calculated with the following
relationship:

Equation 2

Vout

L

≅

Where F
voltage. Increasing the value of the inductance reduces the ripple current but, at the same
time, increases the converter response time to a load transient. If the compensation network
is well designed, during a load transient the device is able to set the duty cycle to 100 % or
to 0 %. When one of these conditions is reached, the response time is limited by the time
required to change the inductor current. During this time the output current is supplied by
the output capacitors. Minimizing the response time can minimize the output capacitor size.

is the switching frequency, Vin is the input voltage and Vout is the output

SW

VoutVin

⋅

∆⋅

IFsw

L

) between 20 % and 30 % of the

L

Vin

6.2 Output capacitors

The output capacitors are basic components for the fast transient response of the power
supply. They depend on the output voltage ripple requirements, as well as any output
voltage deviation requirement during a load transient. During a load transient, the output
capacitors supply the current to the load or absorb the current stored in the inductor until the
converter reacts. In fact, even if the controller recognizes immediately the load transient and
sets the duty cycle at 100 % or 0 %, the current slope is limited by the inductor value. The
output voltage has a first drop due to the current variation inside the capacitor (neglecting
the effect of the ESL):

Equation 3

Moreover, there is an additional drop due to the effective capacitor discharge or charge that
is given by the following formulas:

Equation 4

Vout

Equation 5

Formula (4) is valid in case of positive load transient while the formula (5) is valid in case of
negative load transient. D

ESR

=∆

COUT

COUT

=∆

2

Vout

is the maximum duty cycle value that in the L6731D is 100%.

MAX

ESRIoutVout

2

LIout

⋅∆

)maxmin,(2

VoutDVinCout

−⋅⋅⋅

2

⋅∆

LIout

VoutCout

⋅⋅

17/23

Application details L6731D

For a given inductor value, minimum input voltage, output voltage and maximum load
transient, a maximum ESR and a minimum Cout value can be set. The ESR and Cout
values also affect the static output voltage ripple. In the worst case the output voltage ripple
can be calculated with the following formula:

Equation 6

(

ESRIVout

L

Usually the voltage drop due to the ESR is the biggest one while the drop due to the
capacitor discharge is almost negligible.

+⋅∆=∆

1

8

)

FswCout

⋅⋅

6.3 Input capacitors

The input capacitors have to sustain the RMS current flowing through them, that is:

Equation 7

)1( DDIoutIrms −⋅⋅=

Where D is the duty cycle. The equation reaches its maximum value, I
The losses in worst case are:

Equation 8

6.4 Compensation network

The loop is based on a voltage mode control (Figure 18.). The output voltage is regulated to
the internal/external reference voltage and scaled by the external resistor divider. The error
amplifier output V
pulse-width modulated (PWM) with an amplitude of V
is filtered by the output filter. The modulator transfer function is the small signal transfer
function of V
L-C

OUT

Gain of the modulator is simply the input voltage V
voltage: V

OUT/VCOMP

resonance and a zero at FESR depending on the output capacitor's ESR. The DC

.

OSC

is then compared with the oscillator triangular wave to provide a

COMP

. This function has a double pole at frequency FLC depending on the

/2 with D = 0.5.

OUT

2

)5.0( IoutESRP ⋅⋅=

at the PHASE node. This waveform

IN

divided by the peak-to-peak oscillator

IN

18/23

L6731D Application details

Figure 11. Compensation network

The compensation network consists in the internal error amplifier, the impedance networks
Z

(R3, R4 and C20) and ZFB (R5, C18 and C19). The compensation network has to

IN

provide a closed loop transfer function with the highest 0 dB crossing frequency to have
fastest transient response (but always lower than fsw/10) and the highest gain in DC
conditions to minimize the load regulation error. A stable control loop has a gain crossing the
0 dB axis with -20 dB/decade slope and a phase margin greater than 45 °. To locate poles
and zeroes of the compensation networks, the following suggestions may be used:

● Modulator singularity frequencies:

Equation 9

Equation 10

● Compensation network singularity frequencies:

Equation 11

ω

ω

ω

=

LC

=

ESR

=

P

1

R

1

CoutL

⋅

1

CoutESR

⋅

1

⎛
⎜

⋅

5

⎜
⎝

⎞

⋅

CC

1918

⎟

⎟

+

CC

1918

⎠

19/23

Application details L6731D

Equation 12

Equation 13

Equation 14

● Compensation network design:

Equation 15

– Put the gain R

ω

P

2

ω

Z

1

ω

=

Z

2

in order to obtain the desired converter bandwidth

5/R3

R

5

R

3

1

=

⋅

CR

204

1

=

⋅

CR

195

1

()

+⋅

RRC

4320

Vin

ϖϖ

Vosc

⋅

LCC

⋅=

∆

ω

– Place

– Place

– Place

– Place

– Check the loop gain considering the error amplifier open loop gain.

Figure 12. Asymptotic bode plot of converter's open loop gain

before the output filter resonance ω

Z1

ω

at the output filter resonance ω

Z2

ω

at the output capacitor ESR zero ω

P1

ω

at one half of the switching frequency;

P2

LC

LC

;

ESR

;

;

20/23

L6731D Package mechanical data

7 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.

Figure 13. HTSSOP16 mechanical data

TSSOP16 EXPOSED PAD MECHANICAL DATA

DIM.

A 1.2 0.047

A1 0.15 0.004 0.006

A2 0.8 1 1.05 0.031 0.039 0.041

b 0.19 0.30 0.007 0.012

c 0.09 0.20 0.004 0.0089

D 4.9 5 5.1 0.193 0.197 0.201

D1 3.0 0.118

E 6.2 6.4 6.6 0.244 0.252 0.260

E1 4.3 4.4 4.5 0.169 0.173 0.177

E2 3.0 0.118

e 0.65 0.0256

K0° 8°0° 8°

L 0.4 5 0.60 0.75 0.018 0.024 0.030

MIN. TYP MA X. MIN. TYP. MAX.

2.8

2.8

mm. inch

3.1 1.102 1.220

3.1 1.102 1.220

7419276A

21/23

Revision history L6731D

8 Revision history

Table 7. Document revision history

Date Revision Changes

21-Dec-2005 1 Initial release.

31-May-2006 2 New template, thermal data updated

04-Jun-2008 3

Updated: Table 4 on page 6, Table 5 on page 8, Section 5.4 on page

11, Figure 13 on page 21

22/23

L6731D

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