ST L6730C, L6730D User Manual

Adjustable step-down controller with synchronous rectification

Features

■ Input voltage range from 1.8V to 14V

■ Supply voltage range from 4.5V to 14V

■ Adjustable output voltage down to 0.6V with

±0.8% accuracy over line voltage and
temperature (0°C~125°C)

■ Fixed frequency voltage mode control

■ T

■ 0% to 100% duty cycle

■ Selectable 0.6V or 1.2V internal voltage

■ External input voltage reference

■ Soft-start and inhibit

■ High current embedded drivers

■ Predictive anti-crossconduction control

■ Selectable UVLO threshold (5V or 12V bus)

■ Programmable high-side and low-side R

■ Switching frequency programmable from

■ Master/slave synchronization with 180° phase

■ Pre-bias start up capability (L6730C)

■ Selectable source/sink or source only

■ Selectable constant current or hiccup mode

lower than 100ns

ON

reference

DS(on)

sense over-current-protection

100KHz to 1MHz

shift

capability after soft-start (L6730C)

overcurrent protection after soft-start (L6730D)

L6730C
L6730D

Target Specification

HTSSOP20

■ Power good output with programmable delay

■ Over voltage protection with selectable

latched/not-latched mode

■ Thermal shut-down

■ Package: HTSSOP20, QFN4x4 24L

Applications

■ High performance / high density DC-DC

modules

■ Low voltage distributed DC-DC

■ niPOL converters

■ DDR memory supply

■ DDR memory bus termination supply

QFN 4x4 24L

Order Codes

Part number Package Packing

L6730CQ QFN4x4 24L Tube

L6730CQTR QFN4x4 24L Tape & Reel

L6730C HTSSOP20 Tube

L6730CTR HTSSOP20 Tape & Reel

L6730D HTSSOP20 Tube

L6730DTR HTSSOP20 Tape & Reel

June 2006 Rev 2 1/50

This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.

www.st.com

50

Contents L6730C - L6730D

Contents

1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Pin connections and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.2 Internal LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.3 Bypassing the LDO to avoid the voltage drop with low Vcc . . . . . . . . . . . . . 14

5.4 Internal and external references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.5 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.6 Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.7 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.8 Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.9 Adjustable masking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.10 Multifunction pin (S/O/U L6730C) (CC/O/U L6730D) . . . . . . . . . . . . . . . . . . 25

5.11 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.12 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.13 Minimum on-time (TON, MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.14 Bootstrap anti-discharging system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.14.1 Fan’s power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.14.2 No-sink at zero current operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2/50

L6730C - L6730D Contents

6 Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.1 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.2 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.3 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.5 Two quadrant or one quadrant operation mode (L6730C) . . . . . . . . . . . . . . 34

7 L6730 Demoboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.2 PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8 I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

10 POL Demoboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

10.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3/50

Summary description L6730C - L6730D

1 Summary description

The controller is an integrated circuit realized in BCD5 (BiCMOS-DMOS, version 5) fabrication
that provides complete control logic and protection for high performance step-down DC-DC and
niPOL converters.

It is designed to drive N-Channel MOSFETs in a synchronous rectified buck topology. The
output voltage of the converter can be precisely regulated down to 600mV with a maximum
tolerance of ±0.8% or to 1.2V, when one of the internal references is used. It is also possible to
use an external reference from 0V to 2.5V. The input voltage can range from 1.8V to 14V, while
the supply voltage can range from 4.5V to 14V. High peak current gate drivers provide for fast
switching to the external power section and the output current can be in excess of 20A,
depending on the number of the external MOSFETs used. The PWM duty cycle can range from
0% to 100% with a minimum on-time (T
with very low duty cycle and very high switching frequency.

The device provides voltage-mode control. It includes a 400KHz free-running oscillator that is
adjustable from 100KHz to 1MHz. The error amplifier features a 10MHz gain-bandwidth­product and 5V/µs slew-rate that permits to realize high converter bandwidth for fast transient
response. The device monitors the current by using the R
side MOSFET(s), eliminating the need for a current sensing resistor and guaranteeing an
effective over-current-protection in all the application conditions. When necessary, two different
current limit protections can be externally set through two external resistors. A leading edge
adjustable blanking time is also available to avoid false over-current-protection (OCP)
interventions in every application condition. It is possible to select the HICCUP mode or the
constant current protection (L6730D) after the soft-start phase.

ON, MIN

) lower than 100ns making possible conversions

of both the high-side and low-

DS(on)

During the soft-start phase a constant current protection is provided. It is possible to select
(before the device turn-on) the sink-source or the source-only mode capability by acting on a
multifunction pin (L6730C). The L6730C disables the sink mode capability during the soft-start
in order to allow a proper start-up also in pre-biased output voltage conditions. The L6730D can
always sink current and so it can be used to supply the DDR Memory BUS termination. Other
features are Master-Slave synchronization (with 180° phase shift), Power-Good with adjustable
delay, over-voltage-protection, feed-back disconnection, selectable UVLO threshold (5V and
12V Bus) and thermal shutdown. The HTSSOP20 package allows the realization of really
compact DC/DC converters.

4/50

L6730C - L6730D Summary description

1.1 Functional description

Figure 1. Block diagram

VCC=4.5V to14V

V

=1.8V to14V

in

SS/INH
SYNCH

OSC

EAREF

PGOOD

SINK/OVP/UVLO*

TMASK

PGOOD

OCL

Monitor

Protection

and Ref

+

-

MASKING TIME

ADJUSTMENT

OCH

LDO

OSC

L6730C/D

0.6V

1.2V

-

+

FB

VCCDR

PWM

+

-

E/A

COMP

BOOT

HGATE

PHASE

LGATE

PGND

GND

Vo

Note: In the L6730D the multifunction pin is: CC/OVP/UVLO.

5/50

Electrical data L6730C - L6730D

2 Electrical data

2.1 Maximum rating

Table 1. Absolute maximum ratings

Symbol Parameter Value Unit

V

CC

V

BOOT - VPHASE

V

HGATE - VPHASE

V

BOOT

VCC to GND and PGND, OCH, PGOOD

-0.3 to 18 V

Boot Voltage 0 to 6 V

0 to V

BOOT

- V

PHASE

BOOT -0.3 to 24 V

PHASE -1 to 18

V

PHASE

PHASE Spike, transient < 50ns (FSW = 500KHz)

-3

+24

OCH Pin

SS, FB, EAREF, SYNC, OSC, OCL, LGATE, COMP, S/O/
U, TMASK, PGOODELAY, V

CCDR

Maximum Withstanding Voltage Range

-0.3 to 6 V

±1500

Test Condition: CDF-AEC-Q100-002 "Human Body Model"

OTHER PINS ±2000

Acceptance Criteria: "Normal Performance"

2.2 Thermal data

Table 2. Thermal data

Symbol Description HTSSOP20 QFN4x4 Unit

(1)

R

thJA

T

STG

T

J

T

A

1. Package mounted on demoboard

Max. Thermal Resistance Junction to ambient 50 30 °C/W

Storage temperature range -40 to +150 °C

Junction operating temperature range -40 to +125 °C

Ambient operating temperature range -40 to +85 °C

V

V

VPGOOD Pin ±1000

6/50

L6730C - L6730D Pin connections and functions

3 Pin connections and functions

Figure 2. Pins connection (top view)

PGOOD DELAY

PGOOD DELAY

SYNCH

SYNCH

SINK/OVP/UVLO

TMASK

TMASK

GND

GND

FB

FB

COMP

COMP

SS/INH

SS/INH

EAREF

EAREF

OSC

OSC

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

HTSSOP20

HTSSOP20

20

20

PGOOD

PGOOD

19

19

VCC

VCC

18

18

VCCDR

VCCDR

17

17

LGATE

LGATE

16

16

PGND

PGND

15

15

BOOT

BOOT

14

14

HGATE

HGATE

13

13

PHASE

PHASE

12

12

OCH

OCH

11

11

OCL

OCL

HTSSOP20

1. In the L6730D the multifunction pin is: CC/OVP/UVLO.

Table 3. Pins connection

Pin n. Name Description

Connecting a capacitor between this pin and ground a delay is introduced
between the trigger of the internal PGOOD comparator and the external signal

1 PGOOD DELAY

rising edge. No delay can be introduced on the falling edge of the PGOOD
signal. The delay can be calculated with the following formula:

QFN 4x4 24L

2 SYNCH

SINK/OVP/UVLO

L6730C

3

CC/OVP/UVLO

L6730D

()

[µs]

pFCPGDelay ⋅= 5.0

It is a Master-Slave pin. Two or more devices can be synchronized by simply
connecting the SYNCH pins together. The device operating with the highest
F

will be the Master. The Slave devices will operate with 180° phase shift

SW

from the Master. The best way to synchronize devices together is to set their

at the same value. If it is not used the SYNCH pin can be left floating.

F

SW

With this pin it is possible:
– To enable-disable the sink mode current capability after SS (L6730C);
– To enable-disable the constant current OCP after SS (L6730D);
– To enable-disable the latch mode for the OVP;
– To set the UVLO threshold for the 5V BUS and 12V BUS.
The device captures the analog value present at this pin at the start-up when

meets the UVLO threshold.

V

CC

7/50

Pin connections and functions L6730C - L6730D

Table 3. Pins connection

By connecting this pin to V

4

5 GND All the internal references are referred to this pin.

6FB

7COMP

8 SS/INH

9 EAREF

T

MASK

values for the leading edge blanking time on the peak-over-current-protection.
The device captures the analog value present at this pin at the start-up when

meets the UVLO threshold.

V

CC

This pin is connected to the error amplifier inverting input. Connect it to Vout
through the compensation network. This pin is also used to sense the output
voltage in order to manage the over voltage conditions and the PGood signal.

This pin is connected to the error amplifier output and is used to compensate
the voltage control loop.

The soft-start time is programmed connecting an external capacitor from this
pin and GND. The internal current generator forces a current of 10µA through
the capacitor. This pin is also used to inhibit the device: when the voltage at
this pin is lower than 0.5V the device is disabled.

It is possible to set two internal references 0.6V / 1.2V or provide an external
reference from 0V to 2.5V:

– V

– V

– V

An internal clamp limits the maximum V
captures the analog value present at this pin at the start-up when V
the UVLO threshold.

Connecting an external resistor from this pin to GND, the external frequency
can be increased according with the following equation:

from 0% to 80% of V

EAREF

from 80% to 95% of V

EAREF

from 95% to 100% of V

EAREF

or ground it is possible to select two different

CCDR

−> External Reference

CCDR

CCDR

CCDR

−> V

=1.2V

REF

−> V

=0.6V

REF

at 2.5V (typ.). The device

EAREF

meets

CC

10 OSC

6

1088.9

400

Connecting a resistor from this pin to V
be lowered according with the following equation:

400

If the pin is left open, the switching frequency is 400 KHz. Normally this pin is at
a voltage of 1.2V. In OVP the pin is pulled up to 4.5V (only in latched mode).
Don’t connect a capacitor from this pin to GND.

+=

KHzFsw

CCDR

−=

KHzFsw

⋅

)(

Ω

KR

OSC

(5V), the switching frequency can

7

1001.3

⋅

)(

Ω

KR

OSC

8/50

L6730C - L6730D Pin connections and functions

Table 3. Pins connection

A resistor connected from this pin to ground sets the valley- current-limit. The
valley current is sensed through the low-side MOSFET(s). The internal current

11 OCL

12 OCH

generator sources a current of 100µA (I
external resistor (R

). The over-current threshold is given by the following

OCL

equation:

I

VALLEY

Connecting a capacitor from this pin to GND helps in reducing the noise
injected from V

to the device, but can be a low impedance path for the high-

CC

frequency noise related to the GND. Connect a capacitor only to a “clean”
GND.

A resistor connected from this pin and the high-side MOSFET(s) drain sets the
peak-current-limit. The peak current is sensed through the high-side
MOSFET(s). The internal 100µA current generator (I

the drain through the external resistor (R
given by the following equation:

I

PEAK

) from this pin to ground through the

OCL

R

I

⋅

OCL

OCL

=

R2

⋅

DSonLS

) sinks a current from

OCH

). The over-current threshold is

OCH

R

I

⋅

OCH

OCH

=

R

DSonHS

This pin is connected to the source of the high-side MOSFET(s) and provides

13 PHASE

the return path for the high-side driver. This pin monitors the drop across both
the upper and lower MOSFET(s) for the current limit together with OCH and
OCL.

14 HGATE This pin is connected to the high-side MOSFET(s) gate.

Through this pin is supplied the high-side driver. Connect a capacitor from this

15 BOOT

pin to the PHASE pin and a diode from V

to this pin (cathode versus

CCDR

BOOT).

16 PGND

This pin has to be connected closely to the low-side MOSFET(s) source in
order to reduce the noise injection into the device.

17 LGATE This pin is connected to the low-side MOSFET(s) gate.

18

19

V

CCDR

V

CC

5V internally regulated voltage. It is used to supply the internal drivers and as a
voltage reference. Filter it to ground with at least 1µF ceramic cap.

Supply voltage pin. The operative supply voltage range is from 4.5V to 14V.

This pin is an open collector output and it is pulled low if the output voltage is

20 PGOOD

not within the specified thresholds (90%-110%). If not used it may be left
floating. Pull-up this pin to V

with a 10K resistor to obtain a logical signal.

CCDR

9/50

L6730C - L6730D Electrical characteristics

4 Electrical characteristics

V

= 12V, TA = 25°C unless otherwise specified

CC

Table 4. Electrical characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

V

supply current

CC

VCC Stand By current

I

CC

quiescent current

V

CC

Power-ON

Tu r n - O N V

5V BUS

Tu r n - O F F V

Tu r n - O N V

12V BUS

Tu r n - O F F V

Tu r n - O N V

V

V

CCDR

IN OK

Regulation

Tu r n - O F F V

V

CCDR

Soft Start and Inhibit

I

SS

Soft Start Current

threshold V

CC

threshold V

CC

threshold V

CC

threshold V

CC

threshold

OCH

threshold

OCH

voltage

OSC = open; SS to GND 4.5 6.5

OSC= open;
HG = open, LG = open, PH=open

= 1.7V

OCH

= 1.7V

OCH

= 1.7V

OCH

= 1.7V

OCH

4.0 4.2 4.4

3.6 3.8 4.0

8.3 8.6 8.9

7.4 7.7 8.0

8.5 10

1.1 1.25 1.47

0.9 1.05 1.27

=5.5V to 14V

V

CC

= 1mA to 100mA

I

DR

4.555.5V

SS = 2V 7 10 13

SS = 0 to 0.5V 20 30 45

mA

V

µA

Oscillator

f

OSC

f

OSC,RT

∆V

OSC

Initial Accuracy OSC = OPEN 380 400 420 KHz

Total Accuracy

Ramp Amplitude 2.1 V

Output Voltage (1.2V MODE)

V

FB

Output Voltage 1.190 1.2 1.208 V

Output Voltage (0.6 MODE)

V

FB

Output Voltage 0.597 0.6 0.603 V

RT = 390KΩ to V

CCDR

RT = 18KΩ to GND

-15 15 %

10/50

L6730C - L6730D Electrical characteristics

Table 4. Electrical characteristics

Symbol Parameter Test Condition Min. Typ. Max. Unit

Error Amplifier

R

EAREF

I

FB

Ext Ref

Clamp

V

OFFSET

G

V

EAREF Input Resistance Vs. GND 70 100 150 kΩ

I.I. bias current

V

FΒ

0.290 0.5 µA

= 0V

2.3 V

Error amplifier offset Vref = 0.6V -5 +5 mV

Open Loop Voltage Gain Guaranteed by design 100 dB

GBWP Gain-Bandwidth Product Guaranteed by design 10 MHz

SR Slew-Rate

COMP = 10pF
Guaranteed by design

5V/µs

Gate Drivers

R

HGATE_ON

R

HGATE_OFF

R

LGATE_ON

R

LGATE_OFF

High Side Source Resistance

High Side Sink Resistance

Low Side Source Resistance

Low Side Sink Resistance

V

BOOT

V

BOOT

V

CCDR

V

CCDR

- V

- V

= 5V

= 5V

PHASE

PHASE

= 5V

= 5V

1.7 Ω

1.12 Ω

1.15 Ω

0.6 Ω

Protections

I

OCH

I

OCL

OVP

I

OSC

OCH Current Source

OCL Current Source 90 100 110 µΑ

Over Voltage Trip
(V

FB

/ V

EAREF

)

OSC Sourcing Current

= 1.7V

V

OCH

V

Rising

FB

V

= 0.6V

EAREF

V

Falling

FB

V

= 0.6V

EAREF

V

> OVP Trip V

FB

OSC

= 3V

90 100 110 µΑ

120 %

117 %

30 mA

Power Good

V

PGOOD

Upper Threshold
(V

FB

/ V

EAREF

)

Lower Threshold
(V

FB

/ V

EAREF

)

PGOOD Voltage Low

Rising

V

FB

V

Falling

FB

I

PGOOD

= -5mA

108 110 112 %

88 90 92 %

0.5 V

11/50

Electrical characteristics L6730C - L6730D

Table 5. Thermal characterizations (V

CC

= 12V)

Symbol Parameter Test Condition Min Typ Max Unit

Oscillator

f

OSC

Initial Accuracy

OSC = OPEN;

=0°C~ 125°C

T

J

376 400 424 KHz

Output Voltage (1.2V MODE)

T

= 0°C~ 125°C

V

FB

Output Voltage

J

T

= -40°C~ 125°C

J

1.188 1.2 1.212 V

1.185 1.2 1.212 V

Output Voltage (0.6V MODE)

T

= 0°C~ 125°C

V

FB

Output Voltage

J

T

= -40°C~ 125°C

J

0.596 0.6 0.605 V

0.593 0.6 0.605 V

12/50

L6730C - L6730D Device description

5 Device description

5.1 Oscillator

The switching frequency is internally fixed to 400KHz. The internal oscillator generates the
triangular waveform for the PWM charging and discharging an internal capacitor (F
400KHz). This current can be varied using an external resistor (R
pin and GND or V
maintained at fixed voltage (typ. 1.2V), the frequency is increased (decreased) proportionally to
the current sunk (sourced) from (into) the pin. In particular, connecting R
frequency is increased (current is sunk from the pin), according to the following relationship:

in order to change the switching frequency. Since the OSC pin is

CCDR

6

1088.9

400

OSC

⋅

KR

+=

KHzFsw

Ω

(1)

)(

) connected between OSC

T

versus GND the

T

SW

=

Connecting R
the following relationship:

Switching frequency variation vs. R

Figure 3. Switching frequency variation versus R

to V

T

the frequency is reduced (current is sourced into the pin), according to

CCDR

400

−=

KHzFsw

is shown in Figure 3..

T

1500

1400

1300

1200

Rosc connected to GND

1100

1000

900

800

700

Fsw (KHz)

600

500

400

300

200

Rosc connected to Vccdr

100

0 100 200 300 400 500 600 700 800 900 1000

OSC

.

T

7

1001.3

⋅

KR

Ω

(2)

)(

Rosc (KOHM )

13/50

Device description L6730C - L6730D

5.2 Internal LDO

An internal LDO supplies the internal circuitry of the device. The input of this stage is the VCC
pin and the output (5V) is the V

Figure 4. LDO block diagram.

pin (see Figure 4.).

CCDR

4.5V÷ 14V

LDO

5.3 Bypassing the LDO to avoid the voltage drop with low Vcc

The LDO can be by-passed, providing directly a 5V voltage to V
V

pins must be shorted together as shown in Figure 5. V

CCDR

CCDR

least 1µF capacitor to sustain the internal LDO during the recharge of the bootstrap capacitor.
V

also represents a voltage reference for Tmask pin, S/O/U pin (L6730C) or CC/O/U pin

CCDR

(L6730D) and PGOOD pin (see Table 3: Pins connection).

If Vcc

≈ 5V the internal LDO works in dropout with an output resistance of about 1Ω.

The maximum LDO output current is about 100mA and so the output voltage drop can be
100mV: to avoid this the LDO can be bypassed.

. In this case Vcc and

CCDR

pin must be filtered with at

Figure 5. Bypassing the LDO

14/50

L6730C - L6730D Device description

V

V

V

V

5.4 Internal and external references

It is possible to set two internal references, 0.6V and 1.2V or provide an external reference from
0V to 2.5V. The maximum value of the external reference depends on the V
the clamp operates at about 2V (typ.), while with V

greater than 5V the maximum external

CC

reference is 2.5V (typ.).

● V

● V

● V

from 0% to 80% of V

EAREF

from 80% to 95% of V

EAREF

from 95% to 100% of V

EAREF

−> External reference

CCDR

−> V

CCDR

CCDR

−> V

REF

REF

= 1.2V

= 0.6V

Providing an external reference from 0V to 450mV the output voltage will be regulated but
some restrictions must be considered:

● The minimum OVP threshold is set at 300mV;

● The under-voltage-protection doesn’t work;

● The PGOOD signal remains low;

To set the resistor divider it must be considered that a 100K pull-down resistor is integrated into
the device (see Figure 6.). Finally it must be taken into account that the voltage at the EAREF
pin is captured by the device at the start-up when Vcc is about 4V.

: with VCC = 4V

CC

5.5 Error amplifier

Figure 6. Error amplifier reference

CCDR

EAREF

100K

0.6

1.2

EXT

2.5

Error Amplifier Ref.

15/50

Device description L6730C - L6730D

V

V

V

5.6 Soft start

When both VCC and VIN are above their turn-ON thresholds (VIN is monitored by the OCH pin)
the start-up phase takes place. Otherwise the SS pin is internally shorted to GND. At start-up, a
ramp is generated charging the external capacitor C
initial value for this current is 35µA and charges the capacitor up to 0.5V. After that it becomes
10µA until the final charge value of approximately 4V (see Figure 7.).

Figure 7. Device start-up: Voltage at the SS pin.

with an internal current generator. The

SS

ss

Vss

0.5V

0.5V

0. 5V

4V

cc

in

4.2V or 8.6V

4. 2V

1. 25V

1.25V

4V

Vcc

Vin

t

t

16/50

L6730C - L6730D Device description

The reference of the error amplifier is clamped with this voltage (Vss) until it reaches the
programmed value: 0.6V or 1.2V. During the soft-start phase the converter works in closed
loop. The L6730C can only source current during the soft-start phase in order to manage the
prebias start-up applications. The L6730D can always sink current and so it can be used to
supply the DDR Memory termination BUS. If an over current is detected during the soft-start
phase, the device provides a constant-current-protection. In this way, in case of short soft-start
time and/or small inductor value and/or high output capacitors value and thus, in case of high
ripple current during the soft-start, the converter can start-up in any case, limiting the current
(see section 4.5 Monitoring and protections) but not entering in HICCUP mode. The soft-start
phase ends when Vss reaches 3.5V. After that the over-current-protection triggers the HICCUP
mode (L6730C). With the L6730D there is the possibility to set the HICCUP mode or the
constant current mode after the soft-start acting on the multifunction pin CC/O/U. With the
L6730 the low-side MOSFET(s) management after soft-start phase depends on the S/O/U pin
state (see related section). If the sink-mode is enabled the converter can sink current after soft­start (see figure 9) while, if the sink-mode is disabled the converter never sinks current (see
figure 10)..

Figure 8. Sink-mode enabled: Inductor current during and after soft-start (L6730C).

V

OUT

V

SS

V

CC

I

L

17/50

Device description L6730C - L6730D

Figure 9. Sink-mode disabled: Inductor current during and after soft-start (L6730C).

Vout

Vss

Vcc

I

L

During normal operation, if any under-voltage is detected on one of the two supplies (VCC, VIN),
the SS pin is internally shorted to GND by an internal switch and so the SS capacitor is rapidly
discharged. Two different turn-on UVLO thresholds can be set: 4.2V for 5V BUS and 8.6V for
12V BUS.

18/50

L6730C - L6730D Device description

5.7 Driver section

The high-side and low-side drivers allow using different types of power MOSFETs (also multiple
MOSFETs to reduce the R
supplied by V
time control avoids MOSFETs cross-conduction maintaining very short dead time duration (see

Figure 10.).

Figure 10. Dead times

while the high-side driver is supplied by the BOOT pin. A predictive dead

CCDR

), maintaining fast switching transitions. The low-side driver is

DS(on)

The control monitors the phase node in order to sense the low-side body diode recirculation. If
the phase node voltage is less than a certain threshold (-350mV typ.) during the dead time, it
will be reduced in the next PWM cycle. The predictive dead time control doesn’t work when the
high-side body diode is conducting because the phase node doesn’t go negative. This situation
happens when the converter is sinking current for example and, in this case, an adaptive dead
time control operates.

19/50

Device description L6730C - L6730D

5.8 Monitoring and protections

The output voltage is monitored by the FB pin. If it is not within ±10% (typ.) of the programmed
value, the Power-Good (PGOOD) output is forced low. The PGOOD signal can be delayed by
adding an external capacitor on PGDelay pin (see Table 3: Pins connection and Figure 11.);
this can be useful to perform cascade sequencing. The delay can be calculated with the
following formula:

()

Figure 11. PGOOD signal

[pF] (3)

pFCPGDelay ⋅= 5.0

The device provides over-voltage-protection: when the voltage sensed on FB pin reaches a
value 20% (typ.) greater than the reference, the low-side driver is turned on. If the OVP not­latched mode has been set the low-side MOSFET is kept on as long as the over voltage is
detected (see Figure 12.).If OVP latched-mode has been set the low-side MOSFET is turned
on until Vcc is toggled (see Figure 13.). In case of latched-mode OVP the OSC pin is forced
high (4.5V typ.) if an over voltage is detected. .

Figure 12. OVP not latched

LGate

FB

OSC

20/50

L6730C - L6730D Device description

Figure 13. OVP latched

LGate

OSC

FB

It must be taken into account that there is an electrical network between the output terminal and
the FB pin and therefore the voltage at this pin is not a perfect replica of the output voltage. If
the converter can sink current, in the most of cases the low-side will be turned-on before the
output voltage exceeds the over-voltage threshold, because the error amplifier will throw off
balance in advance. Even if the device doesn’t report an over-voltage, the behaviour is the
same, because the low-side is turned-on immediately. Instead, if the sink-mode is disabled, the
low-side will be turned-on only when the over-voltage-protection (OVP) operates and not
before, because the current can’t be reversed. In this case a delay between the output voltage
rising and the FB voltage rising can appear and the OVP can operate on late. The following two
figures show an over-voltage event in case of sink enabled and disabled. The output voltage
rises with a slope of 100mV/µs, emulating in this way the breaking of the high-side MOSFET as
an over-voltage cause.

Figure 14. OVP with sink enabled: the low-side MOSFET is turned-on in advance.

V

OUT

109%

FB

V

LGate

21/50

Device description L6730C - L6730D

−

Figure 15. OVP with sink disabled: delay on the OVP operation.

126%

V

OUT

V

FB

LGate

The L6730D can always sink current and so the OVP will operate always in advance. The
device realizes the over-current-protection (OCP) sensing the current both on the high-side
MOSFET(s) and the low-side MOSFET(s) and so 2 current limit thresholds can be set (see
OCH pin and OCL pin in Table 3: Pins connection):

● Peak Current Limit

● Valley Current Limit

The Peak Current Protection is active when the high-side MOSFET(s) is turned on, after an
adjustable masking time (see Chapter 5.10 on page 25). The valley-current-protection is
enabled when the low-side MOSFET(s) is turned on after a fix masking time of about 400ns. If,
when the soft-start phase is completed, an over current event occurs during the on time (peak­current-protection) or during the off time (valley-current-protection) the device enters in
HICCUP mode (L6730C): the high-side and low-side MOSFET(s) are turned off, the soft-start
capacitor is discharged with a constant current of 10µA and when the voltage at the SS pin
reaches 0.5V the soft-start phase restarts. During the soft-start phase the OCP provides a
constant-current-protection. If during the T

the OCH comparator triggers an over current the

ON

high-side MOSFET(s) is immediately turned-off (after the masking time and the internal delay)
and returned-on at the next pwm cycle. The limit of this protection is that the Ton can’t be less
than masking time plus propagation delay (see Chapter 5.9: Adjustable masking time on

page 25) because during the masking time the peak-current-protection is disabled. In case of

very hard short circuit, even with this short T

, the current could escalate. The valley-current-

ON

protection is very helpful in this case to limit the current. If during the off-time the OCL
comparator triggers an over current, the high-side MOSFET(s) is not turned-on until the current
is over the valley-current-limit. This implies that, if it is necessary, some pulses of the high-side
MOSFET(s) will be skipped, guaranteeing a maximum current due to the following formula:

VoutVin

II

+=

T

⋅

L

(4)

MINONVALLEYMAX

,

In constant current protection a current control loop limits the value of the error amplifier’s
output (comp), in order to avoid its saturation and thus recover faster when the output returns in
regulation. Figure 16. shows the behaviour of the device during an over current condition that
persists also in the soft-start phase.

22/50

L6730C - L6730D Device description

Figure 16. Constant current and Hiccup Mode during an OCP (L6730C).

VSS

VCOMP

I

L

Using the L6730D there is the possibility to set the constant-current-protection also after the
soft-start. The following figures show the behaviour of the L6730D during an overcurrent event.

Figure 17. Peak overcurrent-protection in constant-current-protection (L6730D).

V

OUT

Peak th

T

I

L

I

OUT

ON

Figure 17. shows the intervention of the peak OCP: the high-side MOSFET(s) is turned-off

when the current exceeds the OCP threshold. In this way the duty-cycle is reduced, the V
reduced and so the maximum current can be fixed even if the output current is escalating.

Figure 18. shows the limit of this protection: the on-time can be reduced only to the masking

time and, if the output current continues to increase, the maximum current can increase too.
Notice how the Vout remains constant even if the output current increases because the on-time
cannot be reduced anymore.

OUT

is

23/50

Device description L6730C - L6730D

Figure 18. Peak OCP in case of heavy overcurrent (L6730D).

V

OUT

I

L

I

OUT

If the current is higher than the valley OCP threshold during the off-time, the high-side
MOSFET(s) will not be turned-on. In this way the maximum current can be limited (Figure 19.).

Figure 19. Valley OCP (L6730D).

V

OUT

I

L

Valley th

T

OFF

24/50

T

OFF

L6730C - L6730D Device description

During the constant-current-protection if the Vout becomes lower than 80% of the programmed
value an UV (under-voltage) is detected and the device enters in HICCUP mode. The under­voltage-lock-out (UVLO) is adjustable by the multifunction pin (see Chapter 5.10 on page 25).
It’s possible to set two different thresholds:

● 4.2V for 5V Bus

● 8.6V for 12V Bus

Working with a 12V BUS, setting the UVLO at 8.6V can be very helpful to limit the input current
in case of BUS fall.

5.9 Adjustable masking time

By connecting the masking-time pin to V

or GND it is possible to select two different

CCDR

values for the peak -current-protection leading edge blanking time. This is useful to avoid any
false OCP trigger due to spikes and oscillations generated at the turn-on of the high-side
MOSFET(s). The amount of this noise depends a lot on the layout, MOSFETs, free-wheeling
diode, switched current and input voltage. In case of good layout and medium current, the
minimum masking time can be chosen, while in case of higher noise, it’s better to select to
maximum one. Connecting Tmask pin to V

the masking time is about 400ns while

CCDR

connecting it to GND the resulting masking time is about 260ns.

5.10 Multifunction pin (S/O/U L6730C) (CC/O/U L6730D)

With this pin it is possible:

● To enable-disable the sink-mode-current capability (L6730C) or the constant current

protection (L6730D) at the end of the soft-start;

● To enable-disable the latch-mode for the OVP;

● To set the UVLO threshold for 5V BUS and 12V BUS.

Ta bl e 6 shows how to set the different options through an external resistor divider:

Figure 20. External resistor

R1

R2

VCCDR

S/O/U

CC/O/U

L6730C/D

L6730/B

25/50

Device description L6730C - L6730D

≤

≤

Table 6. S/O/U pin; CC/O/U pin

R1 R2

N.C 0Ω 0 5V BUS Not Latched Not

11KΩ 2.7KΩ 0.2 5V BUS Not Latched Yes

6.2KΩ 2.7KΩ 0.3 5V BUS Latched Not

4.3KΩ 2.7KΩ 0.4 5V BUS Latched Yes

2.7KΩ 2.7KΩ 0.5 12V BUS Not Latched Not

1.8KΩ 2.7KΩ 0.6 12V BUS Not Latched Yes

1.2KΩ 2.7KΩ 0.7 12V BUS Latched Not

0Ω N.C 1 12V BUS Latched Yes

V

SOU/VCCDR

UVLO OVP SINK CC

5.11 Synchronization

The presence of many converters on the same board can generate beating frequency noise. To
avoid this it is important to make them operate at the same switching frequency. Moreover, a
phase shift between different modules helps to minimize the RMS current on the common input
capacitors. Figure 21. shows the results of two modules in synchronization. Two or more
devices can be synchronized simply connecting together the SYNCH pins. The device with the
higher switching frequency will be the Master while the other one will be the Slave. The Slave
controller will increase its switching frequency reducing the ramp amplitude proportionally and
then the modulator gain will be increased.

Figure 21. Synchronization.

PWM SIGNALS

To avoid a huge variation of the modulator gain, the best way to synchronize two or more
devices is to make them work at the same switching frequency and, in any case, the switching
frequencies can differ for a maximum of 50% of the lowest one. If, during synchronization
between two (or more) L6730, it’s important to know in advance which the master is, it’s timely
to set its switching frequency at least 15% higher than the slave. Using an external clock signal
(f

) to synchronize one or more devices that are working at a different switching frequency

EXT

(f

) it is recommended to follow the below formula:

SW

INDUCTOR CURRENTS

fff ⋅

3,1

SWEXTSW

The phase shift between master and slaves is approximately done 180°.

26/50

L6730C - L6730D Device description

5.12 Thermal shutdown

When the junction temperature reaches 150°C ±10°C the device enters in thermal shutdown.
Both MOSFETs are turned OFF and the soft-start capacitor is rapidly discharged with an
internal switch. The device does not restart until the junction temperature goes down to 120°C
and, in any case, until the voltage at the soft-start pin reaches 500mV.

5.13 Minimum on-time (T

The device can manage minimum on-times lower than 100ns. This feature comes from the
control topology and from the particular over-current-protection system of the L6730C ­L6730D. In fact, in a voltage mode controller the current has not to be sensed to perform the
regulation and, in the case of L6730C - L6730D, neither for the over-current protection, given
that during the off-time the valley-current-protection can operate. The first advantage related to
this feature is the possibility to realize extremely low conversion ratios. Figure 22. shows a
conversion from 14V to 0.5V at 820KHz with a T
turn-on and turn-off times of the MOSFETs.

Figure 22. 14V -> 0.5V@820KHz, 5A

ON, MIN

)

of about 50ns. The on-time is limited by the

ON

50ns

27/50

Device description L6730C - L6730D

5.14 Bootstrap anti-discharging system

This built-in system avoids that the voltage across the bootstrap capacitor becomes less than

3.3V. An internal comparator senses the voltage across the external bootstrap capacitor
keeping it charged, eventually turning-on the low-side MOSFET for approximately 200ns. If the
bootstrap capacitor is not enough charged the high-side MOSFET cannot be effectively turned­on and it will present a higher R
possible to mention at least two application conditions during which the bootstrap capacitor can
be discharged:

5.14.1 Fan’s power supply

In many applications the FAN is a DC MOTOR driven by a voltage-mode DC/DC converter.
Often only the speed of the MOTOR is controlled by varying the voltage applied to the input
terminal and there’s no control on the torque because the current is not directly controlled.
Obviously the current has to be limited in case of overload or short-circuit but without stopping
the MOTOR. With the L6730D the current can be limited without shutting down the system
because a constant-current-protection is provided. In order to vary the MOTOR speed the
output voltage of the converter must be varied. Both L6730C and L6730D have a dedicated pin
called EAREF (see the related section) that allows providing an external reference to the non­inverting input of the error-amplifier.

In these applications the duty cycle depends on the MOTOR’s speed and sometimes 100% has
to be set in order to go at the maximum speed. Unfortunately in these conditions the bootstrap
capacitor can not be recharged and the system cannot work properly. Some PWM controller
limits the maximum duty-cycle to 80-90% in order to keep the bootstrap cap charged but this
make worse the performance during the load transient. Thanks to the “bootstrap anti­discharging system” the L6730X can work at 100% without any problem. The following picture
shows the device behaviour when input voltage is 5V and 100% is set by the external
reference.

. In some cases the OCP can be also triggered. It’s

DS(on)

Figure 23. 100% duty cycle operation

T

≈

OFF

OFF

≈

200ns

200ns

T

V

= 5V

OUT

Vout=5V

Vout=5V

VIN = 5V

Vin=5V

Vin=5V

LGate

LGate

LGate

FSW

≈

6.3KHz

Fsw?6.3KHz

Fsw?6.3KHz

28/50

L6730C - L6730D Device description

5.14.2 No-sink at zero current operation

The L6730C can work in no-sink mode. If output current is zero the converter skip some pulses
and works with a lower switching frequency. Between two pulses can pass a relatively long time
(say 200-300µs) during which there’s no switching activity and the current into the inductor is
zero. In this condition the phase node is at the output voltage and in some cases this is not
enough to keep the bootstrap cap charged. For example, if Vout is 3.3V the voltage across the
bootstrap cap is only 1.7V. The high-side MOSFET cannot be effectively turned-on and the
regulation can be lost. Thanks to the “bootstrap anti-discharging system” the bootstrap cap is
always kept charged. The following picture shows the behaviour of the device in the following
conditions: 12V◊3.3V@0A.

Figure 24. 12V -> 3.3V@0A in no-sink

I

L

Pulse trainMinimum Bootstrap Voltage V

PHASE

It can be observed that between two pulses trains the low-side is turned-on in order to keep the
bootstrap cap charged.

29/50

Application details L6730C - L6730D

−

V

V

V

V

6 Application details

6.1 Inductor design

The inductance value is defined by a compromise between the transient response time, the
efficiency, the cost and the size. The inductor has to be calculated to maintain the ripple current
(∆I

) between 20% and 30% of the maximum output current. The inductance value can be

L

calculated with the following relationship:

Where F

is the switching frequency, VIN is the input voltage and V

SW

Figure 25. shows the ripple current vs. the output voltage for different values of the inductor,

with Vin = 5V and Vin = 12V at a switching frequency of 400KHz.

Figure 25. Inductor current ripple.

8

7

6

5

4

3

2

1

INDUCTOR CURRENT RIPPL

0

01234

L

≅

OUTPUT VOLTAGE (V)

VoutVin

Vout

⋅

∆⋅

Vin

IFsw

L

(6)

is the output voltage.

OUT

in = 1 2 V , L = 1 u H

in = 1 2 V , L = 2 u H

in = 5 V, L=500nH

in = 5 V , L = 1 .5 u H

Increasing the value of the inductance reduces the current ripple but, at the same time,
increases the converter response time to a load transient. If the compensation network is well
designed, during a load transient the device is able to set the duty cycle to 100% or to 0%.
When one of these conditions is reached, the response time is limited by the time required to
change the inductor current. During this time the output current is supplied by the output
capacitors. Minimizing the response time can minimize the output capacitor size.

30/50

L6730C - L6730D Application details

6.2 Output capacitors

The output capacitors are basic components for the fast transient response of the power
supply. They depend on the output voltage ripple requirements, as well as any output voltage
deviation requirement during a load transient. During a load transient, the output capacitors
supply the current to the load or absorb the current stored into the inductor until the converter
reacts. In fact, even if the controller recognizes immediately the load transient and sets the duty
cycle at 100% or 0%, the current slope is limited by the inductor value. The output voltage has
a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL):

ESRIoutVout

ESR

Moreover, there is an additional drop due to the effective capacitor discharge or charge that is
given by the following formulas:

Vout

Formula (8) is valid in case of positive load transient while the formula (9) is valid in case of
negative load transient. D
100%. For a given inductor value, minimum input voltage, output voltage and maximum load
transient, a maximum ESR and a minimum C
also affect the static output voltage ripple. In the worst case the output voltage ripple can be
calculated with the following formula:

Usually the voltage drop due to the ESR is the biggest one while the drop due to the capacitor
discharge is almost negligible.

COUT

=∆

Vout

MAX

=∆

COUT

is the maximum duty cycle value that in the L6730C - L6730D is

2

(

ESRIVout

L

⋅∆=∆

2

2

⋅∆

VoutCout

⋅⋅

OUT

+⋅∆=∆

8

(7)

LIout

⋅∆

VoutDVinCout

−⋅⋅⋅

(8)

)maxmin,(2

LIout

(9)

value can be set. The ESR and C

1

)

⋅⋅

FswCout

(10)

OUT

values

6.3 Input capacitors

The input capacitors have to sustain the RMS current flowing through them, that is:

Where D is the duty cycle. The equation reaches its maximum value, I
losses in worst case are:

(11)

)1( DDIoutIrms −⋅⋅=

/2 with D = 0.5. The

OUT

2

(12)

)5.0( IoutESRP ⋅⋅=

31/50

Application details L6730C - L6730D

6.4 Compensation network

The loop is based on a voltage mode control (Figure 26.). The output voltage is regulated to the
internal/external reference voltage and scaled by the external resistor divider. The error
amplifier output V
width modulated (PWM) with an amplitude of V
by the output filter. The modulator transfer function is the small signal transfer function of V
V
and a zero at F
simply the input voltage V

Figure 26. Compensation network

. This function has a double pole at frequency FLC depending on the L-Cout resonance

COMP

ESR

is then compared with the oscillator triangular wave to provide a pulse-

COMP

depending on the output capacitor’s ESR. The DC Gain of the modulator is

divided by the peak-to-peak oscillator voltage: V

IN

Z

FB

at the PHASE node. This waveform is filtered

IN

.

OSC

Z

IN

OUT

/

The compensation network consists in the internal error amplifier, the impedance networks Z
(R3, R4 and C20) and Z
closed loop transfer function with the highest 0dB crossing frequency to have fastest transient
response (but always lower than f
load regulation error. A stable control loop has a gain crossing the 0dB axis with -20dB/decade
slope and a phase margin greater than 45°. To locate poles and zeroes of the compensation
networks, the following suggestions may be used:

● Modulator singularity frequencies:

ω

● Compensation network singularity frequencies:

=

ω

P

1

ω

Z

(R5, C18 and C19). The compensation network has to provide a

FB

/10) and the highest gain in DC conditions to minimize the

SW

1

=

CoutLLC⋅

1

⎛
⎜

⋅

R

5

⎜
⎝

1

=

1

⋅

CR

(13)

(15)

⎞

⋅

CC

1918

⎟

⎟

+

CC

1918

⎠

(17)

195

ω

ω

ESR

Z

=

ω

=

2

1

CoutESR

⋅

1

=

2

CRP⋅

204

1

()

+⋅

RRC

4320

(14)

(16)

(18)

IN

32/50

L6730C - L6730D Application details

● Compensation network design:

– Put the gain R

in order to obtain the desired converter bandwidth

5/R3

Vin

R

5

⋅=

∆

R

3

Vosc

ϖϖ

⋅

(18)

LCC

– Place ω
– Place ω
– Place ω
– Place ω

before the output filter resonance ωLC;

Z1

at the output filter resonance ωLC;

Z2

at the output capacitor ESR zero ω

P1

at one half of the switching frequency;

P2

ESR

– Check the loop gain considering the error amplifier open loop gain.

Figure 27. Asymptotic bode plot of converter's open loop gain

;

33/50

Application details L6730C - L6730D

6.5 Two quadrant or one quadrant operation mode (L6730C)

After the soft-start phase the L6730C can work in source only (one quadrant operation mode)
or in sink/source (two quadrant operation mode), depending on the setting of the multifunction
pin (see Chapter 5.10 on page 25). The choice of one or two quadrant operation mode is
related to the application. One quadrant operation mode permits to have a higher efficiency at
light load, because the converter works in discontinuous mode (see Figure 28.). Nevertheless
in some cases, in order to maintain a constant switching frequency, it’s preferable to work in two
quadrants, even at light load. In this way the reduction of the switching frequency due to the
pulse skipping is avoided. To parallel two or more modules is requested the one quadrant
operation in order not to have current sinking between different converters. Finally the two
quadrant operation allows faster recovers after negative load transient. For example, let’s
consider that the load current falls down from I
than L/V

(where L is the inductor value). Even considering that the converter reacts

OUT

instantaneously setting to 0% the duty-cycle, the energy ½*L*I
transferred to the output capacitors, increasing the output voltage. If the converter can sink
current this overvoltage can be faster eliminated.

Figure 28. Efficiency in discontinuous-current-mode and continuous-current-mode.

EFFICIENCY: DCM vs. CCM

to 0A with a slew rate sufficiently greater

OUT

2

stored in the inductor will be

OUT

0.7

0.6

0.5

0.4

EFF. (%

0.3

0.2

0.1

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

OUTPUT CURRENT (A)

EFFICIENCY DCM

EFFICIENCY CCM

34/50

L6730C - L6730D L6730 Demoboard

7 L6730 Demoboard

7.1 Description

L6730 demoboard realizes in a four layer PCB a step-down DC/DC converter and shows the
operation of the device in a general purpose application. The input voltage can range from 4.5V
to 14V and the output voltage is at 3.3V. The module can deliver an output current in excess of
30A. The switching frequency is set at 400 KHz (controller free-running F
increased up to 1MHz. A 7 positions dip-switch allows to select the UVLO threshold (5V or 12V
Bus), the OVP intervention mode and the sink-mode current capability.

Figure 29. Demoboard picture.

Top side Bottom side

) but it can be

SW

35/50

L6730 Demoboard L6730C - L6730D

7.2 PCB layout

Figure 30. Top layer Figure 31. Power ground layer

Figure 32. Signal ground layer Figure 33. Bottom layer

36/50

L6730C - L6730D L6730 Demoboard

Figure 34. Demoboard schematic

Table 7. Demoboard part list

Reference Value Manufacturer Package Supplier

R1 820Ω Neohm SMD 0603 IFARCAD

R2 0Ω Neohm SMD 0603 IFARCAD

R3 N.C.

R4 10Ω 1% 100mW Neohm SMD 0603 IFARCAD

R5 11K 1% 100mW Neohm SMD 0603 IFARCAD

R6 6K2 1% 100mW Neohm SMD 0603 IFARCAD

R7 4K3 1% 100mW Neohm SMD 0603 IFARCAD

R8 2K7 1% 100mW Neohm SMD 0603 IFARCAD

R9 1K8 1% 100mW Neohm SMD 0603 IFARCAD

R10 1K2 1% 100mW Neohm SMD 0603 IFARCAD

R11 2K7 1% 100mW Neohm SMD 0603 IFARCAD

R12 1K Neohm SMD 0603 IFARCAD

37/50

L6730 Demoboard L6730C - L6730D

Table 7. Demoboard part list

Reference Value Manufacturer Package Supplier

R13 2K7 1% 100mW Neohm SMD 0603 IFARCAD

R14 1K 1% 100mW Neohm SMD 0603 IFARCAD

R15 1K 1% 100mW Neohm SMD 0603 IFARCAD

R16 4K7 1% 100mW Neohm SMD 0603 IFARCAD

R17 N.C.

R18 2.2Ω Neohm SMD 0603 IFARCAD

R19 2.2Ω Neohm SMD 0603 IFARCAD

R20 10K 1% 100mW Neohm SMD 0603 IFARCAD

R21 N.C.

R22 N.C.

R23 0Ω Neohm SMD 0603 IFARCAD

C1 220nF Kemet SMD 0603 IFARCAD

C3-C7-C9-C15-C21 100nF Kemet SMD 0603 IFARCAD

C2 1nF. Kemet SMD 0603 IFARCAD

C4-C6 100uF 20V OSCON 20SA100M RADIAL 10X10.5 SANYO

C8 4.7uF 20V AVX SMA6032 IFARCAD

C10 10nF Kemet SMD 0603 IFARCAD

C11 N.C.

C12 47nF Kemet SMD 0603 IFARCAD

C13 1.5nF Kemet SMD 0603 IFARCAD

C14 4.7nF Kemet SMD 0603 IFARCAD

C18-C19 330uF 6.3V POSCAP 6TPB330M SMD SANYO

C20 N.C.

L1 1.8uH Panasonic SMD ST

D1 1N4148 ST SOT23 IFARCAD

D2 STS1L30M ST DO216AA STMicroelectronics

Q1-Q2 STS12NH3LL ST SO8 STMicroelectronics

Q4-Q5 STSJ100NH3LL ST SO8 STMicroelectronics

U1 L6730 ST HTSSOP20 STMicroelectronics

SWITCH DIP SWITCH 7 POS. STMicroelectronics

38/50

L6730C - L6730D L6730 Demoboard

Table 8. Other inductor manufacturer

Manufacturer Series Inductor Value (µH) Saturation Current (A)

WURTH ELEKTRONIC 744318180 1.8 20

SUMIDA CDEP134-2R7MC-H 2.7 15

EPCOS HPI_13 T640 1.4 22

TDK SPM12550T-1R0M220 1 22

TOKO FDA1254 2.2 14

COILTRONICS

Table 9. Other capacitor manufacturer

Manufacturer Series Capacitor value(µF) Rated voltage (V)

HCF1305-1R0 1.15 22

HC5-1R0 1.3 27

TDK

NIPPON CHEMI-CON 25PS100MJ12 100 25

PANASONIC ECJ4YB0J107M 100 6.3

C4532X5R1E156M 15 25

C3225X5R0J107M 100 6.3

39/50

I/O Description L6730C - L6730D

8 I/O Description

Figure 35. Demoboard

Table 10. I/O Functions

Symbol Function

The input voltage can range from 1.8V to 14V. If the input voltage is between 4.5V and 14V

Input (V

Output (V

)

IN-GIN

OUT-GOUT

it can supply also the device (through the VCC pin) and in this case the pin 1 and 2 of the
jumper G1 must be connected together.

The output voltage is fixed at 3.3V but it can be changed by replacing the resistor R14 of the
output resistor divider:

)

The over-current-protection limit is set at 15A but it can be changed by replacing the
resistors R1 and R12 (see OCL and OCH pin in Table 3: Pins connection).

Using the input voltage to supply the controller no power is required at this input.

VCC-GND

CC

V

CCDR

TP1

TP2 This test point is connected to the Tmask pin (see Table 3: Pins connection).

However the controller can be supplied separately from the power stage through
the V

An internal LDO provides the power into the device. The input of this stage is the VCC pin
and the output (5V) is the Vccdr pin. The LDO can be bypassed, providing directly a 5V

voltage from V
shorted.

This pin can be used as an input or as a test point. If all the jumper G2 pins are shorted, TP1
can be used as a test point of the voltage at the EAREF pin. If the pins 2 and 3 of G2 are
connected together, TP1 can be used as an input to provide an external reference for the
internal error amplifier (see section 4.3. Internal and external references).

input (4.5-14V) and, in this case, jumper G1 must be left open.

CC

and Gndcc. In this case the pins 1 and 3 of the jumper G1 must be

CCDR

R

VVo

REF

16

)1(

+⋅=

R

14

TP3 This test point is connected to the S/O/U pin (see Chapter 5.10 on page 25).

40/50

L6730C - L6730D I/O Description

Table 10. I/O Functions

SYNCH This pin is connected to the synch pin of the controller (see Chapter 5.11 on page 26).

PWRGD This pin is connected to the PGOOD pin of the controller.

DIP SWITCH

Table 11. Dip switch

Different positions of the dip switch correspond to different settings of the multifunction pin
(S/O/U) (CC/O/U).

UVLO OVP SINK CC

5V Not Latched Not 0 S7 A

5V Not Latched Yes 0.2 S1-S7 B

5V Latched Not 0.3 S2-S7 C

5V Latched Yes 0.4 S3-S7 D

12V Not Latched Not 0.5 S4-S7 E

12V Not Latched Yes 0.6 S5-S7 F

12V Latched Not 0.7 S6-S7 G

12V Latched Yes 1 S1 H

Vsou/V

CCDR

DIP SWITCH STATE

41/50

Efficiency L6730C - L6730D

Y

Y

9 Efficiency

The following figures show the demoboard efficiency versus load current for different values of
input voltage and switching frequency:

Figure 36. Demoboard efficiency 400KHz

95.00%

90.00%

85.00%

EFFICIENC

80.00%

75.00%

V

VIN = 5V

IN = 5VVIN = 5V

VIN = 12V

13579111315

Figure 37. Demoboard efficiency 645KHz

95.00%

Fsw=400KHz

Iout (A)

Fsw=645KHz

VO = 3.3V

V

= 3.3V

O

90.00%

85.00%

80.00%

EFFICIENC

75.00%

70.00%

42/50

VIN = 5V

VIN = 12V

13579111315

Iout (A)

L6730C - L6730D Efficiency

Y

Figure 38. Demoboard efficiency 1MHz

Fsw=1MHz

VO = 3.3V

95.00%

90.00%

85.00%

VIN = 5V

80.00%

75.00%

EFFICIENC

70.00%

65.00%

60.00%

13579111315

Iout (A)

Figure 39. Efficiency with 2xSTS12NH3LL+2XSTSJ100NH3LL

12V-->3.3V

0.96

0.95

0.94

0.93

0.92

0.91

0.9

EFFICIENCY (%)

0.89

0.88

0.87

3 5 7 9 11 13 15 17 19

VIN = 12V

400KHz

700KHz

1MHz

OUTPUT CURRENT (A)

43/50

POL Demoboard L6730C - L6730D

10 POL Demoboard

10.1 Description

A compact demoboard has been realized to manage currents in the range of 10-15A. Figure

36. shows the schematic and Table 9. the part list. Multi-layer-ceramic-capacitors (MLCCs)

have been used on the input and the output in order to reduce the overall size.

Figure 40. Pol demoboard schematic.

Table 12. Pol demoboard part list.

Reference Value Manufacturer Package Supplier

R1 1K8Ω Neohm SMD 0603 IFARCAD

R2 10KΩ Neohm SMD 0603 IFARCAD

R3 N.C.

R4 10Ω Neohm SMD 0603 IFARCAD

R5 11K 1% 100mW Neohm SMD 0603 IFARCAD

R6 2K7 1% 100mW Neohm SMD 0603 IFARCAD

R7 N.C. Neohm SMD 0603 IFARCAD

R8 0Ω Neohm SMD 0603 IFARCAD

R9 3K 1% 100mW Neohm SMD 0603 IFARCAD

R10 4K7 1% 100mW Neohm SMD 0603 IFARCAD

44/50

L6730C - L6730D POL Demoboard

Y

Table 12. Pol demoboard part list.

R11 15Ω 1% 100mW Neohm SMD 0603 IFARCAD

R12 4K7 1% 100mW Neohm SMD 0603 IFARCAD

R13 1K 1% 100mW Neohm SMD 0603 IFARCAD

R14 2.2Ω Neohm SMD 0603 IFARCAD

R15 2.2Ω Neohm SMD 0603 IFARCAD

C1-C7 220nF Kemet SMD 0603 IFARCAD

C6- C19-C20-C9 100nF Kemet SMD 0603 IFARCAD

C2 1nF Kemet SMD 0603 IFARCAD

C11 N.C.

C12 68nF Kemet SMD 0603 IFARCAD

C13 220pF Kemet SMD0603 IFARCAD

C8 4.7uF 20V AVX SMA6032 IFARCAD

C14 6.8nF Kemet SMD 0603 IFARCAD

C3-C4-C5 15uF TDK MLC

C4532X5R1E156M

C15-C16-C17-C18 100uF PANASONIC MLC P/N

ECJ4YBOJ107M

L1 1.8uH Panasonic SMD ST

D1 STS1L30M ST DO216AA ST

Q1 STS12NH3LL ST POWER SO8 ST

Q2 STSJ100NH3LL ST POWER SO8 ST

U1 L6730 ST HTSSOP20 ST

SMD1812 IFARCAD

SMD 1210 IFARCAD

Figure 41. Pol Demoboard efficiency

0.94

0.92

0.9

0.88

0.86

EFFICIENC

0.84

0.82

1357911

12V-->3.3V@400KHz

OUTP UT CURRENT (A)

45/50

Package mechanical data L6730C - L6730D

11 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second Level Interconnect is marked on the package and on the inner box label, in compliance
with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are
available at: www.st.com.

46/50

L6730C - L6730D Package mechanical data

Table 13. HTSSOP20 mechanical data

DIM.

Min Typ Max Min Typ Max

A 1.200 0.047
A1 0.150 0.006
A2 0.800 1.000 1.050 0.031 0.039 0.041

b 0.190 0.300 0.007 0.012

c 0.090 0.200 0.003 0.008

D

D1

(1)

(3)

6.400 6.500 6.600 0.252 0.256 0.260

2.200 0.087

E 6.200 6.400 6.600 0.244 0.252 0.260

E1

E2

(2)

(3)

4.300 4.400 4.500 0.170 0.173 0.177

1.500 0.059

e 0.650 0.025

L 0.450 0.600 0.750 0.018 0.024 0.030
L1 1.000 0.039

k 0° min., 8° max.

aaa 0.100 0.004

1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed

0.15mm per side.

2. Dimension “E1” does not include interlead flash or protrusions. Intelead flash or protrusions shall not exceed 0.25mm per
side.

3. The size of exposed pad is variable depending of leadframe design pad size. End user should verify “D1” and “E2”
dimensions for each device application.

mm inch

Figure 42. Package dimensions

47/50

Package mechanical data L6730C - L6730D

Table 14. QFN 4mm x 4mm 24L mechanical data

Dim

Min Typ Max Min Typ Max

A 1.00 39.4

A1 0.00 0.05 0.0 2.0

b 0.18 0.30 7.1 11.8

D 3.9 4.1 153.5 161.4

D2 1.95 2.25 76.8 88.6

E 3.9 4.1 153.5 161.4

E2 1.95 2.25 76.8 88.6

e 0.50 19.7

L 0.40 0.60 15.7 23.6

mm inch

Figure 43. Package dimensions

48/50

L6730C - L6730D Revision history

12 Revision history

Table 15. Revision history

Date Revision Changes

21-Dec-2005 1 Initial release.

07-Jun-2006 2 Added QFN package information, new template

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L6730C - L6730D

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