ST L6730B User Manual

Adjustable step-down controller with synchronous rectification

Features

■ Input voltage range from 1.8V to 14V

■ Supply voltage range from 4.5V to 14V

■ Adjustable output voltage down to 0.6V with

±0.8% accuracy over line voltage and temperature (0°C~125°C)

■ Fixed frequency voltage mode control

■ t

■ 0% to 100% duty cycle

■ Selectable 0.6V or 1.2V internal voltage

■ External input voltage reference

■ Soft-start and inhibit

■ High current embedded drivers

■ Predictive anti-crossconduction control

■ Selectable uvlo threshold (5V or 12V BUS)

■ Programmable high-side and low-side R

■ Switching frequency programmable from

■ Master/slave synchronization with 180° phase

■ Pre-bias start up capability (L6730)

■ Selectable source/sink or source only

■ Selectable constant current or hiccup mode

lower than 100ns

reference

DS(on)

sense over-current-protection

100kHz to 1MHz

shift

capability after soft-start (L6730)

overcurrent protection after soft-start (L6730B)

L6730B

HTSSOP20

■ Power good output with programmable delay

■ Over voltage protection with selectable

latched/not-latched mode

■ Thermal shut-down

■ Package: HTSSOP20

Applications

■ High performance / high density DC-DC

modules

■ Low voltage distributed DC-DC

■ niPOL converters

■ DDR memory supply

■ DDR memory bus termination supply

L6730

Order Codes

Part number Package Packing

L6730 HTSSOP20 Tube

L6730TR HTSSOP20 Tape & Reel

L6730B HTSSOP20 Tube

L6730BTR HTSSOP20 Tape & Reel

June 2006 Rev 2 1/52

www.st.com

Contents L6730 - L6730B

Contents

1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Pin connections and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.2 Internal LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.3 Bypassing the LDO to avoid the voltage drop with low Vcc . . . . . . . . . . . . . 14

5.4 Internal and external references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.5 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.6 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.7 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.8 Monitoring and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.9 Adjustable masking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.10 Multifunction pin (S/O/U L6730) (CC/O/U L6730B) . . . . . . . . . . . . . . . . . . . 27

5.11 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.12 Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.13 Minimum ON-time TON(MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.14 Bootstrap anti-discharging system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.14.1 Fan power supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.14.2 No-Sink at zero current operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2/52

L6730 - L6730B Contents

6 Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.1 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.2 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.3 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.5 Two quadrant or one quadrant operation mode (L6730) . . . . . . . . . . . . . . . . 36

7 L6730 Demo board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.2 PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8 I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10 POL Demoboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3/52

Summary description L6730 - L6730B

1 Summary description

The controller is an integrated circuit ... designed using BiCMOS-DMOS, v5 (BCD5) technology that provides complete control logic and protection for high performance, step-down DC/DC and niPOL converters.

It is designed to drive N-Channel MOSFETs in a synchronous rectified buck converter topology. The output voltage of the converter can be precisely regulated down to 600mV, with a maximum tolerance of ±0.8%, or to 1.2V, when one of the internal references is used. It is also possible to use an external reference from 0V to 2.5V.

The input voltage can range from 1.8V to 14V, while the supply voltage can range from 4.5V to 14V. High peak current gate drivers provide for fast switching to the external power section and the output current can be in excess of 20A, depending on the number of the external MOSFETs used. The PWM duty cycle can range from 0% to 100% with a minimum on-time (T lower than 100ns, making conversions with a very low duty cycle and very high switching frequency possible.

The device provides voltage-mode control. It includes a 400kHz free-running oscillator that is adjustable from 100kHz to 1MHz. The error amplifier features a 10MHz gain-bandwidth-product and 5V/µs slew-rate that permits to realize high converter bandwidth for fast transient response. The device monitors the current by using the R MOSFET(s), eliminating the need for a current sensing resistor and guaranteeing an effective over current-protection in all the application conditions. When necessary, two different current limit protections can be externally set through two external resistors. A leading edge adjustable blanking time is also available to avoid false over-current-protection (OCP) intervention in every application condition.

of both the high-side and low-side

DS(ON)

ON(MIN)

)

It is possible to select the HICCUP mode or the constant current protection (L6730B) after the soft-start phase.

During this phase constant current protection is provided. It is possible to select the sink-source or the source-only mode capability (before the device powers on) by acting on a multifunction pin (L6730). The L6730 disables the sink mode capability during the soft-start in order to allow a proper start-up also in pre-biased output voltage conditions. The L6730B can always sink current and, so it can be used to supply the DDR Memory BUS termination. Other features include Master-Slave synchronization (with 180° phase shift), Power-Good with adjustable delay, over voltage-protection, feed back disconnection, selectable UVLO threshold (5V and 12V Bus), and thermal shutdown. The HTSSOP20 package allows the realization for very compact DC/DC converters.

4/52

L6730 - L6730B Summary description

1.1 Functional description

Figure 1. Block diagram

VCC=4.5V to14V

=1.8V to14V

SS/INH SYNCH

OSC

EAREF

PGOOD

SINK/OVP/UVLO*

TMASK

PGOOD

OCL

Monitor

Protection

and Ref

MASKING TIME

ADJUSTMENT

OCH

OSC

L6730/B

0.6V

1.2V

LDO

VCCDR

PWM

E/A

COMP

BOOT

HGATE

PHASE

LGATE

PGND

GND

1. In the L6730B the multifunction pin is: CC/OVP/UVLO.

5/52

Electrical data L6730 - L6730B

2 Electrical data

2.1 Maximum rating

Table 1. Absolute maximum ratings

Symbol Parameter Value Unit

VCC to GND and PGND, OCH, PGOOD

BOOT - VPHASE

HGATE - VPHASE

BOOT

PHASE

Boot Voltage 0 to 6 V

BOOT -0.3 to 24 V

PHASE -1 to 18

PHASE Spike, transient < 50ns (F

= 500KHz)

-0.3 to 18 V

0 to V

BOOT

- V

PHASE

-3

+24

OCH Pin

SS, FB, EAREF, SYNC, OSC, OCL, LGATE, COMP, S/O/ U, TMASK, PGOODELAY, V

CCDR

Maximum Withstanding Voltage Range

-0.3 to 6 V

±1500

Test Condition: CDF-AEC-Q100-002 "Human Body Model"

OTHER PINS ±2000

Acceptance Criteria: "Normal Performance"

2.2 Thermal data

Table 2. Thermal data

Symbol Description Value Unit

(1)

thJA

STG

1. Package mounted on demoboard

Max. Thermal Resistance Junction to ambient 50 °C/W

Storage temperature range -40 to +150 °C

Junction operating temperature range -40 to +125 °C

Ambient operating temperature range -40 to +85 °C

VPGOOD Pin ±1000

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L6730 - L6730B Pin connections and functions

3 Pin connections and functions

Figure 2. Pins connection (Top view)

PGOOD DELAY

SINK/OVP/UVLO

TMASK

SS/INH

EAREF

1. In the L6730B the multifunction pin is: CC/OVP/UVLO.

SYNCH

GND

COMP

OSC

HTSSOP20

PGOOD

VCC

VCCDR

LGATE

PGND

BOOT

HGATE

PHASE

OCH

OCL

Table 3. Pins connection

Pin n. Name Description

A capacitor connected between this pin and GND introduces a delay between the internal PGOOD comparator trigger and the external signal rising edge. No

1 PGOOD DELAY

delay can be introduced on the falling edge of the PGOOD signal. The delay can be calculated with the following formula:

2 SYNCH

SINK/OVP/UVLO

L6730

CC/OVP/UVLO

L6730B

[µ

()

pFCPGDelay ⋅= 5.0

Two or more devices can be synchronized by connecting the SYNCH pins together. The device operating with the highest F The Slave devices will operate at 180° phase shift from the Master. The best way to synchronize devices is to set their FSW at the same value. If it is not used, the SYNCH pin can be left floating.

With this pin it is possible: – To enable-disable the sink mode current capability after SS (L6730); – To enable-disable the constant current OCP after SS (L6730B); – To enable-disable the latch mode for the OVP; – To set the UVLO threshold for the 5V BUS and 12V BUS. The device captures the analog value present at this pin at the start-up when

meets the UVLO threshold.

SW will be the Master device.

7/52

Pin connections and functions L6730 - L6730B

Table 3. Pins connection

The user can select two different values for the leading edge blanking time on

MASK

the peak overcurrent protection by connecting this pin to V device captures the analog value present at this pin at the start-up when VCC meets the UVLO threshold.

5 GND All of the internal references are referenced to this pin.

This pin is connected to the error amplifier inverting input. Connect it to Vout

6FB

through the compensation network. This pin is also used to sense the output voltage in order to manage the over voltage conditions and the PGood signal.

7COMP

This pin is connected to the error amplifier output and used to compensate the voltage control loop.

The soft-start time is programmed connecting an external capacitor from this

8 SS/INH

pin and GND. The internal current generator forces a current of 10µA through the capacitor. This pin is also used to inhibit the device: when the voltage at this pin is lower than 0.5V the device is disabled.

It is possible to set two internal references 0.6V / 1.2V or provide an external reference from 0V to 2.5V:

9 EAREF

– V

from 0% to 80% of V

EAREF

from 80% to 95% of V

EAREF

from 95% to 100% of V

EAREF

An internal clamp limits the maximum V

−> External Reference

CCDR

−> V

=1.2V

REF

−> V

REF

at 2.5V (typ.). The device

EAREF

=0.6V

captures the analog value present at this pin at the start-up when V the UVLO threshold.

CCDR or GND. The

meets

10 OSC

Connecting an external resistor from this pin to GND, the external frequency can be increased according with the following equation:

1088.9

400

Connecting a resistor from this pin to V

+=KRKHzFsw

CCDR

⋅

)(

Ω

OSC

(5V), the switching frequency can

be lowered according with the following equation:

1001.3

400

⋅

−=KRKHzFsw

OSC

)(

Ω

If the pin is left open, the switching frequency is 400 KHz. Normally this pin is at a voltage of 1.2V. In OVP the pin is pulled up to 4.5V (only in latched mode). Don’t connect a capacitor from this pin to GND.

8/52

L6730 - L6730B Pin connections and functions

Table 3. Pins connection

A resistor connected from this pin to ground sets the valley- current-limit. The valley current is sensed through the low-side MOSFET(s). The internal current

11 OCL

12 OCH

generator sources a current of 100µA (I external resistor (R

). The over-current threshold is given by the following

OCL

equation:

VALLEY

Connecting a capacitor from this pin to GND helps in reducing the noise injected from V

to the device, but can be a low impedance path for the high-

frequency noise related to the GND. Connect a capacitor only to a “clean” GND.

A resistor connected from this pin and the high-side MOSFET(s) drain sets the peak-current-limit. The peak current is sensed through the high-side MOSFET(s). The internal 100µA current generator (I

the drain through the external resistor (R given by the following equation:

PEAK

) from this pin to ground through the

OCL

⋅

OCL

⋅

DSonLS

) sinks a current from

OCH

). The over-current threshold is

OCH

⋅

OCH

DSonHS

This pin is connected to the source of the high-side MOSFET(s) and provides

13 PHASE

the return path for the high-side driver. This pin monitors the drop across both the upper and lower MOSFET(s) for the current limit together with OCH and OCL.

14 HGATE This pin is connected to the high-side MOSFET(s) gate.

The high-side driver is supplied through this pin. Connect a capacitor from this

15 BOOT

pin to the PHASE pin, and a diode from V

CCDR to this pin (cathode versus

BOOT).

16 PGND

This pin has to be connected closely to the low-side MOSFET(s) source in order to reduce the noise injection into the device.

17 LGATE This pin is connected to the low-side MOSFET(s) gate.

CCDR

5V internally regulated voltage. It is used to supply the internal drivers and as a voltage reference. Filter it to GND with at least a 1µF ceramic cap.

Supply voltage pin. The operative supply voltage range is from 4.5V to 14V.

This pin is an open collector output and it is pulled low if the output voltage is

20 PGOOD

not within the specified thresholds (90%-110%). If not used it may be left floating. Pull up this pin to V

with a 10K resistor to obtain a logical signal.

CCDR

9/52

L6730 - L6730B Electrical characteristics

4 Electrical characteristics

= 12V, TA = 25°C unless otherwise specified

Table 4. Electrical characteristics

Symbol Parameter Test Condition Min. Typ. Max. Unit

SUPPLY CURRENT

VCC Stand By current

quiescent current

Power-ON

Tu r n - O N V

5V BUS

Tu r n - O F F V

Tu r n - O N V

12V BUS

Tu r n - O F F V

Tu r n - O N V

CCDR

IN OK

Regulation

Tu r n - O F F V

CCDR

Soft Start and Inhibit

Soft Start Current

threshold V

threshold

OCH

threshold

OCH

voltage

OSC = open; SS to GND 7 9

OSC= open; HG = open, LG = open, PH=open

= 1.7V

OCH

= 1.7V

OCH

= 1.7V

OCH

= 1.7V

OCH

4.0 4.2 4.4

3.6 3.8 4.0

8.3 8.6 8.9

7.4 7.7 8.0

8.5 10

1.1 1.25 1.47

0.9 1.05 1.27

=5.5V to 14V

= 1mA to 100mA

4.555.5V

SS = 2V 7 10 13

SS = 0 to 0.5V 20 30 45

µA

Oscillator

OSC

OSC,RT

∆V

OSC

Initial Accuracy OSC = OPEN 380 400 420 KHz

Total Accuracy

Ramp Amplitude 2.1 V

Output Voltage (1.2V MODE)

Output Voltage 1.190 1.2 1.208 V

Output Voltage (0.6 MODE)

Output Voltage 0.597 0.6 0.603 V

RT = 390KΩ to V

CCDR

RT = 18KΩ to GND

-15 15 %

10/52

L6730 - L6730B Electrical characteristics

Table 4. Electrical characteristics

Symbol Parameter Test Condition Min. Typ. Max. Unit

Error Amplifier

EAREF

Ext Ref

Clamp

OFFSET

EAREF Input Resistance Vs. GND 70 100 150 kΩ

I.I. bias current

FΒ

0.290 0.5 µA

= 0V

2.3 V

Error amplifier offset Vref = 0.6V -5 +5 mV

Open Loop Voltage Gain Guaranteed by design 100 dB

GBWP Gain-Bandwidth Product Guaranteed by design 10 MHz

SR Slew-Rate

COMP = 10pF Guaranteed by design

5V/µs

Gate Drivers

HGATE_ON

HGATE_OFF

LGATE_ON

LGATE_OFF

High Side Source Resistance

High Side Sink Resistance

Low Side Source Resistance

Low Side Sink Resistance

BOOT

CCDR

- V

= 5V

PHASE

= 5V

1.7 Ω

1.12 Ω

1.15 Ω

0.6 Ω

Protections

OCH

OCL

OVP

OSC

OCH Current Source

OCL Current Source 90 100 110 µΑ

Over Voltage Trip (V

/ V

EAREF

)

OSC Sourcing Current

= 1.7V

OCH

Rising

= 0.6V

EAREF

Falling

= 0.6V

EAREF

> OVP Trip V

OSC

= 3V

90 100 110 µΑ

120 %

117 %

30 mA

Power Good

PGOOD

Upper Threshold (V

/ V

EAREF

)

Lower Threshold (VFB / V

EAREF

)

PGOOD Voltage Low

Rising

Falling

PGOOD

= -5mA

108 110 112 %

88 90 92 %

0.5 V

11/52

Electrical characteristics L6730 - L6730B

Table 5. Thermal Characterizations (V

= 12V)

Symbol Parameter Test Condition Min Typ Max Unit

Oscillator

OSC

Initial Accuracy

OSC = OPEN;

=0°C~ 125°C

376 400 424 KHz

Output Voltage (1.2V MODE)

= 0°C~ 125°C

Output Voltage

= -40°C~ 125°C

1.188 1.2 1.212 V

1.185 1.2 1.212 V

Output Voltage (0.6V MODE)

= 0°C~ 125°C

Output Voltage

= -40°C~ 125°C

0.596 0.6 0.605 V

0.593 0.6 0.605 V

12/52

L6730 - L6730B Device description

5 Device description

5.1 Oscillator

The switching frequency is internally fixed to 400kHz. The internal oscillator generates the triangular waveform for the PWM charging and discharging an internal capacitor (F 400kHz). This current can be varied using an external resistor (R pin and GND or V maintained at fixed voltage (typ. 1.2V), the frequency is increased (or decreased) proportionally to the current sunk (sourced) from (into) the pin. In particular by connecting R frequency is increased (current is sunk from the pin), according to the following relationship:

in order to change the switching frequency. Since the OSC pin is

CCDR

1088.9

400

+=KRKHzFsw

⋅

OSC

Ω

(1)

)(

) connected between OSC

versus GND the

Connecting R the following relationship:

Switching frequency variation vs. R

Figure 3. Switching frequency variation versus RT.

to V

reduces the frequency (current is sourced into the pin), according to

CCDR

400

−=KRKHzFsw

OSC

is shown in Figure 3..

Switching Frequency Variation

1500

1400

1300

1200

1100

1000

900

800

700

Fsw (KHz)

600

500

400

300

200

100

Rosc connected to GND

Rosc connected to Vccdr

0 100 200 300 400 500 600 700 800 900 1000

1001.3

⋅

(2)

)(

Ω

Rosc (KOHM )

13/52

Device description L6730 - L6730B

5.2 Internal LDO

An internal LDO supplies the internal circuitry of the device. The input of this stage is the VCC pin and the output (5V) is the V

Figure 4. LDO block diagram.

pin (see Figure 4.).

CCDR

4.5V÷14V

LDO

5.3 Bypassing the LDO to avoid the voltage drop with low Vcc

The LDO can be by passed by providing 5V voltage directly to V V

pins must be shorted together as shown in Figure 5. V

CCDR

least 1µF capacitor to sustain the internal LDO during the recharge of the bootstrap capacitor. V

also represents a voltage reference for Tmask pin, S/O/U pin (L6730) or CC/O/U pin

CCDR

(L6730B) and PGOOD pin (see Table 3: Pins connection).

If Vcc

≈ 5V the internal LDO works in dropout with an output resistance of about 1Ω.

The maximum LDO output current is about 100mA, and so the output voltage drop can be 100mV. The LDO can be bypassed to avoid this.

. In this case Vcc and

CCDR

pin must be filtered with at

Figure 5. Bypassing the LDO

14/52

L6730 - L6730B Device description

5.4 Internal and external references

It is possible to set two internal references, 0.6V and 1.2V, or provide an external reference from 0V to 2.5V. The maximum value of the external reference depends on the V 4V the clamp operates at about 2V (typ.), while with V

greater than 5V the maximum external

reference is 2.5V (typ).

● V

from 0% to 80% of V

EAREF

from 80% to 95% of V

EAREF

from 95% to 100% of V

EAREF

−> External reference

CCDR

−> V

CCDR

−> V

REF

= 1.2V

= 0.6V

Providing an external reference from 0V to 450mV the output voltage will be regulated but some restrictions must be considered:

● The minimum OVP threshold is set at 300mV.

● The under-voltage-protection doesn’t work.

● The PGOOD signal remains low.

To set the resistor divider it must be considered that a 100K pull-down resistor is integrated into the device (see Figure 6.). Finally it must be taken into account that the voltage at the EAREF pin is captured by the device at the start-up when Vcc is about 4V.

: with VCC =

5.5 Error amplifier

Figure 6. Error Amplifier Reference

CCDR

EAREF

100K

0.6

1.2

EXT

2.5

Error Amplifier Ref.

15/52

Device description L6730 - L6730B

5.6 Soft-start

When both VCC and VIN are above their turn-on thresholds (VIN is monitored by the OCH pin) the start-up phase takes place. Otherwise the SS pin is internally shorted to GND. At start-up, a ramp is generated charging the external capacitor C initial value for this current is 35µA and charges the capacitor up to 0.5V. After that it becomes 10µA until the final charge value of approximately 4V (see Figure 5.).

Figure 7. Device start-up: Voltage at the SS pin.

with an internal current generator. The

Vss

0.5V

0. 5V

Vcc

Vin

4. 2V

4.2V or 8.6V

1. 25V

1.25V

16/52

+ 36 hidden pages

ST L6730B User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Summary description

1.1 Functional description

Figure 1. Block diagram

2 Electrical data

2.1 Maximum rating

Table 1. Absolute maximum ratings

2.2 Thermal data

Table 2. Thermal data

3 Pin connections and functions

Figure 2. Pins connection (Top view)

Table 3. Pins connection

4 Electrical characteristics

Table 4. Electrical characteristics

5 Device description

5.1 Oscillator

Figure 3. Switching frequency variation versus RT.

5.2 Internal LDO

Figure 4. LDO block diagram.

5.3 Bypassing the LDO to avoid the voltage drop with low Vcc

Figure 5. Bypassing the LDO

5.4 Internal and external references

5.5 Error amplifier

Figure 6. Error Amplifier Reference

5.6 Soft-start

Figure 7. Device start-up: Voltage at the SS pin.