ST L6730 User Manual
Adjustable step-down controller with synchronous rectification
Features
■ Input voltage range from 1.8 V to 14 V
■ Supply voltage range from 4.5 V to 14 V
■ Adjustable output voltage down to 0.6 V with
±0.8% accuracy over line voltage and
temperature (0°C~125°C)
■ Fixed frequency voltage mode control
■ t
■ 0% to 100% duty cycle
■ Selectable 0.6 V or 1.2 V internal voltage
■ External input voltage reference
■ Soft-start and inhibit
■ High current embedded drivers
■ Predictive anti-cross conduction control
■ Selectable uvlo threshold (5 V or 12 V BUS)
■ Programmable high-side and low-side R
■ Switching frequency programmable
■ Master/slave synchronization with 180° phase
■ Pre-bias start up capability (L6730)
■ Selectable source/sink or source only
■ Selectable constant current or hiccup mode
■ Power Good output with programmable delay
■ Overvoltage protection with selectable
■ Thermal shut-down
■ Package: HTSSOP20
lower than 100 ns
ON
reference
sense overcurrent protection
DS(on)
from 100 kHz to 1 MHz
shift
capability after soft-start (L6730)
overcurrent protection after soft-start (L6730B)
latched/not-latched mode
HTSSOP20
Applications
■ High performance / high density DC-DC
modules
■ Low voltage distributed DC-DC
■ niPOL converters
■ DDR memory supply
■ DDR memory bus termination supply
Table 1. Device summary
Order codes Package Packing
L6730 HTSSOP20 Tube
L6730TR HTSSOP20 Tape and reel
L6730B HTSSOP20 Tube
L6730BTR HTSSOP20 Tape and reel
L6730
L6730B
December 2009 Doc ID 11938 Rev 3 1/52
www.st.com
52
Contents L6730 - L6730B
Contents
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Pin connections and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Internal LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 Bypassing the LDO to avoid the voltage drop with low Vcc . . . . . . . . . . . 15
5.4 Internal and external references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.6 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.7 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.8 Monitoring and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.9 Adjustable masking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.10 Multifunction pin (S/O/U L6730) (CC/O/U L6730B) . . . . . . . . . . . . . . . . . 27
5.11 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.12 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.13 Minimum ON-time TON(MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.14 Bootstrap anti-discharging system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.14.1 Fan power supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.14.2 No-sink at zero current operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6 Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2/52 Doc ID 11938 Rev 3
L6730 - L6730B Contents
6.2 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.3 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.5 Two quadrant or one quadrant operation mode (L6730) . . . . . . . . . . . . . 37
7 L6730 demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.2 PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8 I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10 POL demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Doc ID 11938 Rev 3 3/52
Summary description L6730 - L6730B
1 Summary description
The controller is an integrated circuit designed using BiCMOS-DMOS, v5 (BCD5)
technology that provides complete control logic and protection for high performance, stepdown DC/DC and niPOL converters.
It is designed to drive N-Channel MOSFETs in a synchronous rectified buck converter
topology. The output voltage of the converter can be precisely regulated down to 600 mV,
with a maximum tolerance of ±0.8%, or to 1.2 V, when one of the internal references is used.
It is also possible to use an external reference from 0 V to 2.5 V.
The input voltage can range from 1.8 V to 14 V, while the supply voltage can range from 4.5
V to 14 V. High peak current gate drivers provide for fast switching to the external power
section and the output current can be in excess of 20 A, depending on the number of the
external MOSFETs used. The PWM duty cycle can range from 0% to 100% with a minimum
on-time (T
very high switching frequency possible.
The device provides voltage-mode control. It includes a 400 kHz free-running oscillator that
is adjustable from 100 kHz to 1 MHz. The error amplifier features a 10 MHz gain-bandwidthproduct and 5 V/µs slew-rate that permits to realize high converter bandwidth for fast
transient response. The device monitors the current by using the R
side and low-side MOSFET(s), eliminating the need for a current sensing resistor and
guaranteeing an effective over current-protection in all the application conditions. When
necessary, two different current limit protections can be externally set through two external
resistors. A leading edge adjustable blanking time is also available to avoid false overcurrent-protection (OCP) intervention in every application condition.
ON(MIN)
) lower than 100 ns, making conversions with a very low duty cycle and
of both the high-
DS(ON)
It is possible to select the HICCUP mode or the constant current protection (L6730B) after
the soft-start phase.
During this phase constant current protection is provided. It is possible to select the sinksource or the source-only mode capability (before the device powers on) by acting on a
multifunction pin (L6730). The L6730 disables the sink mode capability during the soft-start
in order to allow a proper start-up also in pre-biased output voltage conditions. The L6730B
can always sink current and, so it can be used to supply the DDR memory BUS termination.
Other features include Master-Slave synchronization (with 180° phase shift), Power-Good
with adjustable delay, over voltage-protection, feed back disconnection, selectable UVLO
threshold (5 V and 12 V Bus), and thermal shutdown. The HTSSOP20 package allows the
realization for very compact DC/DC converters.
4/52 Doc ID 11938 Rev 3
L6730 - L6730B Summary description
1.1 Functional description
Figure 1. Block diagram
VCC=4.5V to14V
V
=1.8V to14V
in
OCL
PGOOD
OCH
LDO
VCCDR
BOOT
Monitor
SS/INH
SYNCH
OSC
EAREF
PGOOD
SINK/OVP/UVLO*
TMASK
Protection
and Ref
+
-
MASKING TIME
ADJUSTMENT
OSC
L6730/B
0.6V
1.2V
-
+
PWM
E/A
+
-
FB
HGATE
PHASE
LGATE
PGND
GND
COMP
Note: In the L6730B the multifunction pin is: CC/OVP/UVLO.
Vo
Doc ID 11938 Rev 3 5/52
Summary description L6730 - L6730B
1.2 Application circuit
Figure 2. Application circuit
VCC = 4.5V to 14V
DEC
THERMAL PAD
FB
R
OS
OCH
VCCDR
BOOT
HGATE
PHASE
LGATE
PGND
OCL
R
FILT
R
OCH
C
OCH
R
BOOT
C
BOOT
C
VCCDR
R
OCL
C
OCL
R
FB
RSC
S
VCCDR
R
R
SYNCH
R
H_SOU
H_OSC
L_OSCRL_SOU
SHORT PIN
R
R
H_MASK
L_MASK
1
C
VCC
GND
SYNCH
SS/INH
PGOOD DELAY
C
C
PGdelay
SS
L6730
R
PG
R
R
H_EAREF
L_EAREF
PGOOD
OSC
SOU/COU
TMASK
EAREF
C
EAREF
COMP
RFC
F
C
P
NOTE 1: In module application it is recommended to place the short pin on the module where device is mounted.
VCCDR
VIN = 1.8V to 14V
C
IN_BULK
C
R
HS
IN_HF
HS
LVout
R
LS
R
SN
LS
C
SN
C
OUT
6/52 Doc ID 11938 Rev 3
L6730 - L6730B Electrical data
2 Electrical data
2.1 Maximum rating
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
V
VCC to GND and PGND, OCH, PGOOD
CC
V
BOOT - VPHASE
V
HGATE - VPHASE
V
BOOT
V
PHASE
Boot voltage 0 to 6 V
BOOT -0.3 to 24 V
PHASE -1 to 18
PHASE spike, transient < 50ns (F
= 500kHz)
SW
-0.3 to 18 V
0 to V
BOOT
- V
-3
+24
PHASE
V
V
SS, FB, EAREF, SYNC, OSC, OCL, LGATE, COMP,
S/O/U, TMASK, PGOODELAY, V
OCH Pin
Maximum withstanding voltage range
test condition: CDF-AEC-Q100-002 “human body
OTHER PINS ±2000
model” acceptance criteria: “normal performance”
2.2 Thermal data
Table 3. Thermal data
Symbol Description Value Unit
(1)
R
thJA
T
STG
T
J
T
A
1. Package mounted on demonstration board
Max. thermal resistance junction to ambient 50 °C/W
Storage temperature range -40 to +150 °C
Junction operating temperature range -40 to +125 °C
Ambient operating temperature range -40 to +85 °C
CCDR
-0.3 to 6 V
±1500
VPGOOD Pin ±1000
Doc ID 11938 Rev 3 7/52
Pin connections and functions L6730 - L6730B
(
⋅
=
3 Pin connections and functions
Figure 3. Pins connection (top view)
PGOOD DELAY
PGOOD DELAY
SYNCH
SYNCH
SINK/OVP/UVLO
TMASK
TMASK
GND
GND
FB
FB
COMP
COMP
SS/INH
SS/INH
EAREF
EAREF
OSC
OSC
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
HTSSOP20
HTSSOP20
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
Note: In the L6730B the multifunction pin is: CC/OVP/UVLO.
Table 4. Pin connection
Pin n. Name Description
A capacitor connected between this pin and GND introduces a delay
between the internal PGOOD comparator trigger and the external signal
1 PGOOD DELAY
rising edge. No delay can be introduced on the falling edge of the
PGOOD signal. The delay can be calculated with the following formula:
PGOOD
PGOOD
VCC
VCC
VCCDR
VCCDR
LGATE
LGATE
PGND
PGND
BOOT
BOOT
HGATE
HGATE
PHASE
PHASE
OCH
OCH
OCL
OCL
Two or more devices can be synchronized by connecting the SYNCH pins
together. The device operating with the highest F
2 SYNCH
device. The Slave devices will operate at 180° phase shift from the
Master. The best way to synchronize devices is to set their FSW at the
same value. If it is not used, the SYNCH pin can be left floating.
With this pin it is possible:
SINK/OVP/UVLO
L6730
3
CC/OVP/UVLO
L6730B
To enable-disable the sink mode current capability after SS (L6730);
To enable-disable the constant current OCP after SS (L6730B);
To enable-disable the latch mode for the OVP;
To set the UVLO threshold for the 5 V BUS and 12 V BUS.
The device captures the analog value present at this pin at the start-up
when V
meets the UVLO threshold.
CC
8/52 Doc ID 11938 Rev 3
[μ
s]
)
pFCPGDelay
5.0
SW will be the Master
L6730 - L6730B Pin connections and functions
Table 4. Pin connection (continued)
Pin n. Name Description
The user can select two different values for the leading edge blanking
4
T
MASK
time on the peak overcurrent protection by connecting this pin to V
GND. The device captures the analog value present at this pin at the
start-up when VCC meets the UVLO threshold.
CCDR or
5GND
All the internal references are referenced to this pin. Connect to the PCB
signal ground.
This pin is connected to the error amplifier inverting input. Connect it to
6FB
Vout through the compensation network. This pin is also used to sense
the output voltage in order to manage the over voltage conditions and the
PGood signal.
7COMP
This pin is connected to the error amplifier output and used to
compensate the voltage control loop.
The soft-start time is programmed connecting an external capacitor from
8 SS/INH
this pin and GND. The internal current generator forces a current of 10mA
through the capacitor. This pin is also used to inhibit the device: when the
voltage at this pin is lower than 0.5V the device is disabled.
It is possible to set two internal references 0.6V / 1.2V or provide an
external reference from 0V to 2.5V:
V
9 EAREF
V
V
An internal clamp limits the maximum V
captures the analog value present at this pin at the start-up when VCC
meets the UVLO threshold.
Connecting an external resistor from this pin to GND, the external
frequency can be increased according with the following equation:
from 0% to 80% of V
EAREF
from 80% to 95% of V
EAREF
from 95% to 100% of V
EAREF
-> external reference
CCDR
-> V
CCDR
-> V
CCDR
400
+=KRKHzFsw
=1.2V
REF
=0.6V
REF
at 2.5V (typ.). The device
EAREF
6
1088.9
⋅
)(
Ω
OSC
10 OSC
Connecting a resistor from this pin to V
(5V), the switching frequency
CCDR
can be lowered according with the following equation:
7
1001.3
400
⋅
−=KRKHzFsw
OSC
)(
Ω
If the pin is left open, the switching frequency is 400 KHz. Normally this
pin is at a voltage of 1.2V. In OVP the pin is pulled up to 4.5V (only in
latched mode). Don’t connect a capacitor from this pin to GND.
Doc ID 11938 Rev 3 9/52
Pin connections and functions L6730 - L6730B
Table 4. Pin connection (continued)
Pin n. Name Description
A resistor connected from this pin to ground sets the valley- current-limit.
The valley current is sensed through the low-side MOSFET(s). The
11 OCL
12 OCH
internal current generator sources a current of 100μA (I
to ground through the external resistor (R
). The over-current threshold
OCL
is given by the following equation:
R
I
⋅
OCL
I
VALLEY
OCL
=
R2
⋅
DSonLS
Connecting a capacitor from this pin to GND helps in reducing the noise
injected from V
to the device, but can be a low impedance path for the
CC
high-frequency noise related to the GND. Connect a capacitor only to a
“clean” GND.
A resistor connected from this pin and the high-side MOSFET(s) drain
sets the peak-current-limit. The peak current is sensed through the highside MOSFET(s). The internal 100μA current generator (I
current from the drain through the external resistor (R
current threshold is given by the following equation:
R
I
⋅
I
PEAK
OCH
=
R
DSonHS
OCH
) from this pin
OCL
OCH
). The over-
OCH
) sinks a
This pin is connected to the source of the high-side MOSFET(s) and
13 PHASE
provides the return path for the high-side driver. This pin monitors the
drop across both the upper and lower MOSFET(s) for the current limit
together with OCH and OCL.
14 HGATE This pin is connected to the high-side MOSFET(s) gate.
The high-side driver is supplied through this pin. Connect a capacitor from
15 BOOT
this pin to the PHASE pin, and a diode from V
CCDR to this pin (cathode
versus BOOT).
This pin has to be connected closely to the low-side MOSFET(s) source
16 PGND
in order to reduce the noise injection into the device. Connect to the PCB
power ground plane.
17 LGATE This pin is connected to the low-side MOSFET(s) gate.
5V internally regulated voltage. It is used to supply the internal drivers
18
V
CCDR
and as a voltage reference. Filter it to GND with at least a 1µF ceramic
cap.
19
V
CC
Supply voltage pin. The operative supply voltage range is from 4.5V to
14V.
This pin is an open collector output and it is pulled low if the output
20 PGOOD
voltage is not within the specified thresholds (90%-110%). If not used it
may be left floating. Pull up this pin to V
with a 10K resistor to obtain
CCDR
a logical signal.
- Thermal PAD
Thermal Pad connects the silicon substrate and makes good thermal
contact with the PCB. Connect to the PCB power ground plane.
10/52 Doc ID 11938 Rev 3
L6730 - L6730B Electrical characteristics
4 Electrical characteristics
V
= 12 V, TA = 25°C unless otherwise specified
CC
Table 5. Electrical characteristics
Symbol Parameter Test condition Min. Typ. Max. Unit
V
supply current
CC
VCC stand by current
I
CC
V
CC
Power-ON
Tu r n -O N V
5V BUS
Tu r n -O F F V
Tu r n -O N V
12V BUS
Tu r n -O F F V
Tu r n -O N V
V
V
CCDR
IN OK
regulation
Tu r n -O F F V
V
CCDR
Soft start and inhibit
I
SS
Soft start current
quiescent current
threshold V
CC
threshold V
CC
threshold V
CC
threshold V
CC
threshold
OCH
threshold
OCH
voltage
OSC = open; SS to GND 7 9
OSC= open;
HG = open, LG = open, PH=open
= 1.7V
OCH
= 1.7V
OCH
= 1.7V
OCH
= 1.7V
OCH
4.0 4.2 4.4
3.6 3.8 4.0
8.3 8.6 8.9
7.4 7.7 8.0
8.5 10
1.1 1.25 1.47
0.9 1.05 1.27
=5.5V to 14V
V
CC
= 1mA to 100mA
I
DR
4.5 5 5.5 V
SS = 2V 7 10 13
SS = 0 to 0.5V 20 30 45
mA
V
µA
Oscillator
f
OSC
f
OSC,RT
ΔV
OSC
Initial accuracy OSC = OPEN 380 400 420 kHz
Total accuracy
Ramp amplitude 2.1 V
Output voltage (1.2V MODE)
V
FB
Output voltage 1.190 1.2 1.208 V
Output voltage (0.6 MODE)
V
FB
Output voltage 0.597 0.6 0.603 V
Error amplifier
R
EAREF
EAREF input resistance Vs. GND 70 100 150 kΩ
RT = 390KΩ to V
RT = 18KΩ to GND
CCDR
-15 15 %
Doc ID 11938 Rev 3 11/52
Electrical characteristics L6730 - L6730B
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
I
FB
I.I. bias current
= 0V
V
FB
0.290 0.5 μA
Ext Ref Clamp 2.3 V
V
OFFSET
G
V
Error amplifier offset Vref = 0.6V -5 +5 mV
Open loop voltage gain Guaranteed by design 100 dB
GBWP Gain-bandwidth product Guaranteed by design 10 MHz
SR Slew-rate
COMP = 10pF
Guaranteed by design
5V/μs
Gate drivers
R
HGATE_ON
R
HGATE_OFF
R
LGATE_ON
R
LGATE_OFF
High side source resistance
High side sink resistance
Low side source resistance
Low side sink resistance
V
BOOT
V
BOOT
V
CCDR
V
CCDR
- V
- V
= 5V
= 5V
PHASE
PHASE
= 5V
= 5V
1.7 Ω
1.12 Ω
1.15 Ω
0.6 Ω
Protections
I
OCH
I
OCL
OVP
I
OSC
OCH current source
OCL current source 90 100 110 μA
Over voltage trip
(V
FB
/ V
EAREF
)
OSC sourcing current
= 1.7V
V
OCH
V
rising
FB
V
V
V
V
= 0.6V
EAREF
falling
FB
= 0.6V
EAREF
> OVP Trip V
FB
OSC
= 3V
90 100 110 μA
120 %
117 %
30 mA
Power Good
V
PGOOD
Upper threshold
(V
FB
/ V
EAREF
)
Lower threshold
(VFB / V
EAREF
)
PGOOD voltage low
V
rising
FB
V
falling
FB
I
PGOOD
= -5mA
12/52 Doc ID 11938 Rev 3
108 110 112 %
88 90 92 %
0.5 V
L6730 - L6730B Electrical characteristics
Table 6. Thermal characterizations (V
CC
= 12 V)
Symbol Parameter Test condition Min Typ Max Unit
Oscillator
f
OSC
Initial accuracy
OSC = OPEN;
= 0°C~ 125°C
T
J
376 400 424 kHz
Output voltage (1.2V MODE)
T
= 0°C~ 125°C
V
FB
Output voltage
J
= -40°C~ 125°C
T
J
1.188 1.2 1.212 V
1.185 1.2 1.212 V
Output voltage (0.6V MODE)
T
= 0°C~ 125°C
V
FB
Output voltage
J
T
= -40°C~ 125°C
J
0.596 0.6 0.605 V
0.593 0.6 0.605 V
Doc ID 11938 Rev 3 13/52
Device description L6730 - L6730B
5 Device description
5.1 Oscillator
The switching frequency is internally fixed to 400 kHz. The internal oscillator generates the
triangular waveform for the PWM charging and discharging an internal capacitor (F
kHz). This current can be varied using an external resistor (R
and GND or V
in order to change the switching frequency. Since the OSC pin is
CCDR
) connected between OSC pin
T
maintained at fixed voltage (typ. 1.2 V), the frequency is increased (or decreased)
proportionally to the current sunk (sourced) from (into) the pin. In particular by connecting
R
versus GND the frequency is increased (current is sunk from the pin), according to the
T
following relationship:
6
1088.9
400
+=KRKHzFsw
⋅
OSC
Ω
(1)
)(
SW
= 400
Connecting R
to V
T
reduces the frequency (current is sourced into the pin), according
CCDR
to the following relationship:
7
1001.3
400
Switching frequency variation vs. R
Figure 4. Switching frequency variation versus RT
1500
1400
1300
1200
1100
1000
900
800
700
Fsw (KHz)
600
500
400
300
200
100
Rosc connected to GND
0 100 200 300 400 500 600 700 800 900 1000
is shown in Figure 4.
T
⋅
−=KRKHzFsw
OSC
)(
Ω
Rosc connected to Vccdr
Rosc (KOHM)
(2)
14/52 Doc ID 11938 Rev 3
L6730 - L6730B Device description
5.2 Internal LDO
An internal LDO supplies the internal circuitry of the device. The input of this stage is the
V
pin and the output (5 V) is the V
CC
Figure 5. LDO block diagram
pin (see Figure 5).
CCDR
4.5V÷14V
LDO
5.3 Bypassing the LDO to avoid the voltage drop with low Vcc
The LDO can be by passed by providing 5 V voltage directly to V
V
pins must be shorted together as shown in Figure 6. V
CCDR
CCDR
at least 1 μF capacitor to sustain the internal LDO during the recharge of the bootstrap
capacitor. V
also represents a voltage reference for Tmask pin, S/O/U pin (L6730) or
CCDR
CC/O/U pin (L6730B) and PGOOD pin (see Table 4: Pin connection).
If Vcc
≈ 5 V the internal LDO works in dropout with an output resistance of about 1 Ω.
The maximum LDO output current is about 100 mA, and so the output voltage drop can be
100 mV. The LDO can be bypassed to avoid this.
. In this case Vcc and
CCDR
pin must be filtered with
Doc ID 11938 Rev 3 15/52
Device description L6730 - L6730B
Figure 6. Bypassing the LDO
5.4 Internal and external references
It is possible to set two internal references, 0.6 V and 1.2 V, or provide an external reference
from 0 V to 2.5 V. The maximum value of the external reference depends on the V
V
= 4 V the clamp operates at about 2 V (typ.), while with VCC greater than 5 V the
CC
CC
: with
maximum external reference is 2.5 V (typ).
● V
● V
● V
from 0% to 80% of V
EAREF
from 80% to 95% of V
EAREF
from 95% to 100% of V
EAREF
−> External reference
CCDR
−> V
CCDR
CCDR
−> V
REF
REF
= 1.2 V
= 0.6 V
Providing an external reference from 0V to 450 mV the output voltage will be regulated but
some restrictions must be considered:
● The minimum OVP threshold is set at 300 mV.
● The under-voltage-protection doesn’t work.
● The PGOOD signal remains low.
To set the resistor divider it must be considered that a 100 kΩ pull-down resistor is
integrated into the device (see Figure 7.). Finally it must be taken into account that the
voltage at the EAREF pin is captured by the device at the start-up when Vcc is about 4 V.
16/52 Doc ID 11938 Rev 3
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