ST L6726A User Manual

Feature

■ Flexible power supply from 5 V to 12 V

■ Power conversion input as low as 1.5 V

■ 1% output voltage accuracy

■ High-current integrated drivers

■ Adjustable output voltage

■ 0.8 V internal reference

■ Sensorless and programmable OCP across

Low-side R

■

Oscillator internally fixed at 270 kHz

■ Programmable soft-start

■ Ls-less start up

■ Disable function

■ FB disconnection protection

■ SO-8 package

dsON

L6726A

Single phase PWM controller

SO-8

Description

L6726A is a single-phase step-down controller
with integrated high-current drivers that provides
complete control logic, protections and reference
voltage to realize in an easy and simple way
general DC-DC converters by using a compact
SO-8 package.

Device flexibility allows managing conversions
with power input V
supply voltage ranging from 5 V to 12 V.

as low as 1.5 V and device

IN

L6726A provides simple control loop with trans-

Applications

■ Subsystem power supply (MCH, IOCH, PCI...)

■ Memory and termination supply

■ CPU and DSP power supply

■ Distributed power supply

■ General DC / DC converters

conductance error amplifier. The integrated 0.8 V
reference allows regulating output voltage with
±1% accuracy over line and temperature
variations. Oscillator is internally fixed to 270 kHz.

L6726A provides programmable over current
protection. Current information is monitored
across the low-side MOSFET R

saving the

dsON

use of expensive and space-consuming sense
resistors.

FB disconnection protection prevents excessive
and dangerous output voltages in case of floating
FB pin.

Table 1. Device summary

Order codes Package Packaging

L6726A SO-8 Tube

L6726ATR SO-8 Tape and reel

March 2010 Doc ID 12754 Rev 4 1/35

www.st.com

35

Contents L6726A

Contents

1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4

1.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.1 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6 Soft start and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6.1 Low-side-less start up (LSLess) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6.2 Enable / disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.1 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.1.1 Overcurrent threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.2 Feedback disconnection protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.3 Undervoltage lock out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

8 Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.1 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.2 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.3 Soft-start time calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8.4 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8.5 Embedding L6726A-based VRs… . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2/35 Doc ID 12754 Rev 4

L6726A Contents

9 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

9.1 Output inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

9.2 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

9.3 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

10 20 A demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

10.1 Board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10.1.1 Power input (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10.1.2 Power output (VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10.1.3 IC additional supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10.1.4 Test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10.1.5 Demonstration board efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

11 5 A demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

11.1 Board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

11.1.1 Power input (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

11.1.2 Power output (VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

11.1.3 IC additional supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

11.1.4 Test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

11.1.5 Demonstration board efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

12 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Doc ID 12754 Rev 4 3/35

Typical application circuit and block diagram L6726A

1 Typical application circuit and block diagram

1.1 Application circuit

Figure 1. Typical application circuit

VCC = 5V to 12V

R

R

FB

OS

VIN = 1.5V to 19V

C

DEC

6

FB

7

COMP

C

C

P

R

/ DIS

F

F

3

GND

5

VCC

UGATE

PHASE

L6726A

BOOT

LGATE

/ OC

D

R

D

1

C

BOOT

2

R

R

R

OCSET

gHS

gLS

8

4

HS

LS

C

HF

L

R

SN

C

SN

C

C

(1)

BULK

Vout

OUT

LOAD

L6726A Reference Schematic

(1) Up to 12V with Vcc > 5V

1.2 Block diagram

Figure 2. Block diagram

SS

I

OSCILLATOR

L6726A

VCC

CONTROL LOGIC

& PROTECTIONS

CLOCK

TRANSCONDUCTANCE

ERROR AMPLIFIER

DISABLE

Q

S

R

+

-

OCP

PWM

0.8V

V

OCTH

CROSS CONDUCTION

ADAPTIVE ANTI

I

HS

VCC

LS

OCSET

BOOT

UGATE

PHASE

LGATE
/ OC

GND

/ DIS

COMP

4/35 Doc ID 12754 Rev 4

FB

L6726A Pins description and connection diagrams

2 Pins description and connection diagrams

Figure 3. Pins connection (top view)

LGATE / OC

2.1 Pin descriptions

Table 2. Pins descriptions

Pin n Name Function

1BOOT

2 UGATE HS driver output. Connect to HS MOSFET gate.

3GND

4 LGATE / OC

BOOT

UGATE

GND

HS driver supply.
Connect through a capacitor (100 nF) to the floating node (LS-drain) pin

and provide necessary bootstrap diode from VCC.

All internal references, logic and drivers are connected to this pin.
Connect to the PCB ground plane.

LGATE. LS driver output. Connect to LS MOSFET gate.
OC. Over current threshold set. During a short period of time following VCC

rising over UVLO threshold, a 10μA current is sourced from this pin.
Connect to GND with an R
Threshold. The resulting voltage at this pin is sampled and held internally
as the OC set point. Maximum programmable OC threshold is 0.55 V. A
voltage greater than 0.75V (max) activates an internal clamp and causes
OC threshold to be set at 400 mV. R
default threshold.

1

2

L6726A

3

4

8

PHASE

7

COMP / DIS

6

FB

5

VCC

resistor greater than 5kΩ to program OC

OCSET

not connected sets the 400 mV

OCSET

5VCC

6FB

7 COMP / DIS

8 PHASE

Device and LS driver power supply.
Operative range from 4.1 V to 13.2 V. Filter with at least 1μF MLCC to GND.

Error amplifier inverting input.
Connect with a resistor R

resistor R
reference.

COMP. Error amplifier output. Connect with an R
compensate the device control loop in conjunction to the FB pin.

During the soft-start phase, a 10 μA current is sourced from this pin so the
compensation capacitors also act to program the SS time.

DIS. The device can be disabled by pulling this pin lower than 0.4 V (min).
Setting free the pin, the device enables again.

HS driver return path, current-reading and adaptive-dead-time monitor.
Connect to the LS drain to sense R
This pin is also used by the adaptive-dead-time control circuitry to monitor
when HS MOSFET is OFF.

to the output regulated voltage. Additional

to GND may be used to regulate voltages higher than the

OS

Doc ID 12754 Rev 4 5/35

FB

- CF // CP to GND to

F

drop to measure the output current.

dsON

Pins description and connection diagrams L6726A

2.2 Thermal data

Table 3. Thermal data

Symbol Parameter Value Unit

R

thJA

T

MAX

T

STG

T

J

1. Measured with the component mounted on a 2S2P board in free air (6.7 cm x 6.7 cm, 35 μm (P) and

17.5 μm (S) copper thickness).

Thermal resistance junction to ambient

Maximum junction temperature 150 °C

Storage temperature range -40 to 150 °C

Junction temperature range -20 to 150 °C

(1)

85 °C/W

6/35 Doc ID 12754 Rev 4

L6726A Electrical specifications

3 Electrical specifications

3.1 Absolute maximum ratings

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit

V

V

BOOT

V

UGATE

V

PHASE

V

LGATE

CC

to GND -0.3 to 15 V

to PHASE
to GND

to PHASE
to PHASE; t < 50ns
to GND

-0.3 to (V

BOOT

V

BOOT

15
45

- V

-1
+ 0.3

PHASE)

+ 0.3

to GND -8 to 30 V

to GND
to GND; t < 50ns

-0.3 to V

-2.5

CC

+ 0.3

FB, COMP to GND -0.3 to 3.6 V

3.2 Electrical characteristics

VCC = 12 V; TA = -20 °C to +85 °C unless otherwise specified.

CC

IN

Device supply voltage

Conversion input voltage

See Figure 1

< 7.0 V

V

CC

4.1 13.2 V

13.2 V

19.0 V

Table 5. Electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

Recommended operating conditions

V

V

V

V

V

Supply current and power-ON

I

CC

I

BOOT

VCC supply current UGATE and LGATE = OPEN 6 mA

BOOT supply current UGATE = OPEN; PHASE to GND 0.5 mA

UVLO VCC Turn-ON VCC rising 4.1 V

Hysteresis 0.2 V

Oscillator

T

F

SW

Main oscillator accuracy

= 0 °C to +70 °C 243 270 297

A

225 270 315

ΔV

d

OSC

MAX

PWM ramp amplitude 1.1 V

Maximum duty cycle 80 %

Doc ID 12754 Rev 4 7/35

kHz

Electrical specifications L6726A

Table 5. Electrical characteristics (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Reference

V

= 0.8 V, TA = 0 °C to 70 °C -1 - 1

Output voltage accuracy

Transconductance error amplifier

gm Transconductance

I

FB

A

F

I

COMP

0

0

Input bias current Sourced from FB 100 nA

Open loop gain

Unity gain

(1)

Current capability

(1)

(1)

Soft-Start and disable

OUT

= 0.8 V -1.5 - 1.5

V

OUT

%

5mS

70 dB

4MHz

Source current 360 μA

Sink current -360 μA

I

SS

Soft-start current From COMP pin 10 μA

DIS Disable threshold COMP falling 0.4 0.5 V

Gate drivers

I

UGATE

R

UGATE

I

LGATE

R

LGATE

HS source current BOOT - PHASE = 5 V to 12 V 1.5 A

HS sink resistance BOOT - PHASE = 5 V to 12 V 1.1 Ω

LS source current VCC = 5 V to 12 V 1.5 A

LS sink resistance VCC = 5 V to 12 V 0.65 Ω

Over-current protection

I

OCSET

V

OC_SW

V

OCTH_FIXED

1. Guaranteed by design, not subject to test.

OCSET current source

OC switch-over threshold V

Fixed OC threshold V

Sourced from LGATE pin.
See Section 7.1.1

LGATE/OC

PHASE

rising 780 mV

to GND -400 mV

10 μA

8/35 Doc ID 12754 Rev 4

L6726A Device description

4 Device description

L6726A is a single-phase PWM controller with embedded high-current drivers that provides
complete control logic and protections to realize in an easy and simple way a general DC­DC step-down converter. Designed to drive N-channel MOSFETs in a synchronous buck
topology, with its high level of integration this 8-pin device allows reducing cost and size of
the power supply solution.

L6726A is designed to operate from a 5 V or 12 V supply bus. Thanks to the high precision

0.8V internal reference, the output voltage can be precisely regulated to as low as 0.8 V with
±1% accuracy over line and temperature variations (between 0 °C and +70 °C). The
switching frequency is internally set to 270 kHz.

This device provides a simple control loop with externally compensated transconductance
error-amplifier and programmable soft start. Low-side-less feature allows the device to
perform soft-start over pre-charged output avoiding negative spikes at the load side.

In order to avoid load damages, L6726A provides programmable threshold over current
protection. Output current is monitored across low-side MOSFET R
expensive and space-consuming sense resistor. L6726A also features FB disconnection
protection, preventing dangerous uncontrolled output voltages in case of floating FB pin.

, saving the use of

dsON

Doc ID 12754 Rev 4 9/35

Driver section L6726A

5 Driver section

The integrated high-current drivers allow using different types of power MOSFET (also
multiple MOSFETs to reduce the equivalent R

The driver for high-side MOSFET uses BOOT pin for supply and PHASE pin for return. The
driver for low-side MOSFET uses the VCC pin for supply and GND pin for return.

The controller embodies an anti-shoot-through and adaptive dead-time control to minimize
low side body diode conduction time, maintaining good efficiency while saving the use of
Schottky diode:

● to check for high-side MOSFET turn off, PHASE pin is sensed. When the voltage at

PHASE pin drops down, the low-side MOSFET gate drive is suddenly applied;

● to check for low-side MOSFET turn off, LGATE pin is sensed. When the voltage at

LGATE has fallen, the high-side MOSFET gate drive is suddenly applied.

If the current flowing in the inductor is negative, voltage on PHASE pin will never drop. To
allow the low-side MOSFET to turn-on even in this case, a watchdog controller is enabled: if
the source of the high-side MOSFET doesn't drop, the low side MOSFET is switched on so
allowing the negative current of the inductor to recirculate. This mechanism allows the
system to regulate even if the current is negative.

), maintaining fast switching transition.

dsON

Power conversion input is flexible: 5 V, 12 V bus or any bus that allows the conversion (See
maximum duty cycle limitation and recommended operating conditions) can be chosen
freely.

10/35 Doc ID 12754 Rev 4

L6726A Driver section

5.1 Power dissipation

L6726A embeds high current MOSFET drivers for both high side and low side MOSFETs: it
is then important to consider the power that the device is going to dissipate in driving them
in order to avoid overcoming the maximum junction operative temperature.

Two main terms contribute in the device power dissipation: bias power and drivers power.

● Device bias power (P

supply pins and it is simply quantifiable as follow (assuming to supply HS and LS
drivers with the same VCC of the device):

) depends on the static consumption of the device through the

DC

P

DC

● Drivers power is the power needed by the driver to continuously switch on and off the

external MOSFETs; it is a function of the switching frequency, the voltage supply of the
driver and total gate charge of the selected MOSFETs. It can be quantified considering
that the total power P
dissipated by three main factors: external gate resistance (when present), intrinsic
MOSFET resistance and intrinsic driver resistance. This last term is the important one
to be determined to calculate the device power dissipation. The total power dissipated
to switch the MOSFETs results:

P

SW

where V

External gate resistors helps the device to dissipate the switching power since the same
power P
resulting in a general cooling of the device.

Figure 4. Soft start (left) and disable (right)

will be shared between the internal driver impedance and the external resistor

SW

BOOT

- V

PHASE

dissipated to switch the MOSFETs (easy calculable) is

SW

F

Q

SW

is the voltage across the bootstrap capacitor.

gHS

V

CCICCIBOOT

V

BOOTVPHASE

+()⋅=

–()Q

⋅+⋅[]⋅=

gLSVCC

Doc ID 12754 Rev 4 11/35

Soft start and disable L6726A

6 Soft start and disable

L6726A implements a soft start to smoothly charge the output filter avoiding high in-rush
currents to be required from the input power supply. The device sources a 10 µA soft start
current from COMP, linearly charging the compensation network capacitors. The ramping
COMP voltage is compared to the oscillator triangular waveform generating PWM pulses of
increasing width that charge the output capacitors.

When the FB voltage crosses 800 mV, the output voltage is in regulation: soft start phase
will end and the transconductance error amplifier output will be enabled closing the control
loop.

In the event of an over current during soft start, the over current logic will override the soft
start sequence and will shut down the PWM logic and both the high side and low side gates.
This condition is latched, cycle VCC to recover.

The device sources soft start current only when VCC power supply is above UVLO
threshold and over current threshold setting phase has been completed.

6.1 Low-side-less start up (LSLess)

L6726A performs a special sequence in enabling LS driver to switch: during the soft-start
phase, the LS driver results disabled (LS = OFF) until the HS starts to switch. This avoids
the dangerous negative spike on the output voltage that can happen if starting over a pre­charged output and limits the output discharge (amount of output discharge depends on
programmed SS time length: the shorter the programmed SS, the more limited the output
discharge).

If the output voltage is pre-charged to a voltage higher than the final one, the HS would
never start to switch. In this case, LS is enabled and discharges the output to the final
regulation value.

Figure 5. LSLess startup (left) vs non-LSLess startup (right)

6.2 Enable / disable

The device can be disabled by pushing COMP / DIS pin under 0.4 V (min). In this condition
HS and LS MOSFETs are turned off, and the 10
pin. Setting free the pin, the device enables again performing a new SS.

12/35 Doc ID 12754 Rev 4

μA SS current is sourced from COMP / DIS

L6726A Protections

7 Protections

7.1 Overcurrent protection

The overcurrent feature protects the converter from a shorted output or overload, by sensing
the output current information across the low side MOSFET drain-source on-resistance,
R

. This method reduces cost and enhances converter efficiency by avoiding the use of

dsON

expensive and space-consuming sense resistors.

The low side R
node when LS MOSFET is turned on with the programmed OCP threshold voltage,
internally held. If the monitored voltage drop (GND to PHASE) exceeds this threshold, an
Overcurrent event is detected. If two overcurrent events are detected in two consecutive
switching cycles, the protection will be triggered and the device will turn off both LS and HS
MOSFETs in a latched condition.

To recover from over current protection triggered, VCC power supply must be cycled.

current sense is implemented by comparing the voltage at the PHASE

dsON

7.1.1 Overcurrent threshold setting

L6726A allows to easily program an overcurrent threshold ranging from 50 mV to 550 mV,
simply by adding a resistor (R

During a short time following VCC rising over UVLO threshold, an internal 10µA current
(I
voltage drop will be sampled and internally held by the device as overcurrent Threshold. The
OC setting procedure overall time length ranges from 5.5 ms to 6.5 ms, proportionally to the
threshold being set.

Connecting a R

R

If the voltage drop across R
inrush current and noise. This can result in undesired OCP triggering. In this case, consider
increasing R

In case R
default value: an internal safety clamp on LGATE is triggered as soon as LGATE voltage
reaches 700 mV (typ), enabling the 400 mV default threshold and suddenly ending OC
setting phase.

) is sourced from LGATE pin, determining a voltage drop across R

OCSET

resistor between LGATE and GND, the programmed threshold will be:

OCSET

I

I

OCth

values range from 5 kΩ to 55 kΩ.

OCSET

OCSET

OCSETROCSET

------------------------------------------- -=

value.

OCSET

is not connected, the device switches the OCP threshold to a 400 mV

R

⋅

dsON

OCSET

) between LGATE and GND.

OCSET

is too low, the system will be very sensitive to start-up

OCSET

. This

See Figure 6 for OC threshold setting procedure timings picture and oscilloscope sample
waveforms.

7.2 Feedback disconnection protection

In order to provide load protection even if FB pin is not connected, a 100 nA bias current is
always sourced from this pin. If FB pin is not connected, bias current will permanently pull
up FB: this forces COMP pin low, avoiding output voltage rising to dangerous levels.

Doc ID 12754 Rev 4 13/35

Protections L6726A

Figure 6. OC threshold setting procedure timings (top) and waveforms (bottom)

R

R

OCSET

connected

not connected

OCSET

UVLO Th

PWM ram p

bottom edge

Enable Th

700mV

VCC

COMP

LGATE

5.5ms - 6.5ms

Setting Procedure

t

DELAY

UVLO Th

PWM ramp

bottom edge

Enable Th

700mV

VCC

COMP

LGATE

Setting Procedure

t

DELAY

7.3 Undervoltage lock out

In order to avoid anomalous behaviors of the device when the supply voltage is too low to
support its internal rails, UVLO is provided: the device will start up when VCC reaches
UVLO upper threshold and will shutdown when VCC drops below UVLO lower threshold.

The 4.1 V maximum UVLO upper threshold allows L6726A to be supplied from 5 V and 12 V
busses in or-ing diode configuration.

Figure 7. OCP trip, default threshold, LS: STD38NH02L (left) UVLO turn off (right)

14/35 Doc ID 12754 Rev 4

L6726A Application details

8 Application details

8.1 Output voltage selection

L6726A is capable to precisely regulate an output voltage as low as 0.8 V. In fact, the device
comes with a fixed 0.8 V internal reference that guarantees the output regulated voltage to
be within ±1% tolerance over line and temperature variations between 0 °C and 70 °C
(excluding output resistor divider tolerance, when present).

Output voltage higher than 0.8 V can be achieved by adding a resistor R
and ground. Referring to Figure 1, the steady state DC output voltage will be:

V

OUT

where V

REF

is 0.8 V.

8.2 Compensation network

The control loop shown in Figure 8 is a voltage mode control loop. The error amplifier is a
transconductance type with fixed gain (3.3 ms typ.). The FB voltage is regulated to the
internal reference, thus the output voltage is fixed accordingly to the output resistor divider
(when present).

Transconductance error amplifier output current generates a voltage across Z
compared to oscillator saw-tooth waveform to provide PWM signal to the driver section.
PWM signal is then transferred to the switching node with V
filtered by the output filter.

Figure 8. PWM control loop

OSC

ΔV

OSC

_

+

PWM

COMPARATOR

V

R

⎛⎞

1

REF

⋅=

---------- -+

⎝⎠

R

V

IN

L R

between FB pin

OS

FB

OS

, which is

F

amplitude. This waveform is

IN

V

OUT

C

OUT

ESR

C

R

F

F

COMP

OTA

C

P

Z

F

V

REF

+

_

FB

R

FB

R

OS

OUTPUT
DIVIDER

The converter transfer function is the small signal transfer function between the voltage at
the output node of the EA (COMP) and V
conjugate) at frequency F

depending on the L-C

LC

Doc ID 12754 Rev 4 15/35

. This function has a double pole (complex

OUT

resonance and a zero at F

OUT

ESR

Application details L6726A

depending on the output capacitor ESR. The DC gain of the modulator is simply the input
voltage V

V

OUT

divided by the peak-to-peak oscillator voltage ΔV

IN

OSC

.

is scaled and transferred to FB node by the output resistor divider.

The compensation network closes the loop joining FB and COMP node with transfer
function ideally equal to -gm

·Z

.

F

Compensation goal is to close the control loop assuring high DC regulation accuracy, good
dynamic performances and stability. To achieve this, the overall loop needs high DC gain,
high bandwidth and good phase margin.

High DC gain is achieved giving an integrator shape to compensation network transfer
function. Loop bandwidth (F
should not exceed F

/2π. To achieve a good phase margin, the control loop gain has to

SW

) can be fixed choosing the right RF; however, for stability, it

0dB

cross 0 dB axis with -20 dB/decade slope.

As an example, Figure 9 shows an asymptotic bode plot of a type II compensation.

Figure 9. Example of type II compensation.

Gain

[dB]

OTA

open loop

gain

closed loop

gain

compensation

gain

convert er

open l oop

gain

0dB

F

Z

F

P

20log (gm·RF)

20log [V

F

0dB

/ΔV

IN

OSC·ROS

Log (Freq)

/(RFB+ROS)]

F

LC

● Open loop converter singularities:

F

a)

b)

● Compensation Network singularities frequencies:

a)

b)

LC

F

F

F

ESR

Z

P

1

--------------------------------- -=

2π LC

⋅

------------------------------------------- -=

2π C

1

------------------------------=

⋅⋅

2π R

FCF

--------------------------------------------------=

⋅⋅

2π R

F

OUT

1

ESR⋅⋅

OUT

1

CFCP⋅

⎛⎞

-------------------- -

⎝⎠

C

+

FCP

F

ESR

16/35 Doc ID 12754 Rev 4

L6726A Application details

Type II compensation relies on the zero introduced by the output capacitors bank to achieve
stability. Thus, a needed condition to successfully apply type II compensation is

F

<

ESRF0dB

(usually true when output capacitor is based on electrolytic, aluminium electrolytic or
tantalum capacitor).

To define compensation network components values, the below suggestions may be
followed:

a) Set the output resistor divider in order to obtain the desired output voltage:

FB

OS

V

-------------- 1–=
V

OUT

REF

and ROS ranges from some hundreds of Ω to some kΩ

FB

R

-----------

R

Usual values of R
(consider trade-off between power dissipation on output resistor divider and offset
introduced by FB bias current).

If the desired output voltage is equal to internal reference, R
FB pin can be directly connected to V

b) Set R

in order to obtain the desired closed loop regulator bandwidth according to

F

OUT

.

has to be NC and

OS

the approximated formula:

R

If V

OUT

c) Place F

C

F

d) Place F

C

C

⋅⋅⋅=

F

ΔV

OSC

------------------ -

V

IN

SW

1–⋅⋅⋅

F

⋅

0dBFESR

-------------------------------

F

= V

Z

P

P

2

F

LC

, just consider (RFB+ROS)/ROS factor equal to 1.

REF

below FLC (typically 0.2·FLC):

5

---------------------------------=

⋅⋅

2π R

FFLC

at 0.5·FSW:

----------------------------------------------------

π RFCFF

R

1

--------

----------------------------

gm

1

------------------------------ -

≅=

π RFF

⋅⋅

+

FBROS

R

OS

SW

e) Check that compensation network gain is lower than open loop transconductance

EA gain.

f) Estimate phase margin obtained (it should be greater than 45°) and repeat,

modifying parameters, if necessary.

Doc ID 12754 Rev 4 17/35

Application details L6726A

8.3 Soft-start time calculation

To calculate SS time (tSS), the following approximated equation can be used (CP<<CF):

V

OUT

--------------

C

⋅⋅

t

SS

F

--------------------------------------------------=

ΔV

V

IN

OSC

I

SS

The previous equation refers only to V
OC setting phase or COMP set free to the beginning of V
approximately estimated as follow:

t

delay

Once calculated t

CF0.8V⋅

------------------------=

I

SS

, also the current delivered by the converter during SS to charge the

SS

output capacitor bank can be estimated:

C

I

startup

OUTVOUT

--------------------------------- -=

8.4 Layout guidelines

L6726A provides control functions and high current integrated drivers to implement high­current step-down DC-DC converters. In this kind of application, a good layout is very
important.

The first priority when placing components for these applications has to be reserved to the
power section, minimizing the length of each connection and loop as much as possible. To
minimize noise and voltage spikes (EMI and losses) power connections (highlighted in

Figure 10) must be a part of a power plane and anyway realized by wide and thick copper

traces: loop must be anyway minimized. The critical components, i.e. the power MOSFETs,
must be close one to the other. The use of multi-layer printed circuit board is recommended.

ramp up time. The time elapsed from the end of

OUT

ramp up (see Figure 6) can be

OUT

⋅

t

SS

Figure 10. Power connections (heavy lines)

UGATE

PHASE

L6726A

LGATE

GND

The input capacitance (C

), or at least a portion of the total capacitance needed, has to be

IN

placed close to the power section in order to eliminate the stray inductance generated by the
copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be
connected near the HS drain.

Use proper number of vias when power traces have to move between different planes on the
PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the
same high-current trace on more than one PCB layer will reduce the parasitic resistance
associated to that connection.

18/35 Doc ID 12754 Rev 4

V

IN

C

IN

L

C

OUT

LOAD

L6726A Application details

Connect output bulk capacitors (C

) as near as possible to the load, minimizing parasitic

OUT

inductance and resistance associated to the copper trace, also adding extra decoupling
capacitors along the way to the load when this results in being far from the bulk capacitors
bank.

Gate traces and phase trace must be sized according to the driver RMS current delivered to
the power MOSFET. The device robustness allows managing applications with the power
section far from the controller without losing performances. Anyway, when possible, it is
recommended to minimize the distance between controller and power section. See

Figure 11 for drivers current paths.

Small signal components and connections to critical nodes of the application, as well as
bypass capacitors for the device supply, are also important. Locate bypass capacitor (VCC
and Bootstrap capacitor) and loop compensation components as close to the device as
practical. For over current programmability, place R

close to the device and avoid

OCSET

leakage current paths on LGATE / OC pin, since the internal current source is only 10 μA

Systems that do not use Schottky diode in parallel to the Low-Side MOSFET might show big
negative spikes on the PHASE pin. This spike must be limited within the absolute maximum
ratings (for example, adding a gate resistor in series to HS MOSFET gate, or a phase
resistor in series to PHASE pin), as well as the positive spike, but has an additional
consequence: it causes the bootstrap capacitor to be over-charged. This extra-charge can
cause, in the worst case condition of maximum input voltage and during particular
transients, that boot-to-phase voltage overcomes the absolute maximum ratings also
causing device failures. It is then suggested in this case to limit this extra-charge by adding a
small resistor in series to the bootstrap diode (R

in Figure 1).

D

Figure 11. Drivers turn-on and turn-off paths

LS DRIVER LS MOSFET

VCC

C

GD

R

GATERINT

LGATE

C

GS

GND

C

DS

HS DRIVER HS MOSFET

BOOT

C

GD

R

GATERINT

UGATE

C

GS

PHASE

R

PHASE

C

DS

Doc ID 12754 Rev 4 19/35

Application details L6726A

8.5 Embedding L6726A-based VRs…

When embedding the VR into the application, additional care must be taken since the whole
VR is a switching DC/DC regulator and the most common system in which it has to work is a
digital system such as MB or similar. In fact, latest MBs have become faster and more
powerful: high speed data busses are more and more common and switching-induced noise
produced by the VR can affect data integrity if additional layout guidelines are not followed.
Few easy points must be considered mainly when routing traces in which switching high
currents flow (switching high currents cause voltage spikes across the stray inductance of
the traces causing noise that can affect the near traces):

When reproducing high current path on internal layers, keep all layers the same size in order
to avoid “surrounding” effects that increase noise coupling.

Keep safe guard distance between high current switching VR traces and data busses,
especially if high-speed data busses, to minimize noise coupling.

Keep safe guard distance or filter properly when routing bias traces for I/O sub-systems that
must walk near the VR.

Possible causes of noise can be located in the PHASE connections, MOSFETs gate drive
and Input voltage path (from input bulk capacitors and HS drain). Also GND connection
must be considered if not insisting on a power ground plane. These connections must be
carefully kept far away from noise-sensitive data busses.

Since the generated noise is mainly due to the switching activity of the VR, noise emissions
depend on how fast the current switches. To reduce noise emission levels, it is also possible,
in addition to the previous guidelines, to reduce the current slope and thus to increase the
switching times: this will cause, as a consequence of the higher switching time, an increase
in switching losses that must be considered in the thermal design of the system.

20/35 Doc ID 12754 Rev 4

L6726A Application Information

9 Application Information

9.1 Output inductor

Inductor value is defined by a compromise between dynamic response, ripple, efficiency,
cost and size. Usually, inductance is calculated to maintain inductor ripple current (ΔI
between 20% and 30% of maximum output current. Given the switching frequency (F
the input voltage (V

), the output voltage (V

IN

) and the desired ripple current (ΔIL),

OUT

inductance can be calculated as follows:

L

SW

)

),

L

VINV

–

----------------------------- -

F

SWΔIL

⋅

OUT

V

--------------

⋅=

OUT

V

IN

Figure 12 shows the ripple current vs. the output voltage for different inductance, with

V

= 5 V and VIN = 12 V.

IN

Increasing inductance reduces inductor ripple current (and output voltage ripple
accordingly) but, at the same time, increases the converter response time to load transients.
Higher inductance means that the inductor needs more time to change its current from initial
to final value. Until the inductor has not finished its charging, the additional output current is
supplied by output capacitors. Minimizing the response time lead to minimize the output
capacitance required. If the compensation network is designed with high bandwidth, during
an heavy load transient the device is able to saturate duty cycle (0% or 80%). When this
condition is reached, the response time is limited only by the time required to charge the
inductor.

Figure 12. Inductor current ripple vs output voltage

12

]

10

A

[
e

l
p
p

8

i
r

t
n
e

6

r
r

u
c
r

4

o

t
c
u
d

2

n

I

0

012345

Output voltage [V]

Vin=12V, L=1uH

Vin=12V, L=2uH

Vin=5V, L=500nH

Vin=5V, L=1.5uH

Doc ID 12754 Rev 4 21/35

Application Information L6726A

9.2 Output capacitors

Output capacitors choice depends on the application constraints in point of output voltage
ripple and output voltage deviation during a load transient.

During steady-state conditions, the output voltage ripple is influenced by ESR and
capacitance of the output capacitors as follows:

ΔV

OUT_ESR

ΔV

OUT_C

Where ΔI

ΔILESR⋅=

1

-------------------------------------- -

ΔI

⋅=

L

8C

⋅⋅

OUTFSW

is the inductor current ripple. These contribution are not in phase, so total ripple

L

will be lower than the sum of their moduli. Even ESL and board parasitic inductance can
contribute significantly to output ripple.

During a load variation, the output capacitors supply to the load the additional current or
absorb the current in excess delivered by the inductor until converter reaction is completed.
In fact, even if the controller react immediately to the load transient saturating the duty cycle
to 80% or 0%, the current slew rate is limited by the inductance. At first approximation,
output voltage drop, based on ESR and capacitor charge/discharge and considering an
ideal load-step, can be estimated as follows:

ΔV

OUT_ESR

ΔV

OUT_C

Where ΔV
the load appliance or V

ΔI

L ΔI

------------------------------------- -=

2C

⋅⋅

is the voltage applied to the inductor during the transient ( for

L

ESR⋅=

OUT

⋅

OUT

OUTΔVL

2

for the load removal).

OUT

D

MAXVINVOUT

–⋅

MLCC capacitors typically have low ESR to minimize the ripple but also have low
capacitance that do not minimize the capacitive voltage deviation during load transient. On
the contrary, electrolytic capacitors usually have higher capacitance to minimize capacitive
voltage deviation during load transient, but also higher ESR value resulting in higher ripple
voltage and resistive voltage drop. For these reasons, a mix between electrolytic and MLCC
capacitor is usually suggested to minimize ripple as well as reducing voltage deviation in
dynamic conditions.

9.3 Input capacitors

The input capacitor bank is designed mainly to stand input rms current, which depends on
output current (I

I

rmsIOUT

The equation reaches its maximum value, I
capacitor ESR:

PESRI

22/35 Doc ID 12754 Rev 4

⋅=

rms

) and duty-cycle (D) for the regulation as follows:

OUT

D1D–()⋅⋅=

OUT

2

/2, when D = 0.5. Losses depend on input

L6726A 20 A demonstration board

10 20 A demonstration board

L6726A demonstration board realizes on a four-layer PCB a step-down DC/DC converter
and shows the operation of the device in a general purpose application. Input voltage can
range from 5 V to 12 V bus. Output voltage is programmed to 1.25 V. The voltage regulator
can deliver up to 20 A output current. The switching frequency is 270 kHz.

Figure 13. 20 A demonstration board (left) and components placement (right)

Figure 14. 20 A demonstration board top (left) and bottom (right) layers

Doc ID 12754 Rev 4 23/35

20 A demonstration board L6726A

Figure 15. 20 A demonstration board inner layers

24/35 Doc ID 12754 Rev 4

L6726A 20 A demonstration board

&

R

P

S

H

Q

V

D

W

L

R

Q



1

H

W

Z

R

U

N

$

G

G

L

W

L

R

Q

D

O



6

2





P

R

V

I

H

W



D

Q

G



,

Q

G

X

F

W

R

U

ᤡ

I

R

U



I

X

U

W

K

H

U



F

R

P

S

D

W

L

E

L

O

L

W

\

ᤢ

Figure 16. 20 A demonstration board schematic

PHASE

8
7
6
51

Q3NCQ3

NC

L1NCL1

NC

1 2

PHASE

8
7
6

PHASE OUT

51

Q2NCQ2

NC

HSD

8
7
6
51

Q1NCQ1

NC

VIN1VIN1

NC

NC

NC

NC

NC

NC

GNDIN1GNDIN1

VIN_POWER

GNDIN_POWER0VCC

C3NCC3

C2

C1

C9NCC9

C8NCC8

C7NCC7

C6NCC6

C5NCC5

C4NCC4

NC

1800uFC21800uF

1800uFC11800uF

R160R16

0

GND

3
2

4

LSG2

GND

3
2

4

LSG1

PHASE

3
2

C13

VIN_POWER

HSDHSD

C10

C10

100nF

100nF

C381uF C381uF

0

GND

C13

4.7uF

4.7uF

C12

C12

4.7uF

4.7uF

C11

C11

4.7uF

4.7uF

Q4

STD70NH02LT4

Q4

STD70NH02LT4

1

R30R3

UGATEUGATE

UGATE HSG

4

HSG

0 0 00 0 00

BOOT

R2

3.3R23.3

0 0

D1

1N4148D11N4148

0

GNDGND

VCC

VCCVCC

GNDCC

3 2

0

0 0 0

R17

R17

PHASEPHASE

L6726A/27

L6726A/27

U1

U1

VOUT1VOUT1

8

PHASE

BOOT

1

BOOT PHASE

VOUT

OUT

12

L2

L2

3.3

3.3

COMP

7

COMP

UGATE

2

UGATE

C22NCC22

C21NCC21

C20NCC20

C19NCC19

C18

C18

C17NCC17

C16NCC16

C15NCC15

T60-18 6Ts

T60-18 6Ts

R4

Q6NCQ6

Q5

Q5

LGATELGATE

VCCVCC_PINLGATE

3.3R13.3

FB

1uF

1uF

6

5

FB

VCC

GND

LGATE

3

4

GND

1.8R41.8

GNDOUT

GNDOUT1GNDOUT1

NC

NC

NC

NC

2200uF

2200uF

NC

NC

NC

C23

6.8nF

C23

6.8nF

NC

0

3 2

1

STD95NH02LT4

STD95NH02LT4

0

3 2

1

LSG1

0

R50R5

LGATELGATE

R1

C14

C14

R18

20k

R18

20k

0

0 0 0 0 0 0 0 0 0

LSG2LSG2LSG2LSG2LSG2LSG2LSG2LSG2LSG2LSG2LSG2LSG2

R15NCR15

0

C34NCC34

NC

C33NCC33

NC

C32NCC32

NC

C31NCC31

NC

C30NCC30

NC

C29NCC29

OUT

NC

C28NCC28

NC

C27NCC27

NC

C26NCC26

NC

C25

C25

OUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUT

PHASE

NC

FB

FBFB

COMPCOMP

VCC_PIN

2200uF

2200uF

R110R11

R10NCR10

R9

R8NCR8

C24

C24

R72kR7

COMP

R6NCR6

NC

0 0 0 0 0 0 0 0 0 0

Q
R
L

W
F
Q
X
)

3

V

2

Z
R

2

O

0

O

5

D


NC

'







J

&

Q
L



W



Q



H



C37NCC37

NC

2.2kR92.2k

NC

68nF

68nF

2k

C36NCC36

R14NCR14

R13

R13

R120R12

C35

C35

NC

3.9k

3.9k

0

470pF

470pF

P

5


H



O



S



P

5

L

NC

00

7
(
6
&
2


U
R
I



7




(

5

6



&





&



2



1


U





R



I





/







5

$

5















&



1





/







5

Q





H



5

&

H





Z

1



W
H





E


5

5

\





W

!

L

!

O

L
E





L





W



$

D






S





P





R





&

/

/

Doc ID 12754 Rev 4 25/35

20 A demonstration board L6726A

Table 6. 20 A demonstration board - bill of material

Qty Reference Description Package

Capacitors

2C1, C2

1 C10 MLCC, 100 nF, 25 V, X7R SMD0603

3 C11 to C13

2 C14, C38 MLCC, 1 μF, 16 V, X7R SMD0805

2C18, C25

1 C23 MLCC, 6.8 nF, X7R

1 C35 MLCC, 470 pF, X7R

Resistors

3 R1, R2, R17 Resistor, 3R3, 1/16 W, 1% SMD0603

3 R3, R5, R16 Resistor, 0R, 1/8 W, 1%

1 R4 Resistor, 1R8, 1/8 W, 1%

2 R11, R12 Resistor, 0R, 1/16 W, 1%

1 R9 Resistor, 2K2, 1/16 W, 1%

1 R13 Resistor, 3K9, 1/16 W, 1%

1 R7 Resistor, 2K, 1/16 W, 1%

1 R18 Resistor, 20K, 1/16 W, 1%

Electrolytic Cap 1800 μF 16 V
Nippon Chemi-Con KZJ or KZG

MLCC, 4.7 μF, 1 6 V, X 5 R
Murata GRM31CR61C475MA01

Electrolytic Cap 2200 μF 6.3 V
Nippon Chemi-Con KZJ or KZG

Radial 10 x 25 mm

SMD1206

Radial 10 x 20mm

SMD06031 C24 MLCC, 68 nF, X7R

SMD0805

SMD0603

Inductor

1L1

Active components

1 D1 Diode, 1N4148 or BAT54 SOT23

1 Q5 STD70NH02LT4

1 Q6 STD95NH02LT4

1 U1 Controller, L6726A SO8

26/35 Doc ID 12754 Rev 4

Inductor, 1.25 μH, T60-18, 6Turns
Easymagnet AP106019006P-1R1M

na

DPACK

L6726A 20 A demonstration board

10.1 Board description

10.1.1 Power input (VIN)

This is the input voltage for the power conversion. The high-side MOSFET drain is
connected to this input. Supply must be compliant with VIN recommended operating
conditions and capacitors rating.

If VIN voltage is compliant also to VCC range listed in recommended operating conditions, it
can supply also the device through R16 resistor.

10.1.2 Power output (VOUT)

This is the output voltage of the power conversion. The output voltage is programmed to

1.25 V. It can be changed by replacing R13 (adjusting of compensation network may be
needed). R18 allows to adjust OCP threshold.

10.1.3 IC additional supply (VCC)

The controller can be supplied separately from the power conversion through VCC input. In
this case, to separate VCC from VIN, R16 resistor must be removed.

10.1.4 Test points

The following test points are provided to allow easy probing of important signals:

– COMP: Output of the error amplifier;

– FB: Inverting input of the error amplifier;

– PH: Phase pin of the device;

– LG: Low-side gate pin of the device;

– UG: High-side gate pin of the device.

10.1.5 Demonstration board efficiency

Figure 17. 20 A demonstration board efficiency

100

95
90

85
80

75

70
65

Efficiency [%]

60
55

50

0 2 4 6 8 10 12 14 16 18 20 22

Vin= 12V, Vout=1.25V

Vin= 5V, Vout=1.25V

Vin=12V, Vout=2.5V

Vin= 5V, Vout=2.5V

Output Current [A]

Doc ID 12754 Rev 4 27/35

5 A demonstration board L6726A

11 5 A demonstration board

L6726A demonstration board realizes on a two-layer PCB a step-down DC/DC converter
and shows the operation of the device in a general-purpose low-current application. Input
voltage can range from 5 V to 12 V bus. Output voltage is programmed at 1.25 V. The
application can deliver an output current in excess of 5 A. The switching frequency is 270
kHz.

Figure 18. 5 A demonstration board (left) and components placement (right)

Figure 19. 5 A demonstration board top (left) and bottom (right) layers

28/35 Doc ID 12754 Rev 4

L6726A 5 A demonstration board

&

R

P

S

H

Q

V

D

W

L

R

Q



1

H

W

Z

R

U

N

ᤡ

S

O

D

F

H



Q

H

D

U



W

K

H



F

R

Q

W

U

R

O

O

H

U

ᤢ

(

O

H

F

W

U

R

O

\

W

L

F



F

D

S

D

F

L

W

R

U



ᤡ

G

X

D

O



I

R

R

W

S

U

L

Q

W

ᤢ

7

D

Q

W

D

O

X

P



F

D

S

D

F

L

W

R

U

V



ᤡ

G

X

D

O



I

R

R

W

S

U

L

Q

W

ᤢ











F

H

U

D

P

L

F



F

D

S

D

F

L

W

R

U

V



ᤡ

G

X

D

O



I

R

R

W

S

U

L

Q

W

ᤢ











F

H

U

D

P

L

F



F

D

S

D

F

L

W

R

U

V



ᤡ

S

O

D

F

H



Q

H

D

U



+

6



P

R

V

ᤢ

Figure 20. 5 A demonstration board schematic

VOUT

VOUT1VOUT1

10uF

10uF

C51

C51

0

OUTOUT

10uF

10uF

C12

C12

0

12

12

L2

2.2uHL22.2uH

L3 NCL3 NC

VIN_POWER

U5B

U5B

STS9D8NH3LL

STS9D8NH3LL

HSD

65

4

100nF

100nF

C10

GNDIN1GNDIN1

VIN1VIN1

VIN_POWER

GNDIN_POWER0VCC

BAT54D1BAT54

R160R16

0

VCCVCC

0

C10

BOOT

R2 3.3R2 3.3

D1

C38

C38

GNDGND

VCCVCCVCCVCCVCCVCCVCCVCCVCCVCC

GNDCC

R3 0R3 0

UGATEUGATE

UGATE HSG1

0

1uF

1uF

GND

3

PHASEPHASE

87

PHASE

R17 3.3R17 3.3

PHASE PIN

GNDOUT

GNDOUT1GNDOUT1

C18NCC18

NC

R4

1.8R41.8

U5A

U5A

R5 0R5 0

LGATELGATE

PHASE PIN

8

U1

U1

BOOT

0

6.8nF

6.8nF

C23

C23

0 0

STS9D8NH3LL

STS9D8NH3LL

0

1

2

LSG1LSG1LSG1

LGATELGATE

VCCVCC_PIN

R1

3.3R13.3

FB

COMP

7

5

6

FB

VCC

COMP

PHASE

BOOT1UGATE2GND3LGATE/OC

UGATE

L6726A

L6726A

L6726A

L6726A

4

LGATE

GND

R18NCR18

C29ANCC29A

C30

330uF

C30

330uF

OUTOUTOUTOUTOUTOUTOUTOUT OUTOUT

C14

1uF

C14

1uF

0

C29NCC29

NC

FBFB

COMPCOMP

NC

0

C40NCC40

NC

OUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUT

C39

22uF

C39

22uF

0 0

OUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUT

C36NCC36

NC

R9

2.2kR92.2k
R14NCR14

NC

R13

3.9K

R13

3.9K

0

FBFBFB

R8NCR8

NC

R100R10

0

0

C24

220nF

C24

220nF

R7

820R7820

C35

2.2nF

C35

COMP

2.2nF

0

NC

Doc ID 12754 Rev 4 29/35

5 A demonstration board L6726A

Table 7. 5 A demonstration board - bill of material

Qty Reference Description Package

Capacitors

2C12, C51

1 C10 MLCC, 100nF, 25V, X7R SMD0603

2 C14, C38 MLCC, 1 μF, 16 V, X7R SMD0805

1C39

1C30

1 C23 MLCC, 6.8 nF, X7R

1 C35 MLCC, 2.2 nF, X7R

Resistors

1 R4 Resistor, 1R8, 1/8 W, 1% SMD0805

4 R3, R5, R10, R16 Resistor, 0R, 1/16 W, 1%

3 R1, R2, R17 Resistor, 3R3, 1/16 W, 1%

1 R9 Resistor, 2K2, 1/16 W, 1%

1 R7 Resistor, 820R, 1/16 W, 1%

10 μF, 2 5 V, X 5 R
Murata GRM31CR61E106KA12

MLCC, 22 μF, 6.3 V, X5R
Murata GRM31CR60J226ME19

330 μF, 6.3 V, 40 m
Sanyo 6TPB330M

Ω

SMD1206

SMD1206

SMD7343

SMD06031 C24 MLCC, 220 nF, X7R

SMD0603

SMD06031 R13 Resistor, 3K9, 1/16 W, 1%

Inductor

1L1

Active Components

1 D1 Diode, BAT54 SOT23

1 Q5 Mosfet, STS9D8NH3LL SO8

1 U1 Controller, L6726A SO8

11.1 Board description

11.1.1 Power input (VIN)

This is the input voltage for the power conversion. The high-side MOSFET drain is
connected to this input. Supply must be compliant with VIN recommended operating
conditions and capacitors rating.

If VIN voltage is compliant also to VCC range listed in recommended operating conditions, it
can supply also the device through R16 resistor.

Inductor, 2.20 μH,
Wurth 744324220LF

na

30/35 Doc ID 12754 Rev 4

L6726A 5 A demonstration board

11.1.2 Power output (VOUT)

This is the output voltage of the power conversion. The output voltage is programmed to

1.25 V. It can be changed by replacing R13 (adjusting of compensation network may be
needed). Adding R18 allows to adjust OCP threshold.

11.1.3 IC additional supply (VCC)

The controller can be supplied separately from the power conversion through VCC input. In
this case, to separate VCC from VIN, R16 resistor must be removed.

11.1.4 Test points

The following test points are provided to allow easy probing of important signals:

– COMP: output of the error amplifier;

– FB: inverting input of the error amplifier;

– PH: Phase pin of the device;

– LG: Low-side gate pin of the device;

– UG: High-side gate pin of the device.

11.1.5 Demonstration board efficiency

Figure 21. 5 A demonstration board efficiency

100

95
90
85
80
75
70
65

Efficiency [%]

60
55
50

01234 56

Output Current [A]

Vin = 12V, Vout = 1.25V

Vin = 5V, Vout = 1.25V

Vin = 12V, Vout = 2.5V

Vin = 5V, Vout = 2.5V

Doc ID 12754 Rev 4 31/35

Package mechanical data L6726A

12 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

®

packages, depending on their level of environmental compliance. ECOPACK®

32/35 Doc ID 12754 Rev 4

L6726A Package mechanical data

Table 8. SO-8 mechanical data

mm. inch

Dim.

Min Typ Max Min Typ Max

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

A2 1.10 1.65 0.043 0.065

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

(1)

D

E 3.80 4.00 0.15 0.157

e 1.27 0.050

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 1.27 0.016 0.050

k 0° (min.), 8° (max.)

ddd 0.10 0.004

1. D and F does not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm
(.006inch) per side.

4.80 5.00 0.189 0.197

Figure 22. Package dimensions

Doc ID 12754 Rev 4 33/35

Revision history L6726A

13 Revision history

Table 9. Document revision history

Date Revision Changes

16-Oct-2006 1 Initial release.

26-Oct-2006 2 Mechanical data dimensions updated

30-Jul-2007 3 Updated Figure 1 on page 4, tables 2, 3, 4, 5

Added:

23-Mar-2010 4

Section 9 on page 21, Section 10 on page 23, Section 11 on page 28

Updated: Table 5 on page 7

34/35 Doc ID 12754 Rev 4

L6726A

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

© 2010 STMicroelectronics - All rights reserved

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

Doc ID 12754 Rev 4 35/35