ST L6725, L6725A User Manual
L6725
L6725A
Voltage mode PWM controller with bootstrap anti-discharging system
Features
■Input voltage range from 1.8V to 18V
■Supply voltage range from 4.5V to 18V
■ Adjustable output voltage down to 0.6V with |
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±0.8% accuracy over line voltage and |
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temperature (0°C~125°C) |
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■ Fixed frequency voltage mode control |
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■ 0% to 100% duty cycle |
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■ External input voltage reference |
SO16N (Narrow) |
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■ Soft-start and inhibit |
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■ Bootstrap anti-discharging system |
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■ High current embedded drivers |
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■ Predictive anti-cross conduction control |
Applications |
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■ Programmable high-side and low-side RDS(on) |
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sense over-current-protection |
■ Low voltage distributed DC-DC |
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■ Sink current capability |
■ Graphic cards |
■Selectable switching frequency 250KHz/ 500KHz
■Power good and synch available with L6725A
■Pre-bias start up capability
■Over voltage protection
■Thermal shut-down
■Package: SO16N
Table 1. Device summary
Order codes |
Package |
Packing |
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L6725 |
SO16N |
Tube |
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L6725TR |
SO16N |
Tape & Reel |
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L6725A |
SO16N |
Tube |
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L6725ATR |
SO16N |
Tape & Reel |
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June 2007 |
Rev 5 |
1/32 |
www.st.com
Contents |
L6725 - L6725A |
Contents
1 |
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
4 |
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1.1 |
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
4 |
2 |
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
5 |
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2.1 |
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
5 |
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2.2 |
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
5 |
3 Pin connections and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.2 Internal LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 Bypassing the LDO to avoid the voltage drop with low Vcc . . . . . . . . . . . . . 11 5.4 Internal and external references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.5 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.6 Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.7 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.8 Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.9 Hiccup mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.10 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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L6725 - L6725A |
Contents |
5.11 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.12 Bootstrap anti-discharging system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.12.1 Fan's power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 |
Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
18 |
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6.1 |
Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
18 |
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6.2 |
Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
19 |
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6.3 |
Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
19 |
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6.4 |
Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
20 |
7 |
L6725 demoboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
22 |
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7.1 |
20A board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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7.2 |
5A board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
26 |
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Summary description |
L6725 - L6725A |
1 Summary description
The device is a flexible high performance PWM buck controller dedicated for low voltage distributed DC-DC. The input voltage can range from 1.8V to 18V, while the supply voltage can range from 4.5V to 18V. The output voltage is adjustable down to 0.6V.
High peak current gate drivers provide for fast switching to the external power section, and the output current can be in excess of 20A. The device is capable to manage minimum on-times (TON) shorter than 100ns making possible conversions with very low duty cycle and very high switching frequency. In order to guarantee a real overcurrent protection, also with very narrow TON, the current sense is realized both on the high-side and low-side MOSFETs. When necessary, two different current limit protections can be externally set through an external resistor. The device can sink current after the soft-start phase while, during the soft-start, the sink mode capability is disabled in order to allow a proper start-up also in pre-biased output voltage conditions. Other features are over-voltage-protection and thermal shutdown.
1.1Functional description
Figure 1. |
Block diagram |
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Vcc==414V.5V-14V18V |
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Vin = 14V - 18V |
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Vin=1.8V-14V |
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OCL |
OCH |
VCCDR |
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BOOT |
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LDO |
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SS |
Monitor |
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HGATE |
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Protection and Ref |
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OSC |
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PHASE |
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EAREF |
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L6725 |
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VOUT |
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LGATE |
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PGOOD |
+ |
- |
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0.6V |
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- |
+ |
PWM |
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PGND |
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SYNCH |
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E/A |
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+ |
- |
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GND |
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FB |
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COMP |
4/32
L6725 - L6725A |
Electrical data |
2 Electrical data
2.1Maximum rating
Table 2. Absolute maximum ratings
Symbol |
Parameter |
Value |
Unit |
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VCC |
VCC to GND and PGND, OCH |
-0.3 to 20 |
V |
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VBOOT - VPHASE |
Boot voltage |
0 to 6 |
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VHGATE - VPHASE |
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0 to VBOOT - VPHASE |
V |
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VBOOT |
BOOT |
-0.3 to 26 |
V |
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PHASE |
-1 to 20 |
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VPHASE |
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V |
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PHASE Spike, transient < 50ns (FSW = 500KHz) |
-3 |
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+24 |
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SS, FB, EAREF, OCL, LGATE, COMP, VCCDR |
-0.3 to 6 |
V |
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OCH Pin |
Maximum withstanding voltage range |
±1500 |
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Test Condition: CDF-AEC-Q100-002 "Human Body Model" |
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V |
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OTHER PINS |
±2000 |
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Acceptance Criteria: "Normal Performance" |
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2.2Thermal data
Table 3. |
Thermal data |
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Symbol |
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Description |
Value |
Unit |
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(1) |
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Max. thermal resistance junction to ambient |
50 |
°C/W |
RthJA |
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TSTG |
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Storage temperature range |
-40 to 150 |
°C |
TJ |
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Junction operating temperature range |
-40 to 125 |
°C |
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TA |
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Ambient operating temperature range |
-40 to +85 |
°C |
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1. Package mounted on demoboard
5/32
Pin connections and functions |
L6725 - L6725A |
3 Pin connections and functions
Figure 2. Pins connection (top view)
COMP |
1 |
16 |
FB |
SS/INH |
2 |
15 |
SGND |
EAREF |
3 |
14 |
SYNCH/NC |
OCL |
4 |
13 |
PGOOD/NC |
OCH |
5 |
12 |
VCC |
PHASE |
6 |
11 |
VCCDR |
HGATE |
7 |
10 |
LGATE |
BOOT |
8 |
9 |
PGND |
SO16N
Table 4. |
Pin functions |
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Pin n° |
Name |
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Function |
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1 |
COMP |
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This pin is connected to the error amplifier output and is used to compensate the |
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voltage control feedback loop. |
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The soft-start time is programmed connecting an external capacitor from this pin to |
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SS/INH |
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GND. The internal current generator forces a current of 10µA through the capacitor. |
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When the voltage at this pin is lower than 0.5V the device is disabled. |
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By setting the voltage at this pin is possible to select the internal/external reference |
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and the switching frequency: |
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VEAREF 0-80% of VCCDR -> External Reference/FSW = 250KHz |
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3 |
EAREF |
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VEAREF = 80% - 95% of VCCDR -> VREF = 0.6V/FSW = 500KHz |
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VEAREF = 95% - 100% of VCCDR ->VREF = 0.6V/FSW = 250KHz |
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An internal clamp limits the maximum VEAREF at 2.5V (typ.). The device captures the |
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analog value present at this pin at the start-up when VCC meets the UVLO threshold. |
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A resistor connected from this pin to ground sets the valley- current-limit. The valley |
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current is sensed through the low-side MOSFET(s). The internal current generator |
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sources a current of 100µA (IOCL) from this pin to ground through the external resistor |
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OCL |
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(ROCL). The over-current threshold is given by the following equation: |
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VALLEY |
= IOCL ROCL |
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2 RDSonLS |
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6/32
L6725 - L6725A |
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Pin connections and functions |
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Table 4. |
Pin functions |
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Pin n° |
Name |
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Function |
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A resistor connected from this pin and the high-side MOSFET(s) drain sets the peak- |
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current-limit. The peak current is sensed through the high-side MOSFET(s). The |
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internal 100µA current generator (IOCH) sinks a current from the drain through the |
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5 |
OCH |
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external resistor (ROCH). The over-current threshold is given by the following |
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equation: |
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I |
= IOCH ROCH |
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PEAK |
RDSonHS |
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This pin is connected to the source of the high-side MOSFET(s) and provides the |
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6 |
PHASE |
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return path for the high-side driver. This pin monitors the drop across both the upper |
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and lower MOSFET(s) for the current limit together with OCH and OCL. |
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7 |
HGATE |
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This pin is connected to the high-side MOSFET(s) gate. |
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8 |
BOOT |
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Through this pin is supplied the high-side driver. Connect a capacitor from this pin to |
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the PHASE pin and a diode from VCCDR to this pin (cathode versus BOOT). |
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9 |
PGND |
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This pin has to be connected closely to the low-side MOSFET(s) source in order to |
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reduce the noise injection into the device. |
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10 |
LGATE |
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This pin is connected to the low-side MOSFET(s) gate. |
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11 |
VCCDR |
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5V internally regulated voltage. It is used to supply the internal drivers. Filter it to |
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ground with a 1uF ceramic cap. |
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12 |
VCC |
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Supply voltage pin. The operative supply voltage range is from 4.5V to 14V. |
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PGOOD |
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In L6725 this pin is N.C. With L6725A this pin is an open collector output and it is |
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13 |
(L6725A) |
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pulled low if the output voltage is not |
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N.C. |
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within the specified thresholds (90%-110%). If not used it may be left floating. Pull-up |
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(L6725) |
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this pin to VCCDR with a 10K resistor to obtain a logical signal. |
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In L6725 this pin is N.C. With L6725A it is a Master-Slave pin. Two or more devices |
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SYNCH |
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can be synchronized by simply |
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14 |
(L6725A) |
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connecting the SYNCH pins together. The device operating with the highest FSW will |
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N.C. |
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be the Master. The Slave devices will operate with 180° phase shift from the Master. |
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(L6725) |
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The best way to synchronize devices together is to set their FSW at the same value. If |
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it is not used the SYNCH pin can be left floating. |
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15 |
SGND |
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All the internal references are referred to this pin. |
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16 |
FB |
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This pin is connected to the error amplifier inverting input. Connect it to VOUT through |
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the compensation network. This pin is also used to sense the output voltage in order |
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to manage the over voltage protection. |
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7/32
Electrical characteristics |
L6725 - L6725A |
4 Electrical characteristics
VCC = 12V, TA = 25°C unless otherwise specified.
Table 5. |
Electrical characteristics |
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Symbol |
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Parameter |
Test condition |
Min |
Typ |
Max |
Unit |
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VCC supply current |
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ICC |
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VCC Stand by current |
SS to GND |
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7 |
9 |
mA |
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VCC quiescent current |
HG = open, LG = open, PH=open |
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8.5 |
10 |
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Power-ON |
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VCC |
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Turn-ON VCC threshold |
VOCH = 1.7V |
4.0 |
4.2 |
4.4 |
V |
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Turn-OFF VCC threshold |
VOCH = 1.7V |
3.6 |
3.8 |
4.0 |
V |
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VIN OK |
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Turn-ON VOCH threshold |
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1.1 |
1.25 |
1.47 |
V |
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Turn-OFF VOCH threshold |
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0.9 |
1.05 |
1.27 |
V |
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VCCDR Regulation |
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VCCDR voltage |
VCC =5.5V to 18V |
4.5 |
5 |
5.5 |
V |
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IDR = 1mA to 100mA |
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Soft Start and Inhibit |
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ISS |
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Soft Start Current |
SS = 2V |
7 |
10 |
13 |
µA |
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SS = 0 to 0.5V |
20 |
30 |
45 |
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Oscillator |
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fOSC |
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Accuracy |
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237 |
250 |
263 |
KHz |
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450 |
500 |
550 |
KHz |
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∆VOSC |
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Ramp Amplitude |
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2.1 |
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Output Voltage |
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VFB |
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Output Voltage |
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0.597 |
0.6 |
0.603 |
V |
8/32
L6725 - L6725A |
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Electrical characteristics |
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Table 5. |
Electrical characteristics |
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Symbol |
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Parameter |
Test condition |
Min. |
Typ. |
Max. |
Unit |
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Error Amplifier |
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REAREF |
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EAREF Input Resistance |
Vs. GND |
70 |
100 |
150 |
kΩ |
IFB |
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I.I. bias current |
VFΒ = 0V |
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0.290 |
0.5 |
µA |
Ext Ref |
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2.3 |
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V |
Clamp |
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VOFFSET |
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Error amplifier offset |
Vref = 0.6V |
-5 |
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+5 |
mV |
GV |
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Open Loop Voltage Gain |
Guaranteed by design |
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100 |
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dB |
GBWP |
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Gain-Bandwidth Product |
Guaranteed by design |
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10 |
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MHz |
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SR |
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Slew-Rate |
COMP = 10pF |
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5 |
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V/µs |
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Guaranteed by design |
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Gate drivers |
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RHGATE_ON |
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High Side Source Resistance |
VBOOT - VPHASE = 5V |
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1.7 |
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Ω |
RHGATE_OFF |
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High Side Sink Resistance |
VBOOT - VPHASE = 5V |
|
1.12 |
|
Ω |
RLGATE_ON |
|
Low Side Source Resistance |
VCCDR = 5V |
|
1.15 |
|
Ω |
RLGATE_OFF |
|
Low Side Sink Resistance |
VCCDR = 5V |
|
0.6 |
|
Ω |
Protections |
|
|
|
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|
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|
|
|
IOCH |
|
OCH Current Source |
VOCH = 1.7V |
90 |
100 |
110 |
µΑ |
IOCL |
|
OCL Current Source |
|
90 |
100 |
110 |
µΑ |
|
|
|
VFB Rising |
|
120 |
|
% |
|
|
Over Voltage Trip |
VEAREF = 0.6V |
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||
OVP |
|
|
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|
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||
|
(VFB / VEAREF) |
VFB Falling |
|
117 |
|
% |
|
|
|
|
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||||
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|
|
VEAREF = 0.6V |
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9/32
L6725 - L6725A |
Device description |
5 Device description
The controller provides complete control logic and protection for flexible and cost-effective DCDC converters. It is designed to drive N-Channel MOSFETs in a synchronous rectified buck topology. The output voltage of the converter can be precisely regulated down to 600mV with a maximum tolerance of ±0.8%, when the internal reference is used. The device allows also using an external reference (0V to 2.5V) for the regulation. The device provides voltage-mode control. The switching frequency can be set at two different values: 250KHz or 500KHz. The error amplifier features a 10MHz gain-bandwidth-product and 5V/µs slew-rate that permits to realize high converter bandwidth for fast transient response. The PWM duty cycle can range from 0% to 100%. The device protects against over current conditions providing a constant- current-protection during the soft-start phase and entering in HICCUP mode in all the other
conditions. The device monitors the current by using the RDS(ON) of both the high-side and lowside MOSFET(s), eliminating the need for a current sensing resistor and guaranteeing an
effective over-current-protection in all the application conditions. Other features are over- voltage-protection and thermal shutdown. The device is available in SO16N package.
5.1Oscillator
The switching frequency can be fixed to two values: 250KHz or 500KHz by setting the proper voltage at the EAREF pin (see Table 4. Pins function and section 4.3 Internal and external reference).
5.2Internal LDO
An internal LDO supplies the internal circuitry of the device. The input of this stage is the VCC
pin and the output (5V) is the VCCDR pin. The LDO can be by-passed, providing directly a 5V voltage to VCCDR. In this case VCC and VCCDR pins must be shorted together as shown in Figure 3. VCCDR pin must be filtered with a 1uF capacitor to sustain the internal LDO during the recharge of the bootstrap capacitor.
10/32
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