ST L6725, L6725A User Manual

with bootstrap anti-discharging system

Features

■ Input voltage range from 1.8V to 18V

■ Supply voltage range from 4.5V to 18V

■ Adjustable output voltage down to 0.6V with

±0.8% accuracy over line voltage and temperature (0°C~125°C)

■ Fixed frequency voltage mode control

■ 0% to 100% duty cycle

■ External input voltage reference

■ Soft-start and inhibit

■ Bootstrap anti-discharging system

■ High current embedded drivers

■ Predictive anti-cross conduction control

■ Programmable high-side and low-side R

sense over-current-protection

■ Sink current capability

■ Selectable switching frequency 250KHz/

500KHz

■ Power good and synch available with L6725A

■ Pre-bias start up capability

■ Over voltage protection

■ Thermal shut-down

■ Package: SO16N

DS(on)

Voltage mode PWM controller

SO16N (Narrow)

Applications

■ Low voltage distributed DC-DC

■ Graphic cards

L6725

L6725A

Table 1. Device summary

Order codes Package Packing

L6725 SO16N Tube

L6725TR SO16N Tape & Reel

L6725A SO16N Tube

L6725ATR SO16N Tape & Reel

June 2007 Rev 5 1/32

www.st.com

Contents L6725 - L6725A

Contents

1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Pin connections and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.2 Internal LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.3 Bypassing the LDO to avoid the voltage drop with low Vcc . . . . . . . . . . . . . 11

5.4 Internal and external references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.5 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.6 Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.7 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.8 Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.9 Hiccup mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.10 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2/32

L6725 - L6725A Contents

5.11 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.12 Bootstrap anti-discharging system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.12.1 Fan's power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6 Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.1 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.2 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.3 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7 L6725 demoboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.1 20A board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.2 5A board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3/32

Summary description L6725 - L6725A

1 Summary description

The device is a flexible high performance PWM buck controller dedicated for low voltage distributed DC-DC. The input voltage can range from 1.8V to 18V, while the supply voltage can range from 4.5V to 18V. The output voltage is adjustable down to 0.6V.

High peak current gate drivers provide for fast switching to the external power section, and the output current can be in excess of 20A. The device is capable to manage minimum on-times (T

) shorter than 100ns making possible conversions with very low duty cycle and very high

switching frequency. In order to guarantee a real overcurrent protection, also with very narrow T

, the current sense is realized both on the high-side and low-side MOSFETs. When

necessary, two different current limit protections can be externally set through an external resistor. The device can sink current after the soft-start phase while, during the soft-start, the sink mode capability is disabled in order to allow a proper start-up also in pre-biased output voltage conditions. Other features are over-voltage-protection and thermal shutdown.

1.1 Functional description

Figure 1. Block diagram

Vcc = 14V - 18V

Vin = 14V - 18V

Vin=1.8V-14V

OCH

0.6V

LDO

OSC

L6725

VCCDR

BOOT

HGATE

PHASE

OUT

LGATE

PWM

+-+

PWM

E/A

COMP

PGND

GND

EAREF

PGOOD

SYNCH

OCL

Monitor

Protection and Ref

4/32

L6725 - L6725A Electrical data

2 Electrical data

2.1 Maximum rating

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

VCC to GND and PGND, OCH

BOOT - VPHASE

HGATE - VPHASE

BOOT

PHASE

Boot voltage 0 to 6 \

BOOT -0.3 to 26 V

PHASE -1 to 20

PHASE Spike, transient < 50ns (F

= 500KHz)

-0.3 to 20 V

0 to V

BOOT

- V

PHASE

-3

+24

SS, FB, EAREF, OCL, LGATE, COMP, V

OCH Pin Maximum withstanding voltage range

CCDR

-0.3 to 6 V

±1500

Test Condition: CDF-AEC-Q100-002 "Human Body Model"

OTHER PINS ±2000

Acceptance Criteria: "Normal Performance"

2.2 Thermal data

Table 3. Thermal data

Symbol Description Value Unit

(1)

thJA

STG

1. Package mounted on demoboard

Max. thermal resistance junction to ambient 50 °C/W

Storage temperature range -40 to 150 °C

Junction operating temperature range -40 to 125 °C

Ambient operating temperature range -40 to +85 °C

5/32

Pin connections and functions L6725 - L6725A

3 Pin connections and functions

Figure 2. Pins connection (top view)

COMP SS/INH EAREF

OCL

OCH

PHASE HGATE BOOT

SO16N

Table 4. Pin functions

Pin n° Name Function

1COMP

2 SS/INH

3 EAREF

4OCL

This pin is connected to the error amplifier output and is used to compensate the voltage control feedback loop.

The soft-start time is programmed connecting an external capacitor from this pin to GND. The internal current generator forces a current of 10µA through the capacitor. When the voltage at this pin is lower than 0.5V the device is disabled.

By setting the voltage at this pin is possible to select the internal/external reference and the switching frequency:

EAREF

0-80% of V

= 80% - 95% of V = 95% - 100% of V

-> External Reference/FSW = 250KHz

CCDR

-> V

->V

= 0.6V/F

REF

An internal clamp limits the maximum V analog value present at this pin at the start-up when V

A resistor connected from this pin to ground sets the valley- current-limit. The valley current is sensed through the low-side MOSFET(s). The internal current generator sources a current of 100µA (I

). The over-current threshold is given by the following equation:

OCL

) from this pin to ground through the external resistor

OCL

VALLEY

SGND

SYNCH/NC

PGOOD/NC

VCC

VCCD

LGATE

PGND

= 500KHz

= 0.6V/FSW = 250KHz

at 2.5V (typ.). The device captures the

EAREF

meets the UVLO threshold.

⋅

OCL

⋅

DSonLS

6/32

L6725 - L6725A Pin connections and functions

Table 4. Pin functions

Pin n° Name Function

A resistor connected from this pin and the high-side MOSFET(s) drain sets the peakcurrent-limit. The peak current is sensed through the high-side MOSFET(s). The internal 100µA current generator (I

external resistor (R

5OCH

equation:

). The over-current threshold is given by the following

OCH

This pin is connected to the source of the high-side MOSFET(s) and provides the

6 PHASE

return path for the high-side driver. This pin monitors the drop across both the upper and lower MOSFET(s) for the current limit together with OCH and OCL.

7 HGATE This pin is connected to the high-side MOSFET(s) gate.

8BOOT

9PGND

Through this pin is supplied the high-side driver. Connect a capacitor from this pin to the PHASE pin and a diode from V

This pin has to be connected closely to the low-side MOSFET(s) source in order to reduce the noise injection into the device.

10 LGATE This pin is connected to the low-side MOSFET(s) gate.

CCDR

PGOOD

(L6725A)

N.C.

(L6725)

5V internally regulated voltage. It is used to supply the internal drivers. Filter it to ground with a 1uF ceramic cap.

Supply voltage pin. The operative supply voltage range is from 4.5V to 14V.

In L6725 this pin is N.C. With L6725A this pin is an open collector output and it is pulled low if the output voltage is not

within the specified thresholds (90%-110%). If not used it may be left floating. Pull-up this pin to V

with a 10K resistor to obtain a logical signal.

CCDR

In L6725 this pin is N.C. With L6725A it is a Master-Slave pin. Two or more devices can be synchronized by simply

connecting the SYNCH pins together. The device operating with the highest FSW will be the Master. The Slave devices will operate with 180° phase shift from the Master. The best way to synchronize devices together is to set their FSW at the same value. If

SYNCH

(L6725A)

N.C.

(L6725)

it is not used the SYNCH pin can be left floating.

) sinks a current from the drain through the

OCH

⋅

PEAK

OCH

to this pin (cathode versus BOOT).

CCDR

DSonHS

OCH

15 SGND All the internal references are referred to this pin.

This pin is connected to the error amplifier inverting input. Connect it to V

16 FB

the compensation network. This pin is also used to sense the output voltage in order to manage the over voltage protection.

OUT

through

7/32

Electrical characteristics L6725 - L6725A

4 Electrical characteristics

= 12V, TA = 25°C unless otherwise specified.

Table 5. Electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit

supply current

quiescent current

Power-ON

Tur n -O N VCC threshold V

VCC Stand by current

Tur n -O F F V

Tur n -O N V

CCDR

IN OK

Regulation

Tur n -O F F V

CCDR

Soft Start and Inhibit

Soft Start Current

Oscillator

∆V

OSC

Accuracy

Ramp Amplitude 2.1 V

OCH

voltage

threshold V

threshold

SS to GND 7 9

HG = open, LG = open, PH=open 8.5 10

OCH

= 1.7V

4.0 4.2 4.4 V

3.6 3.8 4.0 V

1.1 1.25 1.47 V

0.9 1.05 1.27 V

=5.5V to 18V

= 1mA to 100mA

4.555.5V

SS = 2V 7 10 13

SS = 0 to 0.5V 20 30 45

237 250 263 KHz

450 500 550 KHz

µA

Output Voltage

Output Voltage 0.597 0.6 0.603 V

8/32

L6725 - L6725A Electrical characteristics

Table 5. Electrical characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

Error Amplifier

EAREF

Ext Ref

Clamp

OFFSET

EAREF Input Resistance Vs. GND 70 100 150 kΩ

I.I. bias current

FΒ

0.290 0.5 µA

= 0V

2.3 V

Error amplifier offset Vref = 0.6V -5 +5 mV

Open Loop Voltage Gain Guaranteed by design 100 dB

GBWP Gain-Bandwidth Product Guaranteed by design 10 MHz

SR Slew-Rate

COMP = 10pF Guaranteed by design

5V/µs

Gate drivers

HGATE_ON

HGATE_OFF

LGATE_ON

LGATE_OFF

High Side Source Resistance

High Side Sink Resistance

Low Side Source Resistance

Low Side Sink Resistance

BOOT

CCDR

- V

= 5V

PHASE

= 5V

1.7 Ω

1.12 Ω

1.15 Ω

0.6 Ω

Protections

OCH

OCL

OVP

OCH Current Source

OCL Current Source 90 100 110 µΑ

Over Voltage Trip (V

/ V

EAREF

)

OCH

EAREF

= 1.7V

Rising

= 0.6V

Falling

= 0.6V

90 100 110 µΑ

120 %

117 %

9/32

L6725 - L6725A Device description

5 Device description

The controller provides complete control logic and protection for flexible and cost-effective DCDC converters. It is designed to drive N-Channel MOSFETs in a synchronous rectified buck topology. The output voltage of the converter can be precisely regulated down to 600mV with a maximum tolerance of ±0.8%, when the internal reference is used. The device allows also using an external reference (0V to 2.5V) for the regulation. The device provides voltage-mode control. The switching frequency can be set at two different values: 250KHz or 500KHz. The error amplifier features a 10MHz gain-bandwidth-product and 5V/µs slew-rate that permits to realize high converter bandwidth for fast transient response. The PWM duty cycle can range from 0% to 100%. The device protects against over current conditions providing a constantcurrent-protection during the soft-start phase and entering in HICCUP mode in all the other conditions. The device monitors the current by using the R side MOSFET(s), eliminating the need for a current sensing resistor and guaranteeing an effective over-current-protection in all the application conditions. Other features are overvoltage-protection and thermal shutdown. The device is available in SO16N package.

5.1 Oscillator

DS(ON)

of both the high-side and low-

The switching frequency can be fixed to two values: 250KHz or 500KHz by setting the proper voltage at the EAREF pin (see Table 4. Pins function and section 4.3 Internal and external reference).

5.2 Internal LDO

An internal LDO supplies the internal circuitry of the device. The input of this stage is the VCC pin and the output (5V) is the V voltage to V

Figure 3. V

recharge of the bootstrap capacitor.

. In this case VCC and V

CCDR

pin must be filtered with a 1uF capacitor to sustain the internal LDO during the

CCDR

pin. The LDO can be by-passed, providing directly a 5V

CCDR

pins must be shorted together as shown in

CCDR

10/32

+ 22 hidden pages