ST L6718 User Manual

Digitally controlled dual PWM with embedded drivers for VR12

VFQFPN56 - 7x7mm

Features

■ VR12 compliant with 25 MHz SVID bus rev. 1.5

■ Second generation LTB Technology

Very compact dual controller:

■

– Up to 4 phases for core section with 2

internal drivers

– 1 phase for GFX section with internal driver

■ Input voltage up to 12 V

■ SMBus interface for power management

■ SWAP, Jmode, multi-rail only support

■ Programmable offset voltage

■ Single NTC design for TM, LL and IMON

thermal compensation (for each section)

■ VFDE for efficiency optimization

■ DPM - dynamic phase management

■ Dual differential remote sense

■ 0.5% output voltage accuracy

■ Full-differential current sense across DCR

■ AVP - adaptive voltage positioning

■ Programmable switching frequency

■ Dual current monitor

■ Pre-biased output management

■ High-current embedded drivers optimized for

7 V operation

■ OC, OV, UV and FB disconnection protection

■ Dual VR_READY

■ VFQFPN56 7x7 mm package with exposed

pad

Applications

■ High-current VRM / VRD for desktop / server /

new generation workstation CPUs

■ DDR3 DDR4 memory supply for VR12

™

L6718

processors

Datasheet − preliminary data

Description

The L6718 is a very compact, digitally controlled
and cost effective dual controller designed to
power Intel
pinstrapping is used to program the main
parameters.

The device features from 2 to 4-phase
programmable operation for the core section
providing 2 embedded drivers. A single-phase
with embedded driver and with independent
control loop is used for GFX.

The L6718 supports power state transitions
featuring VFDE and a programmable DPM,
maintaining the best efficiency over all loading
conditions without compromising transient
response.

Second generation LTB Technology
minimal cost output filter providing fast load
transient response. The controller assures fast
and independent protection against load
overcurrent, under/overvoltage and feedback
disconnections.

The device is available in VFQFPN56, 7x7 mm
compact package with exposed pad.

Table 1. Device summary

Order code Package Packaging

L6718

L6718TR

®

VR12 processors. Dedicated

™

allows a

VFQFPN56 7x7mm Tray

VFQFPN56 7x7mm

Tape and

reel

July 2012 Doc ID 023399 Rev 1 1/71

This is preliminar y information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.

www.st.com

71

Contents L6718

Contents

1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 7

1.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2 Pin description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 11

2.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4 VID tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5 Device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6 Device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1 CPU mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.2 DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.3 SWAP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.3.1 MRO - multi-phase rail only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.4 Jmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.5 Phase number configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.6 Pinstrapping configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.6.1 CONFIG0 in CPU mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.6.2 CONFIG0 in DDR mode (STCOMP=GND) . . . . . . . . . . . . . . . . . . . . . . 34

6.6.3 CONFIG1 in CPU mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.6.4 CONFIG1 in DDR mode (STCOMP=GND) . . . . . . . . . . . . . . . . . . . . . . 37

6.6.5 CONFIG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.6.6 CONFIG3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7 L6718 power manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.1 SMBus power manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2/71 Doc ID 023399 Rev 1

L6718 Contents

7.1.1 SMBus sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.2 SMBus tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.3 DPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.4 VFDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.5 Power state indicator (PSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8 Output voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.1 Multi-phase section - current reading and current sharing loop . . . . . . . . 50

8.2 Multi-phase section - defining load-line . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8.3 Single-phase section - current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.4 Single-phase section - defining load-line . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.5 Dynamic VID transition support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8.6 DVID optimization: REF/SREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9 Output voltage monitoring and protection . . . . . . . . . . . . . . . . . . . . . . 55

9.1 Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

9.2 Overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

9.2.1 Multi-phase section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

9.2.2 Overcurrent and power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

9.2.3 Single-phase section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

10 Single NTC thermal monitor and compensation . . . . . . . . . . . . . . . . . 59

10.1 Thermal monitor and VR_HOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.2 Thermal compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

10.3 TM and TCOMP design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

11 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

12 System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

12.1 Compensation network guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

12.2 LTB technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

13 Power dissipation and application details . . . . . . . . . . . . . . . . . . . . . . 65

13.1 High-current embedded drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

13.2 Boot diode and capacitor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Doc ID 023399 Rev 1 3/71

Contents L6718

13.3 Device power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

14 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

14.1 Power components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

14.2 Small signal components and connections . . . . . . . . . . . . . . . . . . . . . . . 67

15 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4/71 Doc ID 023399 Rev 1

L6718 List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 6. VID table, both sections, commanded through serial bus . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 7. Phase number programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 8. CONFIG0/PSI0 pinstrapping in CPU MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 9. CONFIG0/PSI0 pinstrapping in DDR MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 10. CONFIG1/PSI1 pinstrapping in CPU MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 11. CONFIG1/PSI1 pinstrapping in DDR MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 12. CONFIG2/SDA pinstrapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 13. CONFIG3/SCL pinstrapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 14. SMBus addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 15. SMBus interface commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 16. SMBus VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 17. Power status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 18. L6718 protection at a glance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 19. Multi-phase section OC scaling and power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 20. VFQFPN56 7x7 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 21. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Doc ID 023399 Rev 1 5/71

List of figures L6718

List of figures

Figure 1. Typical 4-phase application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. Typical 3-phase application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. Typical 2-phase application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6. Device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 7. SWAP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 8. SMBus communication format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 9. Output current vs. switching frequency in PSK mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 10. Voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 11. Current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 12. DVID optimization circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 13. Thermal monitor connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 14. ROSC [KOhm] vs. switching frequency [kHz] per phase. . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 15. Equivalent control loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 16. Control loop Bode diagram and fine tuning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 17. VFQFPN56 7x7 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6/71 Doc ID 023399 Rev 1

L6718 Typical application circuit and block diagram

LS1

L1

CHF

Rtcm

Ctcm

+12V

Rg

BOOT

UGATE

PHASE

LGATE

VCC

L6743

EN

PWM4

CS3P

SC3N

SCSP

SCSN

SBOOT

VR12 μP LOAD

CORE

VR12 SVID

C

SOUTCSMLCC

PWM

GND

CDEC

SVCLK

ALERT#

SVDATA

CF

RF

CI

RI

RFB

CP

RGND

VSEN

FB

COMP

IMON

CSF

RSF

CSI

RSI

RSFB

CSP

SRGND

SVSEN

SFB

SCOMP

SIMON

CLTB RLTB

LTB

SPHASE

+7V

VCC5

+5V

GND

(PAD)

VR_HOT

EN

REF

SREF/JEN

+5V

ST L6718

ST L6718 (4+1) Reference Schematic

C

OUT

C

MLCC

HS1

LSs

Ls

CHF

Rtcm_s

Ctcm_s

+12V

Rg_s

HSs

LS2

L2

CHF

Rtcm

Ctcm

+12V

Rg

HS2

LS3

L3

CHF

Rtcm

Ctcm

+12V

Rg

HS3

LS4

L4

CHF

Rtcm

Ctcm

+12V

RG

HS4

+12V

BOOT

UGATE

PHASE

LGATE

VCC

L6743

EN

PWM

GND

CDEC

+12V

PWM3

SLGATE

SHGATE

CS1P
CS1N

BOOT1

PHASE1

LGATE1

HGATE1

CS2P
CS2N

BOOT2

PHASE2

LGATE2

HGATE2

CS4P

CS4N

OSC/FLT

SOSC/SFLT

ENABLE

SVREADY
VREADY

VRHOT

TM

CONF1/PSI1
TCOMP
STCOMP/DDR

CONF0/PSI0

SCL/CONFIG3

SDA/CONFIG2

VCC12

GPU

RSIMON

+5V

CSREF RSREF

CREF

RREF

RIMON

STM

RGate

RGate

RGate

RGate

RGate

RGate

RGate

RGate

RGate

RGate

Rboot

Rboot

Rboot

Rboot

Rboot

Cboot

Cboot

Cboot

Cboot

Cboot

AM12875v1

1 Typical application circuit and block diagram

1.1 Application circuit

Figure 1. Typical 4-phase application circuit

Doc ID 023399 Rev 1 7/71

Typical application circuit and block diagram L6718

LS1

L1

CHF

Rtcm

Ctcm

+12V

Rg

BOOT

UGATE

PHASE

LGATE

VCC

L6743B

EN

PWM4

CS3P

SC3N

SCSP

SCSN

SBOOT

VR12 μP LOAD

CORE

VR12 SVID

C

SOUTCSMLCC

PWM

GND

CDEC

SVCLK

ALERT#

SVDATA

CF

RF

CI

RI

RFB

CP

RGND

VSEN

FB

COMP

IMON

CSF

RSF

CSI

RSI

RSFB

CSP

SRGND

SVSEN

SFB

SCOMP

SIMON

CLTB RLTB

LTB

SPHASE

+7V

VCC5

+5V

GND

(PAD)

EN

REF

SREF/JEN

+5V

ST L6718

ST L6718 (3+1) Reference Schematic

C

OUT

C

MLCC

HS1

LSs

Ls

CHF

+12V

Rg_s

HSs

LS2

L2

CHF

+12V

HS2

LS2

L3

CHF

+12V

HS3

+12V

PWM3

SLGATE

SHGATE

CS1P

CS1N

BOOT1

PHASE1

LGATE1

HGATE1

CS2P

CS2N

BOOT2

PHASE2

LGATE2

HGATE2

CS4N

CS4P

OSC/OVP

SOSC/SOVP

ENABLE

SVREADY

VREADY

VRHOT

TM

CONF1/PSI1

TCOMP

STCOMP/DDR

CONF0/PSI0

SCL/CONFIG3

SDA/CONFIG2

VCC12

GPU

RSIMON

+5V

CSREF RSREF

CREF RREF

RIMON

STM

Rtcm_s

Ctcm_s

RGate

RGate

Rboot

Cboot

RGate

RGate

Rboot

Cboot

RGate

RGate

Rboot

Cboot

RGate

RGate

Rboot

Cboot

Rtcm

Ctcm

Rg

Rtcm

Ctcm

Rg

AM12876v1

Figure 2. Typical 3-phase application circuit

8/71 Doc ID 023399 Rev 1

L6718 Typical application circuit and block diagram

LS2

L1

CHF

+12V

PWM4

CS3N
SC3P

SCSP
SCSN

SBOOT

VR12 μP LOAD

CORE

VR12 SVID

C

SOUTCSMLCC

SVCLK

ALERT#

SVDATA

CF

RF

CI

RI

RFB

CP

RGND

VSEN

FB

COMP

IMON

CSF

RSF

CSI

RSI

RSFB

CSP

SRGND

SVSEN

SFB

SCOMP

SIMON

CLTB RLTB

LTB

SPHASE

+7V

VCC5

+5V

GND

(PAD)

EN

REF

SREF/JEN

+5V

ST L6718

ST L6718 (2+1) Reference Schematic

C

OUT

C

MLCC

HS1

LSs

Ls

CHF

+12V

HSs

LS2

L2

CHF

+12V

HS2

PWM3

SLGATE

SHGATE

CS1P
CS1N

BOOT1

PHASE1

LGATE1

HGATE1

CS2P
CS2N

BOOT2

PHASE2

LGATE2

HGATE2

CS4N

CS4P

OSC/FLT

SOSC/SFLT

ENABLE

SVREADY
VREADY

VRHOT

TM

CONF1/PSI1
TCOMP
STCOMP/DDR

CONF0/PSI0

SCL/CONFIG3

SDA/CONFIG2

VCC12

GPU

RSIMON

+5V

CSREF RSREF

CREF RREF

RIMON

STM

Rtcm_s

Ctcm_s

Rg_s

Rtcm

Ctcm

Rg

Rtcm

Ctcm

Rg

RGate

RGate

Rboot

Cboot

RGate

RGate

Rboot

Cboot

RGate

RGate

Rboot

Cboot

Rg

Rg

AM12877v1

Figure 3. Typical 2-phase application circuit

Doc ID 023399 Rev 1 9/71

Typical application circuit and block diagram L6718

PWM4

PWM3

PWM2

PWM1

LTB Technology

Modulator

& Frequency Limiter

Ramp & Clock

Generator
with VFDE

S

S

S

S

Differential Current Sense

Current Balance

& Peak Curr Limit

Thermal

Compensation

and Gain adjust

CS1P
CS1N

CS2P
CS2N

CS3P
CS3N

CS4P
CS4N

LTB

ERROR

AMPLIFIER

TM

TCOMP

VRHOT

I

MON

I

DROOP

OCP

VR12 Bus Manager

FB

REF

COMP

SVD ATA

ALERT#

SVCLK

IMON

Dual DAC & Ref

Generator

VR12 Registers

CONFIG1/PSI1

CONFIG0/PSI0

RGND

VSEN

OV

+OVP_Trk

MultiPhase

Fault Manager

OC

SREF

Thermal

Sensing

and Monitor

TempZone

TempZone

Imon

SImon

Chan #

LTB Technology

Modulator

& Frequency Limiter

Ramp & Clock

Generator
withVFDE

SOSC/SFLT

SHGATE

SPWM

ERROR

AMPLIFIER

I

SMON

I

SDROOP

OCP

SFB

SREF/JEN

SCOMP

SIMON

SRGND

SVSEN SOV

+OVP_Trk

SOC

SREF

SinglePhase

Fault Manager

VREADY

FLT

FLT

To SinglePhase

FLT Manager

To M ultiPhase FLT Manage

SVREADY

SFLT

SFLT

DDR

Differential

Current Sense

SCSP
SCSN

Start-up Logic

VCC12

VCC5

ENABLE

S_EN

EN

S_EN

GND (PAD)

OSC /FLT

VSEN

I

REF

I

REF

I

SREF

I

SREF

STM

Thermal

Compensation

and Gain adjust

STCOMP/DDR

VCC12

SBOOT

SPHASE

SLGATE

SWAP

Anti Cross

Conduction

Anti Cross

Conduction

Anti Cross

Conduction

SDA/CONF2

SCL/CONF3

SMBus

Manager

SWAP

DDRTh

PWM4/PH#N

PMW3/SPWM

LGATE2

PHASE2

HGATE2

BOOT2

LGATE1

PHASE1

HGATE1

BOOT1

PH#N

L6718

JEN

AM12878v1

1.2 Block diagram

Figure 4. Block diagram

10/71 Doc ID 023399 Rev 1

L6718 Pin description and connection diagrams

12

11

10

9

8

7

6

5

4

3

2

1

31

32

33

34

35

36

37

38

39

40

41

42

56 55 54 53 52 51 50 49 48 47 46 45

15 16 17 18 19 20 21 22 23 24 25 26

SOSC/SFLT

SCSP

SCSN

STM

CONF0/PSI0

SHGATE

SPHASE

SLGATE

PWM4/PH#

PMW3//SPWM

PHASE1

SBOOT

LT B

VSEN

RGND

ALERT#

SV DATA

SVCLK

VRHOT

TM

CS3N

CS3P

CS1P

CS1N

CS2N

CS2P

CS4P

CS4N

VREADY

SVREADY

LGATE1

LGAE2

PHASE2

HGATE2

BOOT2

VCC12

IMON

REF

SRGND

SVSEN

SFB

SCOMP

SIMON

SREF

ENABLE

STCOMP/DDR

TCOMP

CONF1/PSI1

L6718

27 28

29

30

44 43

14

13

COMP

FB

CONF2/SDA

CONF3/SCL

VCC5

OSC/FLT

BOOT1

HGATE1

AM12879v1

2 Pin description and connection diagrams

Figure 5. Pin connection (top view)

Doc ID 023399 Rev 1 11/71

Pin description and connection diagrams L6718

2.1 Pin description

Table 2. Pin description

Pin# Name Function

Channel 1 current sense negative input.
Connect through an RG resistor to the output-side of channel 1 inductor.

1CS1N

2CS1P

3CS3P

4CS3N

5TM

Filter the output-side of R

with 100 nF (typ.) to GND.

G

This pin is compared with VSEN for the feedback disconnection.
See Section 14 for proper layout of this connection.

Channel 1 current sense positive input.
Connect through an R-C filter to the phase-side of channel 1 inductor.
See Section 14 for proper layout of this connection.

Channel 3 current sense positive input.
Connect through an R-C filter to the phase-side of channel 3 inductor.
Short to V

when not using channel 3.

OUT

See Section 14 for proper layout of this connection.

Channel 3 current sense negative input.
Connect through an R
Filter the output-side of R
Connect to V
See Section 14 for proper layout of this connection.

MULTI-RAIL SECTION

OUT

resistor to the output-side of channel 3 inductor.

G

with 100 nF (typ.) to GND.

G

through an RG resistor when not using channel 3.

Thermal monitor sensor.
Connect with proper network embedding NTC to the multi-phase rail

power section. The IC senses the power section temperature and uses the
information to define the VRHOT signal and temperature zone register.

By programming proper TCOMP gain, the IC also implements load-line
thermal compensation for the multi-phase rail section. See Section 10 for
details.

Voltage regulator HOT.

6 VRHOT

Open drain output, set free by controller when the temperature sensed
through the TM pin exceeds TMAX (active low).

See Section 10.1 for details.

7 SVCLK

Serial clock

8 SVDATA Serial data

9ALERT# Alert

SVID BUS

12/71 Doc ID 023399 Rev 1

L6718 Pin description and connection diagrams

Table 2. Pin description (continued)

Pin# Name Function

Remote ground sense pin.

10 RGND

11 VSEN

12 LTB

13 FB

14 COMP

Connect to the negative side of the load to perform remote sense.
See Section 14 for proper layout of this connection.

Output voltage monitor pin.
Manages OVP/UVP protection and feedback disconnection. Connect to

the positive side of the load to perform remote sense. A fixed 50 uA
current is sourced from this pin.

See Section 14 for proper layout of this connection.

Load transient boost technology input pin.
Internally fixed at 1.67 V, connecting R

LT B

- C

LT B

vs. V

allows the load

OUT

transient boost technology to be enabled, as soon as the device detects a
transient load it turns on all the PHASEs at the same time. Short to SGND
to disable the function.

See Section 12.2 for details.

Error amplifier inverting input.
Connect with an R

to VSEN and (RF - CF)// CP to COMP.

FB

A current proportional to the load current is sourced from this pin in order
to implement the droop effect. See Section 8.2 for details.

MULTI-RAIL SECTION

Error amplifier output.
Connect with (RF - CF)// CP to FB.
The device cannot be disabled by pulling down this pin.

15 IMON

16 REF

Current monitor output.
A current proportional to the multi-phase rail output current is sourced

from this pin. Connect through a resistor R

to GND to show a voltage

IMON

proportional to the current load. Based on pin voltage level, DPM and
overcurrent protection can be triggered. Filtering through C
allows control of the delay. See Section 9.2 for R

IMON

definition.

IMON

to GND

The reference used for the regulation of the multi-phase rail section is
available on this pin with -100 mV + offset. Connect through an R

to RGND to optimize DVID transitions. See Section 8.6 for details.

C

REF

REF

-

Doc ID 023399 Rev 1 13/71

Pin description and connection diagrams L6718

Table 2. Pin description (continued)

Pin# Name Function

Single-phase rail remote ground sense.

17 SRGND

18 SVSEN

19 SFB

20 SCOMP

21 SIMON

22 SREF/JEN

Connect to the negative side of the single-phase rail load to perform
remote sense.

See Section 14 for proper layout of this connection.

Single-rail output voltage monitor.
Manages OVP/UVP protection and feedback disconnection. Connect to

the positive side of the load to perform remote sense. It is also the sense
for the single-phase rail LTB.

Connect to the positive side of the single-phase rail load to perform
remote sense.

See Section 14 for proper layout of this connection.

Error amplifier inverting input.
Connect with a resistor R

to SVSEN and with (RSF - CSF)// CSP to

SFB

SCOMP. A current proportional to the load current is supplied from this pin
in order to implement the droop effect. See Section 8.4 for details.

Error amplifier output.
Connect with an (R

- CSF)// CSP to SFB. The device cannot be disabled

SF

by pulling this pin low.

SINGLE-RAIL SECTION

Current monitor output.
A current proportional to the output current is sourced from this pin.

Connect through a resistor R
overcurrent protection can be triggered. Filtering through C

to local GND. Based on pin voltage,

SIMON

SIMON

allows control of the delay for OC intervention. See Section 9.2 for R
definition.

The reference used for the regulation of the single-rail section is available
on this pin with -100 mV + offset. Connect through an R

SREF-CSREF

SRGND to optimize DVID transitions. See Section 8.6 for details.
If Jmode is selected by Config1 pinstrapping, this pin is used as a logic

input for the single-phase rail enable. Pulling this pin up above 0.8 V, the
single-phase rail turns on.

to GND

SIMON

to

Enable pin.
External pull-up is needed on this pin.
Forced low to disable the device with all MOSFETs OFF: all protection is

23 ENABLE

disabled except for preliminary overvoltage.
Over 0.65 V the device turns up.
Cycle this pin to recover latch from protection, filter with 1 nF (typ.) to

GND.

Thermal monitor sensor gain and DDR selected.

24

STCOMP/

DDR

Connect proper resistor divider between VCC5 and GND to define the
gain to apply to the signal sensed by ST to implement thermal
compensation for the single-phase rail. See Section 10 for details. Short to
GND to disable thermal compensation and set the device to DDR mode.

SINGLE-RAIL SECTION

14/71 Doc ID 023399 Rev 1

L6718 Pin description and connection diagrams

Table 2. Pin description (continued)

Pin# Name Function

Thermal monitor sensor gain.
Connect proper resistor divider between VCC5 and GND to define the

25 TCOMP

CONFIG1/

26

27

28

29 VCC5

30 OSC/FLT

PSI1

SDA /

CONFIG2

SCL /

CONFIG3

gain to apply to the signal sensed by TM to implement thermal
compensation for the multi-phase rail.

Short to GND to disable the single NTC thermal compensation for multi­phase section. See Section 10 for details.

SINGLE-RAIL SECTION

Connect a resistor divider to GND and VCC5 to define power
management configuration. See Section 6.6 for details.

At the end of the soft-start, this pin is internally pulled up or pulled down to
indicate the power status. See Table 17 for details.

PINSTRAPPING

If SMBus power management is enabled through Config0 pinstrapping,
connect to data signal of SMBus communicator.

If SMBus power management is disabled through Config0 pinstrapping,
connect a resistor divider to GND and VCC5 to define power management
characteristics. See Section 6.6.5 for details.

If SMBus power management is enabled through Config0 pinstrapping,
connect to clock signal of SMBus communicator.

If SMBus power management is disabled through Config0 pinstrapping,
connect a resistor divider to GND and VCC5 to define power management

SMBus / PINSTRAPPING

characteristics. See Section 6.6.5 for details.

Main IC power supply.
Operative voltage is connected to 5 V filtered with 1 uF MLCC to GND.

Oscillator pin for multi-phase rail.
Allows the programming of the switching frequency F

section. The equivalent switching frequency at the load side results in
being multiplied by the number of phases active.

The pin is internally set to 1.8 V, frequency is programmed according to a
resistor connected to GND or VCC with a gain of 10 kHz/µA. Free running
is set to 200 kHz.

The pin is forced high (3.3 V) if a fault is detected on a multi-rail section. To
recover from this condition, it is necessary to cycle VCC or enable. See

MULTI-RAIL SECTION

Section 11 for details.

for multi-phase

SW

31

SOSC /

SFLT

Oscillator pin for single-phase.
Allows the programming of the switching frequency FSW for the single-

phase section.
The pin is internally set to 1.8 V, frequency is programmed according to

the resistor connected to GND or VCC with a gain of 10 kHz/µA. Free
running is set to 200 kHz.

The pin is forced high (3.3 V) if a fault is detected on a single-phase rail
section. To recover from this condition, it is necessary to cycle VCC or

SINGLE-RAIL SECTION

enable. See Section 11 for details.

Doc ID 023399 Rev 1 15/71

Pin description and connection diagrams L6718

Table 2. Pin description (continued)

Pin# Name Function

Single-phase rail current sense positive input.

32 SCSP

33 SCSN

34 STM

CONFIG0

35

/PSI0

36 SBOOT

Connect through an R-C filter to the phase-side of single-phase rail
inductor.

See Section 14 for proper layout of this connection.

Single-phase rail current sense negative input.
Connect through an R

resistor to the output-side of single-phase rail

G

inductor.
Filter the output-side of R

with 100 nF (typ.) to GND.

G

See Section 14 for proper layout of this connection.

Thermal monitor sensor.
Connect with proper network embedding NTC to the single-phase power

SINGLE-RAIL SECTION

section. The IC senses the hot spot temperature and uses the information
to define the VRHOT signal and temperature zone register.

By programming proper STCOMP gain, the IC also implements load-line
thermal compensation for the single-phase section.

Short to GND if not used. See Section 10 for details.

Connect a resistor divider to GND and VCC5 to define power
management characteristics. See Section 6.6 for details.

At the end of the soft-start, this pin is internally pulled up or pulled down to
indicate the power status. See Table 17 for details.

PINSTRAPPING

Single-phase rail high-side driver supply.
Connect through a capacitor (220 nF typ.) and a resistor (2.2 Ohm) to

SPHASE and provide a Shottky bootstrap diode. A small resistor in series
to the boot diode helps to reduce boot capacitor overcharge.

Single-phase rail high-side driver output.

37 SHGATE

It must be connected to the HS MOSFET gate. A small series resistor
helps to reduce the device-dissipated power and the negative phase
spike.

Single-phase rail high-side driver return path.

38 SPHASE

It must be connected to the HS MOSFET source and provides return path
for the HS driver.

SINGLE-RAIL SECTION

Single-phase rail low-side driver output.

39 SLGATE

It must be connected to the low-side MOSFET gate. A small series
resistor helps to reduce device-dissipated power.

Fourth phase PWM output of the multi-phase rail and phase number
selection pin.

Internally pulled up to 3.3 V, connect to external driver PWM4 when
channel 4 is used. The device is able to manage the HiZ by setting the pin
floating.

40

PWM4

/ PH#

Short to GND or leave floating to 3/2 phase operation, seeTa bl e 7 for
details.

16/71 Doc ID 023399 Rev 1

L6718 Pin description and connection diagrams

Table 2. Pin description (continued)

Pin# Name Function

Third phase PWM output of multi-phase rail or PWM output for single­phase rail.

Connect to external driver PWM input if this channel is used.

PWM3 /

41

SPWM

42 PHASE1

43 HGATE1

44 BOOT1

Internally pull up to 3.3 V, connect to external driver PWM3 when channel
3 is used (seeTa b le 7 for details). The device is able to manage HiZ status
by setting the pin floating.

If SWAP mode is selected by pinstrapping Config0, it must be connected
to single-phase external driver SPWM, see Section 6.3 for details.

Channel 1 HS driver return path.
It must be connected to the HS1 MOSFET source and provides return

path for the HS driver of channel 1.

Channel 1 HS driver output.
It must be connected to the HS1 MOSFET gate. A small series resistor

helps to reduce the device-dissipated power and the negative phase
spike.

Channel 1 HS driver supply.
Connect through a capacitor (220 nF typ.) and a resistor (2.2 Ohm typ.) to

MULTI-RAIL SECTION

PHASE1 and provide a Shottky bootstrap diode. A small resistor in series
to the boot diode helps to reduce boot capacitor overcharge.

45 VCC12

46 BOOT2

47 HGATE2

48 PHASE2

49 LGATE2

50 LGATE1

51 SVREADY

7 V supply.
It is the low-side driver supply. It must be connected to the 7 V bus and

filtered with 2 x 1 µf MLCC caps vs. GND.

Channel 2 high-side driver supply.
Connect through a capacitor (220 nF typ.) and a resistor (2.2 Ohm typ.) to

PHASE2 and provide a Shottky bootstrap diode. A small resistor in series
to the boot diode helps to reduce boot capacitor overcharge.

Channel 2 high-side driver output.
It must be connected to the HS2 MOSFET gate. A small series resistor

helps to reduce the device-dissipated power and the negative phase spike

Channel 2 HS driver return path.
It must be connected to the HS2 MOSFET source and provides a return

path for the HS driver of channel 2.

Channel 2 low-side driver output.

MULTI-RAIL SECTION

It must be connected to the LS2 MOSFET gate. A small series resistor
helps to reduce device-dissipated power.

Channel 1 low-side driver output.
It must be connected to the LS1 MOSFET gate. A small series resistor

helps to reduce device-dissipated power.

Single-phase rail VREADY
Open drain output set free after SS has finished and pulled low when

triggering any protection on the single-phase rail. Pull up to a voltage
lower than 3.3 V (typ.), if not used it can be left floating.

Doc ID 023399 Rev 1 17/71

Pin description and connection diagrams L6718

Table 2. Pin description (continued)

Pin# Name Function

Multi-phase rail VREADY

52 VREADY

53 CS4N

54 CS4P

55 CS2P

56 CS2N

Open drain output set free after SS has finished and pulled low when
triggering any protection on multi-phase rail. Pull up to a voltage lower
than 3.3 V (typ.), if not used it can be left floating

Channel 4 current sense negative input.
Connect through an R

resistor to the output-side of channel 4 inductor.

G

Filter the output-side of RG with 100 nF (typ.) to GND.
Connect to V

through an RG resistor when not using channel 4.

OUT

See Section 14 for proper layout of this connection.

Channel 4 current sense positive input.
Connect through an R-C filter to the phase-side of channel 3 inductor.
Short to V

when not using channel 4.

OUT

See Section 14 for proper layout of this connection.

MULTI-RAIL SECTION

Channel 2 current sense positive input.
Connect through an R-C filter to the phase-side of channel 2 inductor.
See Section 14 for proper layout of this connection.

Channel 2 current sense negative input.
Connect through an R

resistor to the output-side of channel 2 inductor.

G

Filter the output-side of RG with 100 nF (typ.) to GND.
See Section 14 for proper layout of this connection.

PA D G N D

GND connection.
Exposed pad connects also the silicon substrate. It makes a good thermal

contact with the PCB to dissipate the internal power. All internal
references and logic are referenced to this pin.

Connect to power GND plane using 5.3 x 5.3 mm square area on the PCB
and with 9 vias (uniformly distributed) to improve electrical and thermal
conductivity.

18/71 Doc ID 023399 Rev 1

L6718 Pin description and connection diagrams

2.2 Thermal data

Table 3. Thermal data

Symbol Parameter Value Unit

R

T

T

THJA

MAX

STG

T

J

P

tot

Thermal resistance junction-to-ambient
(Device soldered on 2s2p PC board)

TBD °C/W

Maximum junction temperature 150 °C

Storage temperature range -40 to 150 °C

Junction temperature range 0 to 125 °C

Max. power dissipation at T

= 25 °C TDB W

amb

Doc ID 023399 Rev 1 19/71

Electrical specifications L6718

3 Electrical specifications

3.1 Absolute maximum ratings

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit

VCC12 To GND -0.3 to 7.5 V

V

BOOTX-VPHASEx

V

UGATEx-VPHASEx

LGATEx to GND -0.3 to VCC12 + 0.3 V

V

PHASEX

VCC5, STM, TM, PWM3, PWM4,
SIMAX,IMAX, CONFIGX,

All other pins To GND -0.3 to 3.6 V

Maximum withstanding voltage
range test condition: CDF-AEC­Q1000-002- “human body model”
acceptance criteria: “normal
performance”

Positive peak voltage t<400 ns 15 V

Negative peak voltage to GND
t< 400 ns. BOOT>3.5 V

Positive peak voltage to GND
t< 200 ns

To G N D -0 . 3 t o 7 V

BOOTx

Other pins ±1000 V

3.2 Electrical characteristics

(V

= 5 V ± 5%, TJ = 0 °C to 70 °C unless otherwise specified.)

CC

Table 5. Electrical characteristics

-0.3 to VCC12 + 0.3 V

-0.3 to VCC12 + 0.3 V

-8 V

35 V

±750 V

Symbol Parameter Test conditions Min. Typ. Max. Unit

Supply current

I

CC5

I

CC12

I

BOOTX

20/71 Doc ID 023399 Rev 1

VCC5 supply current

VCC12 supply current

BOOTX supply current

ENABLE = High 20 mA

ENABLE = Low 15 mA

ENABLE = High; Lgate open
Phase To GND; BOOT=7 V

ENABLE = Low 1 mA

ENABLE = High; Ugate open
Phase To GND; BOOT=7 V

12 mA

0.9 mA

L6718 Electrical specifications

Table 5. Electrical characteristics (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Power-on

UVLO

VCC5

VCC5 turn-off VCC5 falling 3 V

VCC12 turn-on VCC12 rising 4.75 V

VCC5 turn-on VCC5 rising 4.1 V

UVLO

VCC12

VCC12 turn-off VCC12 falling 4 V

Oscillator, soft-start and enable

MP F

MP F

SP F

SP F

V

OSC

SW

SW

SW

SW

Initial oscillator accuracy OSC = open 180 200 220 kHz

Initial oscillator accuracy OSC = 62 K 429 475 521 kHz

Initial oscillator accuracy OSC = open 180 200 220 kHz

Initial oscillator accuracy OSC = 62 K 450 500 550 kHz

PWM ramp amplitude 1.5 V

Voltage at pin SOSC After latch 3 V

FAULT

Voltage at pin OSC After latch 3 V

SOFT
START

SS time

Tu r n - on V

ENABLE

Tu r n- o ff V

SVI Serial Bus

Vboot > 0, from pinstrapping; multi­phase section

Vboot > 0, from pinstrapping; single­phase section

rising 0.65 V

ENABLE

falling 0.4 V

ENABLE

2.5 2.8 3.1 mV/μs

2.5 2.8 3.1 mV/μs

SVCLCK,
SVDATA

SVDATA,
ALERT#

Input high 0.6 V

Input low 0.4 V

Voltage low (ACK) I

Reference and current reading

K

VID

K

SVID

DROOP

DROOP

SDROOP

SDROOP

V

accuracy (MPhase)

OUT

V

accuracy (SPhase)

OUT

LL accuracy (MPhase) 0
to full load

LL accuracy (MPhase) 0
to full load

LL accuracy (SPhase) 0
to full load

LL accuracy (SPhase) 0
to full load

= -5 mA 50 mV

SINK

=0 A; N=4; RG= 810 Ω;

I

OUT

R

=2.125 kΩ

FB

I

=0 A

OUT

RG=1.1 kΩ; R

=0; N=4; VID>1 V

I

INFOx

= 6.662 kΩ

FB

RG=810 Ω; RFB=2.125 kΩ

=20 μA; N=4; VID>1 V

I

INFOx

RG=810 Ω; RFB=2.125 kΩ

=0; VID>1 V

I

SCSN

RG=1.1 kΩ; RFB=6.662 kΩ

=20 μA;VID>1 V

I

SCSN

RG=1.1 kΩ; RFB=6.662 kΩ

-0.5 0.5 %

-0.5 0.5 %

-2.5 2 μA

-3.5 4 μA

-0.75 0.75 μA

-1.5 1.5 μA

Doc ID 023399 Rev 1 21/71

Electrical specifications L6718

Table 5. Electrical characteristics (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

=0 μA; N=4;

k

IMON

k

SIMON

IMON accuracy (MPhase)

SIMON accuracy
(SPhase)

INFOx

RG=810 Ω; RFB=2.125 kΩ

I

=20 μA; N=4;

INFOx

RG=810 Ω; RFB=2.125 kΩ

=0 μA;

I

SCSN

RG=1.1 kΩ; RFB=6.662 kΩ

I

=20 μA;

SCSN

RG=1.1 kΩ; RFB=6.662 kΩ

-1.5 1.5 μA

-2 2 μA

-0.75 0.75 μA

-1 1 μA

A

0

EA DC gain 100 dB

SR Slew rate COMP, SCOMP to GND = 10 pF 20 V/μs

DVI D

Slew rate fast

Multi-phase section

10 mV/μs

Slew rate slow 2.5 mV/μs

DVI D

Slew rate fast

Single-phase section

10 mV/μs

Slew rate slow 2.5 mV/μs

IMON ADC

GetReg(15h)

V

= 0.992 V

Accuracy C0 CF Hex

IMON

CC Hex

PWM OUTPUTS

PWM3 /
SPWM

I

PWM3,IPWM4

Output high I = 1 mA 5 V

Output low I = -1 mA 0.2 V

Pull-up current 10 μA

Protection (both sections)

VSEN rising; wrt Ref. +175 mV

OVP Overvoltage protection

VSEN rising; wrt Ref. +500 mV

UVP Undervoltage protection VSEN falling; wrt Ref; Ref > 500 mV -500 mV

FBR DISC FB disconnection Vcs - rising above VSEN/SVSEN +700

FBG DISC FBG disconnection EA NI input wrt VID +500

VREADY,
SVREADY,

Voltage low I = - 4 mA 0.4 V

VRHOT

1.70 V

V

OC_TOT

I

OC_TH

VRHOT Voltage low I

Overcurrent threshold V

IMON

, V

SIMON

rising

1.55 V

Constant current 35 μA

= -5 mA 13 mΩ

SINK

Gate drives control

t

RISE_UGATE

High-side rise time

BOOTx - PHASEx =7 V
C

to GND=3.3 nF

UGATE

TBD ns

22/71 Doc ID 023399 Rev 1