ST L6716 User Manual

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2/3/4 phase controller with embedded drivers for Intel® VR11.1

Features

■ Load transient boost LTB Technology™ to

minimize the number of output capacitors

■ 2 or 3-phase operation with internal driver

■ 4-phase operation with external PWM driver

signal

■ PSI input with programmable strategy

■ Imon output

■ 0.5% output voltage accuracy

■ 8-bit programmable output up to 1.60000 V -

Intel VR11.1 DAC - backward compatible with VR10/VR11

■ Full differential current sense across inductor

■ Differential remote voltage sensing

■ Adjustable voltage offset

■ LSLess startup to manage pre-biased output

■ Feedback disconnection protection

■ Preliminary overvoltage protection

■ Programmable overcurrent protection

■ Programmable overvoltage protection

■ Adjustable switching frequency

■ SS_END and OUTEN signal

■ VFQFPN-48 7x7 mm package with exposed

pad

Applications

■ High current VRM/VRD for desktop / server /

workstation CPUs

■ High density DC/DC converters

L6716

VFQFPN-48 - 7 x 7 mm

Description

The device implements a two-to-four phases stepdown controller with three integrated high current drivers in a compact 7x7 mm body package with exposed pad.

Load transient boost LTB Technology™ reduces system cost by providing the fastest response to load transition therefore requiring less bulk and ceramic output capacitors to satisfy load transient requirements.

The device embeds VR11.x DACs: the output voltage ranges up to 1.60000 V managing D-VID with ±0.5% output voltage accuracy over line and temperature variations.

The controller assures fast protection against load overcurrent and under / overvoltage (in this last case also before UVLO). Feedback disconnection prevents from damaging the load in case of disconnections in the system board.

In case of overcurrent, the system works in constant current mode until UVP.

Table 1. Device summary

January 2010 Doc ID 14521 Rev 3 1/57

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L6716

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Contents L6716

Contents

1 Principle application circuit and block diagram . . . . . . . . . . . . . . . . . . . 4

1.1 Principle application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Pin description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Voltage identifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7 DAC and Phase number selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

9 Current reading and current sharing loop . . . . . . . . . . . . . . . . . . . . . . 23

10 Differential remote voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

11 Voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

11.1 Offset (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

11.2 Droop function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

12 Droop thermal compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

13 Output current monitoring (IMON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

14 Load transient boost technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2/57 Doc ID 14521 Rev 3

L6716 Contents

15 Dynamic VID transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

16 Enable and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

17 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

17.1 Low-side-less startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

18 Output voltage monitor and protections . . . . . . . . . . . . . . . . . . . . . . . . 39

18.1 Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

18.2 Preliminary overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

18.3 Overvoltage and programmable OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

18.4 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

18.5 Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

19 Low power state management and PSI# . . . . . . . . . . . . . . . . . . . . . . . . 44

20 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

21 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

22 System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

23 Tolerance band (TOB) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

23.1 Controller tolerance (TOBController) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

23.2 External current sense circuit tolerance (TOBCurrSense) . . . . . . . . . . . . 50

23.3 Time constant matching error tolerance (TOBTCMatching) . . . . . . . . . . . 50

23.4 Temperature measurement error (VTC) . . . . . . . . . . . . . . . . . . . . . . . . . . 51

24 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

24.1 Power components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

24.2 Small signal components and connections . . . . . . . . . . . . . . . . . . . . . . . 53

25 Embedding L6716 - based VR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

26 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Doc ID 14521 Rev 3 3/57

Principle application circuit and block diagram L6716

1 Principle application circuit and block diagram

1.1 Principle application circuit

to BOOT1

to BOOT3

220nF

ROUT

(a)

Vcc_core

LOAD

GND_core

Figure 1. Principle application circuit for VR11.1 - 2 phase operation

VCCDR

VCC

SGND

OVPSEL

OCSET/PSI_A

OFFSET

LTBGAIN

OSC/FAULT

SSOSC

SSEND

VID7

VID6

VID5

VID4

VID3

VID2

VID1

VID0

PSI

OUTEN

IMON

LTB

COMP

VSEN

FBG

L6716

PWM4 / PH_SEL

PGND

BOOT1

UGATE1

PHASE1

LGATE1

CS1-

CS1+

BOOT2

UGATE2

PHASE2

LGATE2

CS2-

CS2+

BOOT3

UGATE3

PHASE3

LGATE3

CS3-

CS3+

CS4-

CS4+

VIN

HS1

LS1

VIN

HS3

LS3

CIN

220nF

COUT

220nF

VIN

GNDIN

Optional:Pre-OVP

Vcc

ROVP

ROCSET

ROFFSET

RLTBGAIN

ROSC_SGND

ROSC_VCC

To Vcc

RSS_FLIM

RSSOSC

Optional:

See DS

VTT

SS_END

+3V3

RIMON_OS

RIMON_TOT

CLTB

RLTB

L6716 REF.SCH: 2Phase Operation

To GND CORE

RFLIMT

10k

VID bus from CPU

To CPU

To Enable circuitry

NTC

RFB

RFB1

RFB2

RFB3

NTC

CIMON

a. Refer to the application note for the reference schematic.

4/57 Doc ID 14521 Rev 3

L6716 Principle application circuit and block diagram

Figure 2. Principle application circuit for VR11.1- 3 phase operation

GND

Optional:Pre-OVP

OVP

OCSET

OFFSET

LTBGAIN

OSC_SGND

Optional:

See DS

To Vcc

SSOSC

10k

OSC_VCC

SS_FLIM

FLIMT

VTT

IMON_TOT

IMON_OS

VID bus from CPU

To CPU

To Enable circuitry

NTC

33 32

31 30 29 28 27 26

MON

SS_END

+3V3

To GND CORE

LTB

FB1

FB3

NTC

FB2

L6716 REF.SCH:

3-Phase Operation

VCCDR

VCC

SGND

OVPSEL

OCSET/PSI_A

OFFSET

LTBGAIN

OSC/FAULT

SSOSC

SSEND

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

PSI

OUTEN

IMON

LTB

COMP

VSEN

FBG

PGND

BOOT1

UGATE1

PHASE1

LGATE1

CS1-

CS1+

BOOT2

UGATE2

PHASE2

LGATE2

CS2-

CS2+

BOOT3

L6716

UGATE3

PHASE3

LGATE3

CS3-

CS3+

PWM4 / PH_SEL

CS4-

CS4+

HS1

LS1

HS2

220nF

LS2

HS3

220nF

LS3

220nF

(b)

to BOOT1

to BOOT2

to BOOT3

Vcc_core

OUT

LOAD

OUT

GND_core

220nF

b. Refer to the application note for the reference schematic.

Doc ID 14521 Rev 3 5/57

Principle application circuit and block diagram L6716

Figure 3. Principle application circuit for VR11.1- 4 phase operation

GND

Optional:Pre-OVP

Optional:

See DS

VTT

SS_END

+3V3

IMON_TOT

To GND CORE

L6716 REF.SCH: 4-Phase Operation

IMON_OS

LTB

To Vcc

SSOSC

10k

VID bus from CPU

To CPU

To Enable circuitry

NTC

FB1

FB3

OVP

OCSET

OFFSET

LTBGAIN

OSC_SGND

OSC_VCC

SS_FLIM

NTC

FLIMT

33 32

31 30

29 28 27 26

MON

FB2

VCCDR

VCC

SGND

OVPSEL

OCSET/PSI_A

OFFSET

LTBGAIN

OSC/FAULT

SSOSC

SSEND

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

PSI

OUTEN

IMON

LTB

COMP

VSEN

FBG

PGND

BOOT1

UGATE1

PHASE1

LGATE1

CS1-

CS1+

BOOT2

UGATE2

PHASE2

LGATE2

CS2-

CS2+

BOOT3

L6716

UGATE3

PHASE3

LGATE3

CS3-

CS3+

25 PWM4 / PH_SEL

CS4-

CS4+

HS1

LS1

220nF

HS2

LS2

220nF

OUT

HS3

LS3

220nF

VIN

Optional

VCC

EX_PAD

PVCC

BOOT

UGATE

PHASE

L6741

LGATE

HS4

LS4

3V3

PWM

GND

(c)

to BOOT1

to BOOT2

to BOOT3

220nF

Vcc_core

LOAD

OUT

GND_core

c. Refer to the application note for the reference schematic.

6/57 Doc ID 14521 Rev 3

L6716 Principle application circuit and block diagram

1.2 Block diagram

Figure 4. Block diagram

BOOT1

UGATE1

PHASE1

LGATE1

BOOT2

UGATE2

PHASE2

LGATE2

BOOT3

UGATE3

PHASE3

LGATE3

SS_END

OSC / FAULT

SSOSC

VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7

PSI

2/4 PHASE

OSCILLATOR

DIGITAL

SOFT START

DAC

OUTEN

HS1 LS1

LTB

VID CONTROL

WITH DYNAMIC

10uA

HS2

LOGIC PWM

ADAPTIVE ANTI

CROSS CONDUCTION

CURRENT SHARING CORRECTION

PWM1 PWM2 PWM3

VCC

VCCDR

OUTEN

SSOSC

DROOP

FFSET O

LTB

PWM1

CONTROL LOGIC

AND PROTECTIONS

VREF

GND DROP RECOVERY

FBG

ERROR

AMPLIFIER

COMP

OFFSET

LS2 HS3

LOGIC PWM

ADAPTIVE ANTI

CROSS CONDUCTION

CURRENT SHARING CORRECTION

PWM2

PWM3

L6716

TOTAL DELIVERED CURRENT

+175mV / 1.800V / OVP

COMPARATOR

+.1240V

50uA

VSEN

OFFSET

PWM4

OCP

PSI

OVP

LTB

CROSS CONDUCTION

CURRENT SHARING CORRECTION

LTB

OCSET

+.1240V

LS3

LOGIC PWM

ADAPTIVE ANTI

AVERAGE

CURRENT

OCSET

/PSI_A

OCSET

PGND

LTB

CH4 CURRENT

CH1 CURRENT

CH2 CURRENT

CH3 CURRENT

20uA

OVP

OVPSEL

VCCDR

+.1240V

CURRENT SHARING CORRECTION

PWM4

READING

IMON

PWM4/PH_SEL

10uA

LTBGAIN

CS4-

CS4+

CS1CS1+

CS2CS2+

CS3-

CS3+

VCC

DROOP

VCC

SGND

Doc ID 14521 Rev 3 7/57

Pin description and connection diagram L6716

2 Pin description and connection diagram

Figure 5. Pin connection (top view)

BOOT3

SSEND

PSI

VID7

VID6

VID5

VID4

VID3

VID2

VID1

VID0

PWM4/

PH_SEL

UGATE3

PHASE3

BOOT2

UGATE2

PHASE2

VCCDR

LGATE3

LGATE2

LGATE1

N.C.

PHASE1

UGATE1

36 35 34 33 32 31 30 29 28 27 26 25

123456789101112

49 PGND

CS4-

CS4+

CS3-

CS3+

CS2-

CS2+

CS1-

CS1+

OUTEN

SSOSC

OSC/FAULT

OCSET/PSI_A

2.1 Pin description

Table 2. Pin description

N° Name Description

Channel 1 HS driver supply.

1BOOT1

2 SGND All the internal references are referred to this pin. Connect it to the PCB signal ground.

3VCC

4COMP

5FB

6VSEN

7FBG

Connect through a capacitor (100 nF typ.) to PHASE1 and provide necessary bootstrap diode. A small resistor in series to the boot diode helps in reducing boot capacitor overcharge.

Device supply voltage pin. The operative supply voltage is 12 V ±15%. Filter with at least 1 μF capacitor vs. SGND.

Error amplifier output. Connect with an R The device cannot be disabled by pulling down this pin.

Error amplifier inverting input pin. Connect with a resistor R A current proportional to the load current is sourced from this pin in order to implement the

Droop effect. See “Droop function” Section for details.

Output voltage monitor, manages OVP/UVP protections and FB disconnection. Connect to the positive side of the load to perform remote sense.

See “Layout guidelines” Section for proper layout of this connection.

Connect to the negative side of the load to perform remote sense.

See “Layout guidelines” Section for proper layout of this connection.

VCC

SGND

BOOT1

COMP

vs. VSEN and with an RF - CF//CP vs. COMP pin.

LT B

FBG

VSEN

IMON

LTBGAIN

- CF//CP vs. FB pin.

OFFSET

OVPSEL

8/57 Doc ID 14521 Rev 3

L6716 Pin description and connection diagram

Table 2. Pin description (continued)

N° Name Description

Load transient boost pin. Internally fixed at 2 V, connecting a R

8LTB

boost technology™: as soon as the device detects a transient load it turns on all the PHASEs at the same time. Short to SGND to disable the function.

See “Load transient boost technology” Section for details.

Current monitor output pin.

9IMON

A current proportional to the load current is sourced from this pin. Connect through a resistor

to FBG to implement a load indicator. Connect the load indicator directly to VR11.1

MON

CPUs.The pin voltage is clamped to 1.1 V max to preserve the CPU from excessive voltages.

Load transient boost technology™ gain pin.

10 LTBGAIN

Internally fixed at 1.24 V, connecting a R the LTB action. See See “Load transient boost technology” Section for details.

Offset programming pin. Internally fixed at 1.240 V, connecting a R

11 OFFSET

that is mirrored into FB pin in order to program a positive offset according to the selected R Short to SGND to disable the function.

See “Offset (optional)” Section for details.

Overvoltage programming pin. Internally pulled up by 20 µA (typ) to 3.3 V. Leave floating to use built-in protection thresholds (OVP

12 OVPSEL

Connect to SGND through a R threshold to a fixed voltage according to the R

OVP

See “Overvoltage and programmable OVP” Section for details.

Connect to SGND to select VR10/VR11 table. In this case the OVP threshold becomes

1.800 V (typ).

Overcurrent setting, PSI action pin.

OCSET/

PSI_A

Connect to SGND through a R

OCSET

It also allows to select the number of phase when PSI mode is selected.

See “Overcurrent protection” Section for details.

Oscillator, FAULT pin. It allows programming the switching frequency FSW of each channel: the equivalent switching

frequency at the load side results in being multiplied by the phase number N.

OSC/

FAULT

Frequency is programmed according to the resistor connected from the pin vs. SGND or VCC with a gain of 9.1 kHz/µA (see relevant section for details).

Leaving the pin floating programs a switching frequency of 200 kHz per phase. The pin is forced high (3.3 V typ) to signal an OVP/UVP fault: to recover from this condition,

cycle VCC or the OUTEN pin. See “Oscillator” Section for details.

Soft-start oscillator pin. By connecting a resistor R

15 SSOSC

Soft-Start time T implemented to reach V V

to the programmed VID code. The pin is kept to a fixed 1.240 V.

BOOT

See “Soft-start” Section for details.

will proportionally change with a gain of 25 [µs / kΩ]. The same slope

to GND, it allows programming the soft-start time.

has to be considered also when the reference moves from

BOOT

- C

LT B

LTBGAIN

OFFSET

vs. V

resistor vs SGND allows setting the gain of

resistor vs. SGND allows setting a current

allows to enable the load transient

OUT

= VID + 175 mV typ).

resistor and filter with 100 pF (max) to set the OVP

resistor.

OVP

resistor to set the OCP threshold for each phase.

Doc ID 14521 Rev 3 9/57

Pin description and connection diagram L6716

Table 2. Pin description (continued)

N° Name Description

Output enable pin. Internally pulled up by 10 µA (typ) to 3 V. Forced low, the device stops operations with all MOSFETs OFF: all the protections are

16 OUTEN

17 CS1+

18 CS1-

19 CS2+

20 CS2-

21 CS3+

22 CS3-

disabled except for preliminary overvoltage. Leave floating, the device starts-up implementing soft-start up to the selected VID code. Cycle this pin to recover latch from protections; filter with 1 nF (typ) vs. SGND.

Channel 1 current sense positive input. Connect through an R-C filter to the phase-side of the channel 1 inductor.

See “Layout guidelines” Section for proper layout of this connection.

Channel 1 current sense negative input. Connect through a Rg resistor to the output-side of the channel 1 inductor.

See “Layout guidelines” Section for proper layout of this connection.

Channel 2 current sense positive input. Connect through an R-C filter to the phase-side of the channel 2 inductor. Short to V

when using 2-phase operation.

OUT

See “Layout guidelines” Section for proper layout of this connection.

Channel 2 current sense negative input. Connect through a Rg resistor to the output-side of the channel 2 inductor. Still connect to V

through Rg resistor when using 2-phase operation.

OUT

See “Layout guidelines” Section for proper layout of this connection.

Channel 3 current sense positive input. Connect through an R-C filter to the phase-side of the channel 3 inductor.

See “Layout guidelines” Section for proper layout of this connection.

Channel 3 current sense negative input. Connect through a Rg resistor to the output-side of the channel 3 inductor.

See “Layout guidelines” Section for proper layout of this connection.

Channel 4 current sense positive input.

23 CS4+

Connect through an R-C filter to the phase-side of the channel 4 inductor. Short to V

when using 2-phase or 3-phase operation.

OUT

See “Layout guidelines” Section for proper layout of this connection.

Channel 4 current sense negative input.

24 CS4-

Connect through a Rg resistor to the output-side of the channel 4 inductor. Still connect to V

through Rg resistor when using 2-phase or 3-phase operation.

OUT

See “Layout guidelines” Section for proper layout of this connection.

PWM outputs, phase selection pin. Internally pulled up by 10 µA to 3.3 V (until the soft-start has not finished), connect to external

driver PWM input when 4-phase operation is used. The device is able to manage HiZ status by setting the pis floating.

PWM4/

PH_SEL

Short to SGND to select 3-phase operation and leave floating to select 2-phase operation.

26 to 33

VID0 to

VID7

Voltage identification pins. (not internally pulled up). Connect to SGND to program a '0' or connect to the external pull-up resistor to program a '1'.

They allow programming output voltage as specified in Tab l e 7 .

10/57 Doc ID 14521 Rev 3

L6716 Pin description and connection diagram

Table 2. Pin description (continued)

N° Name Description

Power saving indicator pin.

34 PSI

35 SSEND

36 BOOT3

37 UGATE3

38 PHASE3

39 BOOT2

40 UGATE2

Connect to the PSI pin of the CPU to manage low-power state. When asserted (pulled low), the controller will act as programmed on the OCSET/PSI_A.

Soft-start END signal. Open drain output sets free after ss has finished and pulled low when triggering any

protection. Pull up to a voltage lower than 3.3 V, if not used it can be left floating.

Channel 3 HS driver supply. Connect through a capacitor (100 nF typ.) to PHASE3 and provide necessary bootstrap

diode.A small resistor in series to the boot diode helps in reducing boot capacitor overcharge.

Channel 3HS driver output. It must be connected to the HS3 MOSFET gate. A small series resistors helps in reducing

device-dissipated power.

Channel 3 HS driver return path. It must be connected to the HS3 MOSFET source and provides return path for the HS driver

of channel 3.

Channel 2 HS driver supply. Connect through a capacitor (100 nF typ.) to PHASE2 and provide necessary bootstrap diode.

A small resistor in series to the boot diode helps in reducing Boot capacitor overcharge. Leave floating when using 2-Phase operation.

Channel 2HS driver output. It must be connected to the HS2 MOSFET gate. A small series resistors helps in reducing

device-dissipated power. Leave floating when using 2-Phase operation.

Channel 2 HS driver return path.

41 PHASE2

It must be connected to the HS2 MOSFET source and provides return path for the HS driver of channel 2. Leave floating when using 2-phase operation.

42 VCCDR

43 LGATE3

LS Driver Supply. VCDDR pin voltage has to be the same of VCC pin. Filter with 2 x 1 µF MLCC capacitor vs. PGND.

Channel 3LS driver output. A small series resistor helps in reducing device-dissipated power.

Channel 2LS driver output.

44 LGATE2

A small series resistor helps in reducing device-dissipated power. Leave floating when using 2-phase operation.

45 LGATE1

Channel 1LS driver output. A small series resistor helps in reducing device-dissipated power.

46 N.C. Not internally connected.

Channel 1 HS driver return path.

47 PHASE1

It must be connected to the HS1 MOSFET source and provides return path for the HS driver of channel 1.

Doc ID 14521 Rev 3 11/57

Pin description and connection diagram L6716

Table 2. Pin description (continued)

N° Name Description

Channel 1HS driver output.

48 UGATE1

49 PGND

It must be connected to the HS1 MOSFET gate. A small series resistors helps in reducing device-dissipated power.

Power ground pin (LS drivers return path). Connect to power ground plane. Exposed pad connects also the silicon substrate. As a consequence it makes a good thermal

contact with the PCB to dissipate the power necessary to drive the external MOSFETs. Connect it to the power ground plane using 5.2 x 5.2 mm square area on the PCB and with

sixteen vias (uniformly distributed), to improve electrical and thermal conductivity.

12/57 Doc ID 14521 Rev 3

L6716 Maximum ratings

3 Maximum ratings

3.1 Absolute maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

CC, VCCDR

BOOTx

PHASEx

UGATEx

PHASEx

To P GN D 1 5 V

Boot voltage 15 V

LGATEx to PGND

All other pins to PGND -0.3 to 3.6 V

Negative peak voltage to PGND; T < 400 ns VCC = VCCDR = 12 V

PHASE

Positive voltage to PGND VCC = VCCDR = 12 V

Positive peak voltage to PGND; T < 200 ns VCC = VCCDR = 12 V

Maximum withstanding voltage range test condition: CDF-AEC-Q100-002- “human body model” acceptance criteria: “normal performance”

3.2 Thermal data

15 V

-0.3 to

Vcc+0.3

-8 V

26 V

30 V

+/- 1750 V

Table 4. Thermal data

Symbol Parameter Value Unit

thJA

MAX

stg

tot

Thermal resistance junction to ambient (Device soldered on 2s2p PC board)

40 °C / W

Maximum junction temperature 150 °C

Storage temperature range -40 to 150 °C

Junction temperature range -10 to 125 °C

Max power dissipation at TA = 25 °C 2.5 W

Doc ID 14521 Rev 3 13/57

Electrical characteristics L6716

4 Electrical characteristics

4.1 Electrical characteristics

= 12 V ± 15%, TJ = 0 °C to 70 °C unless otherwise specified.

Table 5. Electrical characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

Supply current and power-on

CCDR

BOOTx

VCC supply current

VCCDR supply current LGATEx = OPEN; VCCDR = 12 V 5 7 mA

BOOTx supply current

UGATEx and LGATEx open; VCC = VBOOTx = 12 V

UGATEx = OPEN; PHASEx to PGND; VCC = BOOTx = 12V

22 25 mA

1.8 2.7 mA

Power-on

VCC turn-ON VCC rising; VCCDR = VCC 3.7 4.0 V

UVLO

VCC

VCC turn-OFF VCC falling; VCCDR = VCC 3.3 3.5 V

Pre-OVP turn-ON VCC rising; VCCDR = VCC 3.7 4.0 V

UVLO

Pre-OVP

Pre-OVP turn-OFF VCC falling; VCCDR = VCC 3.3 3.5 V

Oscillator and inhibit

OSC

Initial accuracy OSC=OPEN; TJ = 0 to 125 °C 180 200 220 kHz

SS delay time 1 1.5 ms

SS TD2 time R

SS TD3 time 150 250 μs

= 20 kΩ 500 μs

SSOSC

Rising thresholds voltage 0.80 0.85 0.90 V

Output enable

OUTEN

Hysteresis 100 mV

Output pull-up current OUTEN to SGND 10 μA

ΔVosc Ramp amplitude 1.5 V

FAULT Voltage at pin OSC/FAULT OVP and UVP Active 3.3 V

Reference and DAC

VID = 1.000 V to VID = 1.600 V FB = VOUT; FBG = GNDOUT

VID

BOOT

Output voltage accuracy

Boot voltage 1.081 V

VID = 0.800 V to VID = 1.000 V FB = VOUT; FBG = GNDOUT

VID = 0.500 V to VID = 0.800 V FB = VOUT; FBG = GNDOUT

14/57 Doc ID 14521 Rev 3

-0.5 - 0.5 %

-5 - +5 mV

-8 - +8 mV

L6716 Electrical characteristics

Table 5. Electrical characteristics (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

VID

VID pull-up current VIDx to SGND 0 μA

VID thresholds

Input low 0.35 V

Input high 0.8 V

Input low 0.4

PSI thresholds

PSI

Input high 0.8

PSI pull-up current PSI to SGND 0 μA

Error amplifier

EA DC gain 130 dB

SR EA slew-rate COMP = 10 pF to SGND 25 V/μs

Differential current sensing and offset

CSx+

OCSET

Bias current 0 μA

OCSET pin voltage 1.105 1.245 1.385 mV

Rg = 1 kΩ;

DROOP

= 25 μA; = 50 μA; = 75 μA; = 100 μA;

-3 - +3 μA

IDROOP

IOFFSET

OFFSET

Droop current deviation from nominal value

1-PHASE, I 2-PHASE, I 3-PHASE, I 4-PHASE, I

Offset current accuracy I

= 50 μA to 250 μA-5-5%

OFFSET

OFFSET current range 0 250 μA

OFFSET pin bias I

= 0 to 250 μA1.240V

OFFSET

Gate drivers

RISE UGATE

UGATEx

RISE LGATE

LGATEx

PWM output

PWM4

High side rise time

BOOTx-PHASEx = 12 V; C

to PHASEx = 3.3 nF

UGATEx

20 ns

High side source current BOOTx-PHASEx = 12 V 1.5 A

High side sink resistance BOOTx-PHASEx = 12 V 2 Ω

Low side rise time

VCCDR = 12 V; C

to PGNDx = 5.6 nF

LGATEx

25 ns

Low side source current VCCDR = 12 V 2 A

Low side sink resistance VCCDR = 12 V 1 Ω

Output high I = 1 mA 3 V

Output low I = -1 mA 0.2 V

PWM4 pull-up current Before SSEND = 1; PWM4 to SGND 10 μA

Doc ID 14521 Rev 3 15/57

Electrical characteristics L6716

Table 5. Electrical characteristics (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

Protections

OVP

Programmab

le OVP

Pre- OVP

Overvoltage protection (VSEN rising)

current OVP = SGND 20 22 24 μA

OVP

Before V

BOOT

Above VID-19 mV (after TD

) 150 175 200 mV

Comparator offset voltage OVP = 1.800 V -20 0 20 mV

< VCC < UVLO

OVP

VCC

and OUTEN = SGND

1.750 1.800 1.850 V

Preliminary overvoltage protection

UVLO VCC> UVLO VSEN rising

1.24 1.300 V

Hysteresis 350 mV

UVP Under voltage threshold VSEN falling; below VID-19 mV 550 600 650 mV

SSEND

SS_END voltage low I = -4 mA 0.4 V

16/57 Doc ID 14521 Rev 3

L6716 Voltage identifications

5 Voltage identifications

Table 6. Voltage identification (VID) mapping for intel VR11.1 mode

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

800 mV 400 mV 200 mV 100 mV 50 mV 25 mV 12.5 mV 6.25 mV

Table 7. Voltage identification (VID) for Intel VR11.1 mode

HEX code

Output

voltage

(1)

HEX code

Output

voltage

HEX code

(1)

Output

voltage

HEX code

(1)

Output

voltage

0 0 OFF 4 0 1.21250 8 0 0.81250 C 0 0.41250

0 1 OFF 4 1 1.20625 8 1 0.80625 C 1 0.40625

0 2 1.60000 4 2 1.20000 8 2 0.80000 C 2 0.40000

0 3 1.59375 4 3 1.19375 8 3 0.79375 C 3 0.39375

0 4 1.58750 4 4 1.18750 8 4 0.78750 C 4 0.38750

0 5 1.58125 4 5 1.18125 8 5 0.78125 C 5 0.38125

0 6 1.57500 4 6 1.17500 8 6 0.77500 C 6 0.37500

0 7 1.56875 4 7 1.16875 8 7 0.76875 C 7 0.36875

0 8 1.56250 4 8 1.16250 8 8 0.76250 C 8 0.36250

0 9 1.55625 4 9 1.15625 8 9 0.75625 C 9 0.35625

0 A 1.55000 4 A 1.15000 8 A 0.75000 C A 0.35000

0 B 1.54375 4 B 1.14375 8 B 0.74375 C B 0.34375

0 C 1.53750 4 C 1.13750 8 C 0.73750 C C 0.33750

0 D 1.53125 4 D 1.13125 8 D 0.73125 C D 0.33125

0 E 1.52500 4 E 1.12500 8 E 0.72500 C E 0.32500

0 F 1.51875 4 F 1.11875 8 F 0.71875 C F 0.31875

(1)

1 0 1.51250 5 0 1.11250 9 0 0.71250 D 0 0.31250

1 1 1.50625 5 1 1.10625 9 1 0.70625 D 1 0.30625

1 2 1.50000 5 2 1.10000 9 2 0.70000 D 2 0.30000

1 3 1.49375 5 3 1.09375 9 3 0.69375 D 3 0.29375

1 4 1.48750 5 4 1.08750 9 4 0.68750 D 4 0.28750

1 5 1.48125 5 5 1.08125 9 5 0.68125 D 5 0.28125

1 6 1.47500 5 6 1.07500 9 6 0.67500 D 6 0.27500

1 7 1.46875 5 7 1.06875 9 7 0.66875 D 7 0.26875

1 8 1.46250 5 8 1.06250 9 8 0.66250 D 8 0.26250

1 9 1.45625 5 9 1.05625 9 9 0.65625 D 9 0.25625

Doc ID 14521 Rev 3 17/57

Voltage identifications L6716

Table 7. Voltage identification (VID) for Intel VR11.1 mode (continued)

HEX code

Output

voltage

(1)

HEX code

Output

voltage

HEX code

(1)

Output

voltage

HEX code

(1)

Output

voltage

1 A 1.45000 5 A 1.05000 9 A 0.65000 D A 0.25000

1 B 1.44375 5 B 1.04375 9 B 0.64375 D B 0.24375

1 C 1.43750 5 C 1.03750 9 C 0.63750 D C 0.23750

1 D 1.43125 5 D 1.03125 9 D 0.63125 D D 0.23125

1 E 1.42500 5 E 1.02500 9 E 0.62500 D E 0.22500

1 F 1.41875 5 F 1.01875 9 F 0.61875 D F 0.21875

2 0 1.41250 6 0 1.01250 A 0 0.61250 E 0 0.21250

2 1 1.40625 6 1 1.00625 A 1 0.60625 E 1 0.20625

2 2 1.40000 6 2 1.00000 A 2 0.60000 E 2 0.20000

2 3 1.39375 6 3 0.99375 A 3 0.59375 E 3 0.19375

2 4 1.38750 6 4 0.98750 A 4 0.58750 E 4 0.18750

2 5 1.38125 6 5 0.98125 A 5 0.58125 E 5 0.18125

2 6 1.37500 6 6 0.97500 A 6 0.57500 E 6 0.17500

2 7 1.36875 6 7 0.96875 A 7 0.56875 E 7 0.16875

2 8 1.36250 6 8 0.96250 A 8 0.56250 E 8 0.16250

2 9 1.35625 6 9 0.95625 A 9 0.55625 E 9 0.15625

2 A 1.35000 6 A 0.95000 A A 0.55000 E A 0.15000

(1)

2 B 1.34375 6 B 0.94375 A B 0.54375 E B 0.14375

2 C 1.33750 6 C 0.93750 A C 0.53750 E C 0.13750

2 D 1.33125 6 D 0.93125 A D 0.53125 E D 0.13125

2 E 1.32500 6 E 0.92500 A E 0.52500 E E 0.12500

2 F 1.31875 6 F 0.91875 A F 0.51875 E F 0.11875

3 0 1.31250 7 0 0.91250 B 0 0.51250 F 0 0.11250

3 1 1.30625 7 1 0.90625 B 1 0.50625 F 1 0.10625

3 2 1.30000 7 2 0.90000 B 2 0.50000 F 2 0.10000

3 3 1.29375 7 3 0.89375 B 3 0.49375 F 3 0.09375

3 4 1.28750 7 4 0.88750 B 4 0.48750 F 4 0.08750

3 5 1.28125 7 5 0.88125 B 5 0.48125 F 5 0.08125

3 6 1.27500 7 6 0.87500 B 6 0.47500 F 6 0.07500

3 7 1.26875 7 7 0.86875 B 7 0.46875 F 7 0.06875

3 8 1.26250 7 8 0.86250 B 8 0.46250 F 8 0.06250

3 9 1.25625 7 9 0.85625 B 9 0.45625 F 9 0.05625

3 A 1.25000 7 A 0.85000 B A 0.45000 F A 0.05000

3 B 1.24375 7 B 0.84375 B B 0.44375 F B 0.04375

18/57 Doc ID 14521 Rev 3

L6716 Voltage identifications

Table 7. Voltage identification (VID) for Intel VR11.1 mode (continued)

HEX code

Output

voltage

(1)

HEX code

Output

voltage

HEX code

(1)

Output

voltage

HEX code

(1)

Output

voltage

3 C 1.23750 7 C 0.83750 B C 0.43750 F C 0.03750

3 D 1.23125 7 D 0.83125 B D 0.43125 F D 0.03125

3 E 1.22500 7 E 0.82500 B E 0.42500 F E OFF

3 F 1.21875 7 F 0.81875 B F 0.41875 F F OFF

1. According to INTEL specs, the device automatically regulates output voltage 19 mV lower to avoid any external offset to modify the built-in 0.5% accuracy improving TOB performances. Output regulated voltage is than what extracted from the table lowered by 19 mV.

(1)

Doc ID 14521 Rev 3 19/57

Device description L6716

6 Device description

L6716 is two-to-four phase PWM controller with three embedded high current drivers providing complete control logic and protections for a high performance step-down DC-DC voltage regulator optimized for advanced microprocessor power supply. Multi phase buck is the simplest and most cost-effective topology employable to satisfy the increasing current demand of newer microprocessors and modern high current VRM modules. It allows distributing equally load and power between the phases using smaller, cheaper and most common external power MOSFETs and inductors. Moreover, thanks to the equal phase shift between each phase, the input and output capacitor count results in being reduced. Phase interleaving causes in fact input rms current and output ripple voltage reduction.

L6716 is a dual-edge asynchronous PWM controller featuring load transient boost LTB Technology™: the device turns on simultaneously all the phases as soon as a load transient is detected allowing to minimize system cost by providing the fastest response to load transition. Load transition is detected (through LTB pin) measuring the derivate dV/dt of the output voltage and the dV/dt can be easily programmed extending the system design flexibility. Moreover, load transient boost (LTB) Technology™ gain can be easily modified in order to keep under control the output voltage ring back.

LTB Technology™ can be disabled and in this condition the device works as a dual-edge asynchronous PWM.

The controller allows to implement a scalable design: a three phase design can be easily downgraded to two phase and upgraded to four phase (using an external driver).The same design can be used for more than one project saving development and debug time.

L6716 permits easy system design by allowing current reading across inductor in fully differential mode. Also a sense resistor in series to the inductor can be considered to improve reading precision. The current information read corrects the PWM output in order to equalize the average current carried by each phase limiting the error in the static and dynamic conditions.

The controller allows compatibility with both Intel VR11.0 and VR11.1 processors specifications, also performing D-VID transitions accordingly.

The device is VR11.1 compatible implementing IMON signal and managing the PSI# signal to enhance the system performances at low current in low-power states.

Low-side-less start-up allows soft-start over pre-biased output avoiding dangerous current return through the main inductors as well as negative spike at the load side.

L6716 provides a programmable overvoltage protection to protect the load from dangerous over stress, latching immediately by turning ON the lower driver and driving high the OSC/FAULT pin. Furthermore, preliminary OVP protection also allows the device to protect load from dangerous OVP when VCC is not above the UVLO threshold or OUTEN is low. The overcurrent protection is for each phase and externally adjustable through a single resistor. The device keeps constant the peak of the inductor current ripple working in constant current mode until the latched UVP.

A compact 7x7 mm body VFQFPN-48 package with exposed thermal pad allows dissipating the power to drive the external MOSFET through the system board.

20/57 Doc ID 14521 Rev 3

L6716 DAC and Phase number selection

7 DAC and Phase number selection

L6716 embeds VRD11.x DAC (see Tab le 7 ) that allows to regulate the output voltage with a tolerance of ±0.5% recovering from offsets and manufacturing variations.

The device automatically introduces a -19 mV (both VRD11.x and VR10) offset to the regulated voltage in order to avoid any external offset circuitry to worsen the guaranteed accuracy and, as a consequence, the calculated system TOB.

Output voltage is programmed through the VID pins: they are inputs of an internal DAC that is realized by means of a series of resistors providing a partition of the internal voltage reference. The VID code drives a multiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an amplifier obtaining the voltage reference (i.e. the set-point of the error amplifier, V

L6716 implements a flexible 2 to 4 interleaved-phase converter. The device allows to select the phase number operation simply using the PWM4/PHASE_SEL pin, as shown in the following table.

Table 8. Number of phases setting

PWM4 / PH_SEL pin Number of phases Phases used

REF

Floating 2-PHASE Phase1, Phase3

Short to SGND 3-PHASE Phase1, Phase2, Phase3

Connect to PWM driver input 4-PHASE Phase1, Phase2, Phase3, Phase4

Note: PWM4 pin is internally pulled up by 10 µA to 3.3 V, until soft-start is not finished.

For the disabled phase(s), the current reading pins need to be properly connected to avoid errors in current-sharing and voltage-positioning: CSx+ needs to be connected to the regulated output voltage while CSX- needs to be connected to V

trough the same RG

OUT

resistor used for the other phases.

Note: To select VR10/VR11 table, short to SGND the OVP pin. In this case the PSI pin becomes

the VIDSEL pin (to select VR10 and VR11 table, in according to the VR11 specification).

Doc ID 14521 Rev 3 21/57

Power dissipation L6716

8 Power dissipation

L6716 embeds three high current MOSFET drivers for both high side and low side MOSFETs: it is then important to consider the power the device is going to dissipate in driving them in order to avoid overcoming the maximum junction operative temperature.

Exposed pad (PGND pin) needs to be soldered to the PCB power ground plane through several VIAs in order to facilitate the heat dissipation.

Two main terms contribute in the device power dissipation: bias power and drivers' power. The first one (P and it is simply quantifiable as follow (assuming to supply HS and LS drivers with the same VCC of the device):

) depends on the static consumption of the device through the supply pins

DCVCCICCICCDR

N+

⋅+()⋅=

BOOTx

where N

is the number of internal drivers used.

Drivers' power is the power needed by the driver to continuously switch on and off the external MOSFETs; it is a function of the switching frequency and total gate charge of the selected MOSFETs. It can be quantified considering that the total power P

dissipated to

switch the MOSFETs (easy calculable) is dissipated by three main factors: external gate resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance. This last term is the important one to be determined to calculate the device power dissipation.

The total power dissipated to switch the MOSFETs results:

NDF

SWQGHSVBOOT

⋅ Q

⋅+()⋅⋅=

GLSVCCDR

External gate resistors helps the device to dissipate the switching power since the same power P

will be shared between the internal driver impedance and the external resistor

resulting in a general cooling of the device. When driving multiple MOSFETs in parallel, it is suggested to use one gate resistor for each MOSFET.

Figure 6. L6716 dissipated power (quiescent + switching)

22/57 Doc ID 14521 Rev 3

L6716 Current reading and current sharing loop

9 Current reading and current sharing loop

L6716 embeds a flexible, fully-differential current sense circuitry that is able to read across inductor parasitic resistance or across a sense resistor placed in series to the inductor element. The fully-differential current reading rejects noise and allows placing sensing element in different locations without affecting the measurement's accuracy.

Reading current across the inductor DCR, the current flowing trough each phase is read using the voltage drop across the output inductor or across a sense resistor in its series and internally converted into a current. The trans-conductance ratio is issued by the external resistor Rg placed outside the chip between CSx- pin toward the reading points.

The current sense circuit always tracks the current information, no bias current is sourced from the CSx+ pin: this pin is used as a reference keeping the CSx- pin to this voltage. To correctly reproduce the inductor current an R-C filtering network must be introduced in parallel to the sensing element.

The current that flows from the CSx- pin is then given by the following equation (see

Figure 7):

DCR

1 s L DCR()⁄⋅+

-------------

CSx-

------------------------------------------ -

⋅=

1sRC⋅⋅+

I⋅

PHASEx

Where I

is the current carried by the relative phase.

PHASEx

Figure 7. Current reading connections

PHASEx

DCR

PHASEx

CSx+

NO Bias

CSx-=IINFOx

CSx-

Inductor DCR Current Sense

Considering now to match the time constant between the inductor and the R-C filter applied (Time constant mismatches cause the introduction of poles into the current reading network causing instability. In addition, it is also important for the load transient response and to let the system show resistive equivalent output impedance), it results:

Where I

------------- RC I DCR

is the current information reproduced internally.

INFOx

CSx-

DCR

-------------

⋅=⇒⋅ I

PHASEx

INFOx

INFOX

DCR

-------------

⋅=⇒==

PHASEx

The Rg trans-conductance resistor has to be selected using the following formula, in order to guarantee the correct functionality of internal current reading circuitry:

MAX

DCR

------------------------

Where I

OUT

MAX

is the maximum output current, DCR

20μA

MAX

OUT

--------------------------

⋅=

MAX

the maximum inductor DCR and N

number of phases.

Doc ID 14521 Rev 3 23/57

Current reading and current sharing loop L6716

trough the same RG

OUT

resistor used for the other phases, as shown in figure Figure 9.

Figure 8. Current reading connections for the disabled phase

Current Sense connection

Disabled Phase

CSx+

VOUT

CSx-

Current sharing control loop reported in Figure 9: it considers a current I the current delivered by each phase and the average current . The error between the read current I

and the reference I

INFOx

proportional to

INFOx

ΣI

is then converted into a voltage that

AVG

INFOx

N⁄=

with a proper gain is used to adjust the duty cycle whose dominant value is set by the voltage error amplifier in order to equalize the current carried by each phase. Details about connections are shown in Figure 9.

Figure 9. Current sharing loop

AVG

INFO1

AVG

INFO2

From EA

INFO3

PWM1 Out

PWM2 Out

PWM3 Out

INFO4

(PHASE4 Only when using 4-PHASE Operation - PHASE2 when using 3 or 4 PHASE Operation)

24/57 Doc ID 14521 Rev 3

PWM4 Out

L6716 Differential remote voltage sensing

10 Differential remote voltage sensing

The output voltage is sensed in fully-differential mode between the FB and FBG pin.

The FB pin has to be connected through a resistor to the regulation point while the FBG pin has to be connected directly to the remote sense ground point.

In this way, the output voltage programmed is regulated between the remote sense point compensating motherboard or connector losses.

Keeping the FB and FBG traces parallel and guarded by a power plane results in common mode coupling for any picked-up noise.

Figure 10. Differential remote voltage sensing connections

PROG

GND DROP

RECOVERY

OFFSET

DROOP

REF

ERROR AMPLIFIER

FBG

To GND_core

(Remote Sense)

To VCC_core

(Remote Sense)

VSEN

COMP

Doc ID 14521 Rev 3 25/57

Voltage positioning L6716

11 Voltage positioning

Output voltage positioning is performed by selecting the internal reference value through VID pins and by programming the droop function and offset to the reference (see Figure 11). The currents sourced/sunk from FB pin cause the output voltage to vary according to the external R

The output voltage is then driven by the following relationship:

where:

()V

OUTIOUT

PROGRFBIDROOPIOUT

PROG

DROOPIOUT

OFFSET

VID 19mV–=

()

------------------------=

DCR

-------------

1.240V

OFFSET

()I

⋅=

OUT

–[]⋅–=

OFFSET

OFFSET function can be disabled shorting to SGND the OFFSET pin.

Figure 11. Voltage positioning (left) and droop function (right)

PROG

GND DROP

RECOVERY

FBG

To GND_core

(Remote Sense)

11.1 Offset (optional)

The OFFSET pin allows programming a positive offset (VOS) for the output voltage by connecting a resistor R considered in addition to the one already introduced during the production stage (V

OFFSET function can be disabled shorting to SGND the OFFSET pin.

The OFFSET pin is internally fixed at 1.240 V (See Tab l e 5) a current is programmed by connecting the resistor R then properly sunk from the FB pin as shown in Figure 12. Output voltage is then programmed as follow:

=VID-19 mV).

PROG

To VCC_core

(Remote Sense)

OFFSET

VSEN

OFFSET

()V

OUTIOUT

ERROR AMPLIFIER

REF

DROOP

COMP

MAX

NOM

MIN

RESPONSE WITHOUT DROOP

ESR Drop

RESPONSE WITH DROOP

vs. SGND as shown in Figure 12; this offset has to be

between the pin and SGND: this current is mirrored and

PROGRFBIDROOPIOUT

()

1.240V

------------------------–⋅–=

OFFSET

26/57 Doc ID 14521 Rev 3

L6716 Voltage positioning

where:

1.240V

OSRFB

------------------------

⋅=

OFFSET

Offset resistor can be designed by considering the following relationship (RFB is fixed by the Droop effect):

1.240V

OFFSETRFB

------------------ -

⋅=

Offset automatically given by the DAC selection differs from the offset implemented through the OFFSET pin: the built-in feature is trimmed in production and assures ±0.5% error over load and line variations.

Figure 12. Voltage positioning with positive offset

ERROR AMPLIFIER

REF

DROOP

1.240V

OFFSET

PROG

GND DROP

RECOVERY

OFFSET

11.2 Droop function

This method “recovers” part of the drop due to the output capacitor ESR in the load transient, introducing a dependence of the output voltage on the load current: a static error proportional to the output current causes the output voltage to vary according to the sensed current.

As shown in Figure 11, the ESR drop is present in any case, but using the droop function the total deviation of the output voltage is minimized. Moreover, more and more highperformance CPUs require precise load-line regulation to perform in the proper way. DROOP function is not then required only to optimize the output filter, but also becomes a requirement of the load.

The device forces a current I resistor implementing the load regulation dependence. Since I current information about the N phases, the output characteristic vs. load current is then given by (neglecting the OFFSET voltage term):

OUTVPROGRFBIDROOP

ROFFSET

To GND_core

(Remote Sense)

DROOP

⋅– V

FBG

To VCC_core

(Remote Sense)

VSEN

COMP

, proportional to the read current, into the feedback RFB

depends on the

DROOP

DCR

-------------

REFRFB

⋅⋅– V

OUT

PROGRDROOPIOUT

⋅–== =

Where DCR is the inductor parasitic resistance (or sense resistor when used) and I

OUT

is the output current of the system. The whole power supply can be then represented by a “real” voltage generator with an equivalent output resistance R V

. RFB resistor can be also designed according to the R

PROG

DROOP

Doc ID 14521 Rev 3 27/57

-------------

⋅=

DCR

DROOP

and a voltage value of

specifications as follow:

Droop thermal compensation L6716

12 Droop thermal compensation

Current sense element (DCR inductor) has a non-negligible temperature variation. As a consequence, the sensed current is subjected to a measurement error that causes the regulated output voltage to vary accordingly (when droop function is implemented).

To recover from this temperature related error, NTC resistor can be added into feedback compensation network, as shown in Figure 13.

The output voltage is then driven by the following relationship (neglecting the OFFSET voltage term):

OUT

PROGRFBIDROOP

⋅()–=

where R

is the equivalent feedback resistor and it depends on the temperature through

NTC resistor.

Considering the relationships between I

(, )[]V

OUTTIOUT

and the I

DROOP

⎛⎞

–=

PROGRFB

⎝⎠

, the output voltage results:

OUT

DCR T[]

----------------------

T[]

⋅⋅

OUT

where T is the temperature.

If the inductor temperature increases the DCR inductor increases and NTC resistor decreases. As a consequence the equivalent R

resistor decreases keeping constant the

output voltage respect to temperature variation.

NTC resistor must be placed as close as possible to the sense elements (phase inductor).

Figure 13. NTC connections for DC load line thermal compensation

PROG

GND DROP

RECOVERY

To GND_core

(Remote Sense)

FBG

To VCC_core

(Remote Sense)

FB3

NTC

FB2

DROOP

REF

ERROR AMPLIFIER

FB1

COMP

28/57 Doc ID 14521 Rev 3

L6716 Output current monitoring (IMON)

DCR

13 Output current monitoring (IMON)

The device sources from IMON pin a current proportional to the load current (the sourced current is a copy of Droop current).

Connect IMON pin through a R

resistor to remote ground (GND core) to implement a

IMON

load indicator, as shown in Figure 14.

As Intel VR11.1 specification required, on the IMON voltage as to be added a small positive offset to avoid under-estimation of the output load (due to elements accuracy).

The voltage across IMON pin is given by the following formula:

MONITORING

⋅

IMONROS

-----------------------------------

IMONROS

⋅ V

DROOP

REF

IMON

-----------------------------------

⋅+=

IMONROS

where:

-------------

DROOP

⋅=

OUT

The IMON pin voltage is clamped to 1.100 V max to preserve the CPU from excessive voltages as Intel VR11.1 specification required.

Figure 14. Output monitoring connection (left) and thermal compensation (right)

VREF = +3V3

IMON_OS

To CPU

To GND_core

(Remote Sense)

DROOP

IMON

VREF = +3V3

IMON

IMON_OS

To CPU

To GND_core

(Remote Sense)

NTC

DROOP

IMON

Current sense element (DCR inductor) has a non-negligible temperature variation. As a consequence, the sensed current is subjected to a measurement error that causes the monitoring voltage to vary accordingly.

To recover from this temperature related error, NTC resistor can be added into monitoring network, as shown in Figure 14.

The monitoring voltage is then driven by the following relationship (neglecting the offset term for simplicity):

MONITORING

where now the R

⋅

IMONROS

-----------------------------------

IMONROS

is the equivalent monitoring resistor and it depends on the

IMON

⋅

DROOP

⋅

IMONROS

-----------------------------------

IMONROS

DCR

-------------

⋅⋅==

OUT

temperature through NTC resistor.

Considering the relationships between I

MONITORINGTIOUT

(, )[]

and the I

DROOP

--------------------------------------------- -

IMON

, the voltage results:

OUT

⋅

DCR T[]

----------------------

⋅⋅=

OUT

where T is the temperature.

Doc ID 14521 Rev 3 29/57

Output current monitoring (IMON) L6716

If the inductor temperature increases the DCR inductor increases and NTC resistor decreases. As a consequence the equivalent R

resistor decreases keeping constant

IMON

the monitoring voltage respect to temperature variation. NTC resistor must be placed as close as possible to the sense elements (phase inductor).

30/57 Doc ID 14521 Rev 3

L6716 Load transient boost technology

14 Load transient boost technology

LTB Technology™ further enhances the performances of dual-edge asynchronous systems by reducing the system latencies and immediately turning ON all the phases to provide the correct amount of energy to the load.

By properly designing the LTB network, as well as the LTB gain, the undershoot and the ring-back can be minimized also optimizing the output capacitors count.

LTB Technology™ monitors the output voltage through a dedicated pin (see Figure 16) detecting load-transients with selected dV/dt, it cancels the interleaved phase-shift, turningon simultaneously all phases.

It then implements a parallel independent loop that (bypassing error amplifier (E/A) latencies) reacts to load-transients in very short time (<< 200 ns).

LTB Technology™ control loop is reported in Figure 15.

Figure 15. LTB Technology™ control loop

LTB Ramp

LTB

LT Detect

PWM_BOOST

d V

PWM

COMP

ZF(s) Z

Ref

FBCOMP

COMP

GND DROP

DROOP

Monitor

VSEN

RECOVERY

FBG

PROG

LT Detect

LTB

(s)

LTBGAIN

LTBCLTB

L/N

ESR

LTBGAIN

OUT

The LTB detector is able to detect output load transients by coupling the output voltage through an R

LT B

- C

network. After detecting a load transient, the LTB ramp is reset and

LT B

then compared with the COMP pin level. The resulting duty-cycle programmed is then ORed with the PWMx signal of each phase by-passing the main control loop. All the phases will then be turned-on together and the EA latencies results bypassed as well.

Short LTB pin to SGND to disable the LTB Technology™: in this condition the device works as a dual-edge asynchronous PWM controller.

Sensitivity of the load transient detector and the gain of the LTB ramp can be programmed in order to control precisely both the undershoot and the ring-back.

● Detector design. R

which is desired the controller to be sensitive as follow:

LT B

- C

LTB

is design according to the output voltage deviation dV

LT B

OUT

------------------= C

25μA

LTB

------------------------------------------------- -=

2π R

LTB

⋅⋅⋅

Doc ID 14521 Rev 3 31/57

OUT

Load transient boost technology L6716

● Gain design. Through the LTBGAIN pin it is possible to modify the slope of the LTB

Ramp in order to modulate the entity of the LTB response once the LT has been detected. In fact, the response depends on the board design and its parasites requiring different actions from the controller.

Connect R

LTBGAIN

to SGND using the following relationship in order to select the

default value (slope of the LTB ramp equal to 1/2 of the OSC ramp slope).

Where F

2 1240 10

LTBGAIN

is the selected switching frequency (in kHz).

kΩ[]

------------------------------------------------------------------- -=

⋅⋅

Fsw kHz[]200–

⎛⎞

------------------------------------------- -

⎝⎠

LTB Technology™ design tips.

● Decreases R

smaller dV

● Increase C

to increase the system sensitivity making the system sensitive to

LT B

OUT

to increase the system sensitivity making the system sensitive to higher

LT B

dV/dt.

● Decrease R

LTBGAIN

to decrease the width of the LTB pulse reducing the system ring-

back or vice versa.

Figure 16. LTB connections (left) and waveform (right)

LT B

OUT

To VCC_Cor

LTB

32/57 Doc ID 14521 Rev 3

L6716 Dynamic VID transitions

15 Dynamic VID transitions

The device is able to manage dynamic VID code changes that allow output voltage modification during normal device operation.

OVP and UVP signals are masked during every VID transition and they are re-activated after the transition finishes with a transition.

When changing dynamically the regulated voltage (D-VID), the system needs to charge or discharge the output capacitor accordingly. This means that an extra-current I be delivered, especially when increasing the output regulated voltage and it must be considered when setting the overcurrent threshold.

This current can be estimated using the following relationships:

15 µs (typ) delay to prevent from false triggering due to the

needs to

D-VID

OUT

DVID–

OUT

------------------

⋅=

VID

where d

is the selected DAC LSB (6.25 mV for VR11.1) and T

VOUT

is the time interval

VID

between each LSB transition (externally driven).

Overcoming the OC threshold during the dynamic VID causes the device to enter the constant current limitation slowing down the output voltage dV/dt also causing the failure in the D-VID test.

In order to avoid this situation the device automatically increases the OCP threshold to 150% of the selected OCP threshold during every VID transition (adding an extra

15 µs of

delay).

If the DVID (dynamic VID change) happens during low power state (PSI low), the device turns on all the N phases in order to follow the DVID change reducing the over/under shoot of the output voltage.

L6716 checks for VID code modifications (See Figure 17) on the rising edge of an internal additional DVID-clock and waits for a confirmation on the following falling edge. Once the new code is stable, on the next rising edge, the reference starts stepping up or down in LSB increments every VID-clock cycle until the new VID code is reached. During the transition, VID code changes are ignored; the device re-starts monitoring VID after the transition has finished on the next rising edge available. VID-clock frequency (F

) is in the range of 1.8

DVI D

MHz to assure compatibility with the specifications.

Note: If the new VID code is more than 1 LSB different from the previous, the device will execute

the transition stepping the reference with the DVID-clock frequency F

until the new code

DVI D

has reached: for this reason it is recommended to carefully control the VID change rate in order to carefully control the slope of the output voltage.

Doc ID 14521 Rev 3 33/57

Dynamic VID transitions L6716

Figure 17. Dynamics VID transitions

VID Sampled

VID Clock

VID Sampled

VID Stable

VID Sampled

Ref Moved (1)

Ref Moved (2)

Ref Moved (3)

VID Sampled

Ref Moved (4)

VID Sampled

Ref Moved (1)

VID Sampled

VID Stable

Ref Moved (1)

VID Sampled

VID Stable

Ref Moved (1)

VID Sampled

VID Stable

VID Sampled

Ref Moved (1)

VID Sampled

VID Stable

VID Sampled

VID [0,7]

Int. Reference

DVID

out

x 4 Step VID Transition

Vout Slope Controlled by internal

DVID-Clock Oscillator

VID

4 x 1 Step VID Transition

Vout Slope Controlled by external

driving circuit (T

)

VID

34/57 Doc ID 14521 Rev 3

L6716 Enable and disable

16 Enable and disable

L6716 has three different supplies: VCC pin to supply the internal control logic, VCCDR to supply the low side drivers and BOOTx to supply the high side drivers.

If the voltage at pin VCC is not above the turn on threshold specified in the Section 4:

Electrical characteristics on page 14, the device is shut down: all drivers keep the

MOSFETs off to show high impedance to the load.

Once the device is correctly supplied, proper operation is assured and the device can be driven by the OUTEN pin to control the power sequencing. Setting the pin free, the device implements a soft-start up to the programmed voltage. Shorting the pin to SGND, it resets the device (SS_END is shorted to SGND in this condition) from any latched condition and also disables the device keeping all the MOSFET turned off to show high impedance to the load.

Doc ID 14521 Rev 3 35/57

Soft-start L6716

17 Soft-start

L6716 implements a soft-start to smoothly charge the output filter avoiding high in-rush currents to be required to the input power supply. The device increases the reference from zero up to the programmed value and the output voltage increases accordingly with closed loop regulation.

The device implements soft-start only when all the power supplies are above their own turnon thresholds and the OUTEN pin is set free.

At the end of the digital soft-start, SS_END signal is set free.

Protections are active during soft-start: under voltage is enabled when the reference voltage reaches 0.6 V while overvoltage is always enabled.

Note: If the PSI is already low during the start-up, the device implements the soft-start using the N

phases selected trough PWM4 pin. When the soft-start is finished the device turns OFF some phases in according to the PSI strategy.

Figure 18. Soft-start

OUTEN

OUT

SS_END

OVP

TD1TD2TD3T

Once L6716 receives all the correct supplies and enables, it initiates the Soft-Start phase with a T V - 19 mV) in T

=1.5 ms (typ) delay. After that, the reference ramps up to V

according to the SSOSC settings and waits for T

= 1.081 V (1.100

BOOT

= 200 μsec (typ) during

which the device reads the VID lines. Output voltage will then ramps up to the programmed value in T

with the same slope as before (see Figure 18).

SSOSC defines the frequency of an internal additional soft-start-oscillator used to step the reference from zero up to the programmed value; this oscillator is independent from the main oscillator whose frequency is programmed through the OSC pin.

The current flowing from SSOSC pin before the end of soft-start is used to program the desiderated soft-start time (T

After that the soft-start is finished the current flowing from SSOSC pin is used to program the maximum LTB switching frequency (F

In the Figure 19 is shown the SSOSC connection in order to select both parameter (T F

) in independent way.

LIMIT

In particular, it allows to precisely programming the start-up time up to V

LIMIT

and

(TD2) since it

BOOT

is a fixed voltage independent by the programmed VID. Total soft-start time dependence on the programmed VID results (see Figure 20).

36/57 Doc ID 14521 Rev 3

L6716 Soft-start

Note: If during TD3 the programmed VID selects an output voltage lower than V

voltage will ramp to the programmed voltage starting from V

BOOT

Figure 19. SSOSC connection

SSOSCSS_END

SSOSC

Pull-Up

(1.2V)

to SSEND Logic

SSOSC

TSSμs[] 200 μs[]

Pull-Up

(1k)

kΩ[]TD2μs[]40 10

⎧

SSOSC

---------------------------------- -

⎪ ⎪

40 10

⎨ ⎪ ⎪ ⎩

⋅

SSOSC

---------------------------------- -

40 10

⋅

FLIMIT

Rb(10k)

Soft Start time and FLIMIT selected in indipendent way.

⋅⋅ ⋅=

kΩ[]

---------------------------------------------- -

⋅⋅if V

3–

1.24 V

kΩ[]

---------------------------------------------- -

3–

1.24 V

3–

1.24

DIODE

1.24

DIODE

Soft Start time depends on selected FLIMIT.

1.24 V

---------------------------------------------- -

V[]–

DIODE

1.24

------------------

BOOT

------------------+⋅⋅if VSSV

BOOT

FLIM_SS

V[]–

, the output

BOOT

>()

SSVBOOT

<()

BOOT

where T

is the time spent to reach the programmed voltage VSS and R

SSOSC

the resistor

connected between SSOSC and SSEND (through a signal diode) in kΩ.

Figure 20. Soft-start time (T

) when using R

, diode versus SSEND

SSOSC

Use the following relationship to select the maximum LTB switching frequency:

FLIMIT

where F

has to be higher than the FSW switching frequency.

LIMIT

kΩ[]

---------------------------------

LIMIT

kHz[]

2.11 10

⋅

1.24 V

---------------------------------------------- -

⋅=

1.24

BJT

V[]–

Doc ID 14521 Rev 3 37/57

Soft-start L6716

Note: Connecting SSOSC pin to SGND through only the R

Figure 19), the Soft-start time depends on the F

LIMIT

In this case use the following relationship to select F start time:

2.11 104⋅

---------------------------------=

kΩ[]

LIMIT

5.275 105⋅

---------------------------------=

LIMIT

when using R

Figure 21. Soft-start time (T

FLIM SS–

TD2μs[]

) vs F

LIMIT

FLIM_SS

resistor (blue one network in

selected.

and as a consequence the soft-

LIMIT

kHz[]

FLIM_SS

resistor versus SGND

17.1 Low-side-less startup

In order to avoid any kind of negative undershoot on the load side during start-up, L6716 performs a special sequence in enabling LS driver to switch: during the soft-start phase, the LS driver results disabled (LS=OFF) until the HS starts to switch. This avoid the dangerous negative spike on the output voltage that can happen if starting over a pre-biased output (see Figure 22).

This particular feature of the device masks the LS turn-on only from the control loop point of view: protections are still allowed to turn-ON the LS MOSFET in case of overvoltage if needed.

Figure 22. Low-side-less start-up comparison.with LS-less start-up

Without LS-Less start-up

OUT

LGATE

With LS-Less start-up

OUT

LGATE

38/57 Doc ID 14521 Rev 3

L6716 Output voltage monitor and protections

18 Output voltage monitor and protections

L6716 monitors through pin VSEN the regulated voltage in order to manage the OVP and UVP conditions. Protections are active also during soft-start (Section 17: Soft-start on

page 36) while they are masked during D-VID transitions with an additional 67 µs delay after

the transition has finished to avoid false triggering.

18.1 Undervoltage

If the output voltage monitored by VSEN drops more than 600 mV (typ) below the programmed reference for more than one clock period, the L6716:

● Permanently turns OFF all the MOSFETs (PWM4 is forced in high impedance when

external driver is used)

● Drives the OSC/ FAULT pin high (3.3 V typ).

● Power supply or OUTEN pin cycling is required to restart operations.

18.2 Preliminary overvoltage

To provide a protection while VCC is below the UVLO

threshold is fundamental to avoid

VCC

damage to the CPU in case of failed HS MOSFETs. In fact, since the device is supplied from the 12 V bus, it is basically “blind” for any voltage below the turn-on threshold (UVLO

VCC

). In order to give full protection to the load, a preliminary-OVP protection is provided while VCC is within UVLO

and UVLO

VCC

Pre-OVP

This protection turns-on the low side MOSFETs as long as the VSEN pin voltage is greater than 1.800 V with a 350 mV hysteresis. When set, the protection drives the LS MOSFET with a gate-to-source voltage depending on the voltage applied to VCC. This protection depends also on the OUTEN pin status as detailed in Figure 23.

A simple way to provide protection to the output in all conditions when the device is OFF (then avoiding the unprotected red region in Figure 23-Left) consists in supplying the controller through the 5 V

bus as shown in Figure 23-Right: 5 VSB is always present

before +12 V and, in case of HS short, the LS MOSFET is driven with 5 V assuring a reliable protection of the load.

Figure 23. Output voltage protections and typical principle connections

(OUTEN = 0)

Preliminary OVP

VCC

OVP

VSEN Monitored

Preliminary OVP Enabled

VSEN Monitored

No Protection

UVLO

(OUTEN = 1)

Programmable OVP

VSEN Monitored

Provided

+5V

+12V

BAT54C

10Ω

2.2Ω

1μF

2x1μF

VCC

VCCDR

Note: The device turns ON only LS MOSFETs of Phase1-Phase3 if the Pre-OVP is detected

before that VCC is higher than UVLO higher than UVLO

VCC

Doc ID 14521 Rev 3 39/57

. (The device reads PWM4 information if the VCC is

VCC

Output voltage monitor and protections L6716

18.3 Overvoltage and programmable OVP

Once VCC crosses the turn-ON threshold and the device is enabled (OUTEN = 1), L6716 provides an overvoltage protection: when the voltage sensed by VSEN overcomes the OVP threshold (OVP

● Permanently turns OFF all the high-side MOSFETs.

● Permanently turns ON all the low-side MOSFETs (PWM4 is forced low when external

driver is used) in order to protect the load.

● Drives the OSC/ FAULT pin high (3.3 V typ).

● Power supply or OUTEN pin cycling is required to restart operations.

The OVP threshold can be also programmed through the OVP pin: leaving the pin floating, it is internally pulled-up and the OVP threshold is set to VID+150 mV (typ).

), the controller:

Connecting the OVP pin to SGND through a resistor R voltage present at the pin. Since the OVP pin sources a constant I

, the OVP threshold becomes the

OVP

= 20 µA current (see

OVP

Ta bl e 5), the programmed voltage becomes:

OVP

THROVP

20μA⋅= R

OVP

------------------- -=⇒

20μA

Filter OVP pin with 100 pF (max) vs. SGND.

Table 9. Overvoltage protection threshold

OVP pin Thresholds OVP threshold

Floating Tracking OVP

to SGND Fixed OVP

OVP

= VID + 175 mV (typ)

= R

* 20 μA (typ)

OVP

Overvoltage protections is always active during the soft-start, as shown in the following picture:

Figure 24. OVP threshold during soft-start for tracking (left) and fixed (right) mode

OUTEN

OUT

OUTEN

OUT

SS_END

OVP

1.240V

Note: When VR10/VR11 table is selected (OVP pin to SGND) the OVP threshold becomes 1.800

V (typ) fixed.

VID+175mV

SS_END

OVP

ROVP * 20uA

40/57 Doc ID 14521 Rev 3

L6716 Output voltage monitor and protections

18.4 Overcurrent protection

The device limits the peak the inductor current entering in constant current until setting UVP as below explained.

The overcurrent threshold has to be programmed, by designing the R

OCSET

resistors as shown in the Figure 25, to a safe value, in order to be sure that the device doesn't enter OCP during normal operation of the device. This value must take into consideration also the extra current needed during the Dynamic VID Transition I

(See “Dynamic VID

D-VID

transitions” Section for details):

OCP

IOUT

The device detects an overcurrent when the I

IOUT

INFOx

MAX

DVID–

overcome the threshold I

OCTH

externally

programmable through OCSET pin.

OCTH

INFOx

OCP

OCSET

--------------------- -

OCSET

DCR

-------------

1.240V typ()

-------------------------------- -==

OCSET

OCP

⎛⎞

OUT

-----------------------

⋅=

⎜⎟

⎝⎠

ΔIL

-------- -+

where ΔIL is the inductor ripple current (peak-to-peak).

Since the device always senses the current across the inductor, the I

crossing will

OCTH

happen during the HS conduction time: as a consequence of OCP detection, the device will turn OFF the HS MOSFET and turns ON the LSMOSFET of that phase until I

INFOx

re-cross the threshold or until the next clock cycle. This implies that the device limits the peak of the inductor current.

In any case, the inductor current won't overcome the I

value and this will represent the

OCPx

maximum peak value to consider in the OC design.

The device works in constant-current, and the output voltage decreases as the load increase, until the output voltage reaches the UVP threshold. When this threshold is crossed, all MOSFETs are turned off and the device stops working. Cycle the power supply or the OUTEN pin to restart operation.

Figure 25. Overcurrent protection connection

OCSET

=1.240V (

Doc ID 14521 Rev 3 41/57

TYP)

OCSET

OCTH

OCSET/PSI_A

Output voltage monitor and protections L6716

Note: In order to avoid the OCP intervention during the DVID, the device automatically increases

the OCP threshold to 150% of the selected OCP threshold during every VID transition (adding an extra

15 µs of delay).

Since the device reads the current information across inductor DCR, the process spread and temperature variations of these sensing elements has to be considered. Also the programmable threshold spread (I spread, See “Electrical characteristics” Section) has to be considered for the R

current spread as a consequence of V

OCTH

OCSET

design:

OCSET

The OCSET pin is also used to select the number of phases when PSI mode is asserted.

To select the desired OCP threshold and number of phase during PSI mode, refer to the following table.

Table 10. # phases when PSI is asserted

# phase

normal mode

(N)

# phase

PSI mode

(N_PSI)

1 PHASE1

Phases

enabled

PHASE1 PHASE3

OCSET

⎛⎞

------------------------------ -

⋅

⎝⎠

----------------------------------------------------------------------------------------------------------------------- -=

DCR MAX )()

---------------------------------- -

OCSET

----------------------------------------------------------------------------------------------------------------------- -=

DCR MAX )()

---------------------------------- -

----------------------------------------------------------------------------------------- -=

DCR MAX()

--------------------------------

OCSET

MIN()

OCP()

OUT

----------------------------------------------------------------------------------------- -=

DCR MAX()

--------------------------------

----------------------------------------------------------------------------------------- -=

DCR MAX()

--------------------------------

ΔIL

-------- -+

OCSET

OUT

⎛⎞

------------------------------ -

⋅ 77μA+

⎝⎠

OCSET

OUT

⎛⎞

------------------------------ -

⋅ 77μA+

⎝⎠

MIN()

OCP()

ΔIL

-------- -+

MIN()

OCP()

OUT

⎛⎞

------------------------------ -

⋅

⎝⎠

ΔIL

-------- -+

MIN()

OCP()

OUT

⎛⎞

------------------------------ -

⋅

⎝⎠

ΔIL

-------- -+

MIN()

OCP()

ΔIL

-------- -+

1 PHASE1

2N. A.

42/57 Doc ID 14521 Rev 3

OCSET

----------------------------------------------------------------------------------------- -=

DCR MAX()

--------------------------------

OCSET

MIN()

OCP()

OUT

⎛⎞

------------------------------ -

⋅

⎝⎠

ΔIL

-------- -+

Do not use this condition (Not applicable)

L6716 Output voltage monitor and protections

DROOP

18.5 Feedback disconnection

L6716 allows to protect the load from dangerous overvoltage also in case of feedback disconnection. The device is able to recognize both FB pin and FBG pin disconnections, as shown in the Figure 26.

When VSEN pin is more than 500 mV higher then VPROG, the device recognize a FBG disconnections. Viceversa, when CS1- is more than 700 mV higher then VSEN, the device recognize a FB disconnection.

In both of the previous condition the device stops switching with all the MOSFETs permanently OFF and drives high the OSC/FAULT pin. The condition is latched until VCC or OUTEN cycled.

Figure 26. Feedback disconnection

500mV

PROG

GND DROP

RECOVERY

FBG

To GND_core

(Remote Sense)

FBG

DISCONNECTED

To VCC_core

(Remote Sense)

VSEN

REF

700mV

AMPLIFIER

ERROR

COMP

PHASE1

CS1+ CS1-

DISCONNECTED

DCR1

OUT

Doc ID 14521 Rev 3 43/57

Low power state management and PSI# L6716

19 Low power state management and PSI#

The device is able to manage the low power state mode: when the PSI is driven low (PSI is active low) the device turns OFF some phase in order to increase the system efficiency.

The number of phases active when low power state is active depends on the OCSET/PSI_A pin (trough R

Table 11: # phases when PSI is asserted

versus SGND) as shown in the following table:

OCSET

# phase

normal mode

(N)

# phase

PSI mode

(N_PSI)

Phases

enabled

1 PHASE1

PHASE1 PHASE3

1 PHASE1

PHASE1 PHASE3

1 PHASE1

2N. A.

OCSET

----------------------------------------------------------------------------------------------------------------------- -=

DCR MAX )()

---------------------------------- -

OCSET

----------------------------------------------------------------------------------------------------------------------- -=

DCR MAX )()

---------------------------------- -

OCSET

⎛⎞

⋅ 77μA+

----------------------------------------------------------------------------------------- -=

DCR MAX()

--------------------------------

----------------------------------------------------------------------------------------- -=

DCR MAX()

--------------------------------

----------------------------------------------------------------------------------------- -=

DCR MAX()

--------------------------------

⎝⎠

OCSET

⎛⎞

------------------------------ -

⋅ 77μA+

⎝⎠

OCSET

MIN()

OCSET

OCP()

OUT

------------------------------ -

MIN()

OUT

⎛⎞

------------------------------ -

⋅

⎝⎠

MIN()

OUT

⎛⎞

------------------------------ -

⋅

⎝⎠

MIN()

OCP()

OUT

MIN()

OUT

⎛⎞

------------------------------ -

⋅

⎝⎠

Do not use this condition (Not applicable)

ΔIL

-------- -+

OCP()

ΔIL

-------- -+

ΔIL

-------- -+

ΔIL

-------- -+

ΔIL

-------- -+

If DVID (dynamic VID change) happens during low power state (PSI low), the device turns on all the N phases in order to follow the DVID change reducing the over/under shoot of the output voltage.

Note: If the PSI is already low during the start-up, the device implements the soft-start using the N

phases selected trough PWM4 pin. When the soft-start is finished the device turns OFF some phases in according to the PSI strategy.

44/57 Doc ID 14521 Rev 3

L6716 Oscillator

20 Oscillator

L6716 embeds two-to-four phase oscillator with optimized phase-shift (180º/120º/90º phase-shift) in order to reduce the input rms current and optimize the output filter definition.

The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an internal capacitor. The switching frequency for each channel, F load side results in being multiplied by N (number of phases).

The current delivered to the oscillator is typically 25 μA (corresponding to the free running frequency F between the OSC/FAULT pin and SGND or VCC (or a fixed voltage greater than 1.24 V). Since the OSC/FAULT pin is fixed at 1.240 V, the frequency is varied proportionally to the current sunk (forced) from (into) the pin considering the internal gain of 9.1 kHz/μA.

, is internally fixed at 200 kHz so that the resulting switching frequency at the

= 200 kHz) and it may be varied using an external resistor (R

) connected

OSC

In particular connecting R pin), while connecting R

to SGND the frequency is increased (current is sunk from the

OSC

to VCC = 12 V the frequency is reduced (current is forced into

OSC

the pin), according the following relationships:

vs. SGND

OSC

vs. +12 V

----------------------------

12V 1.240V–

----------------------------------- -

200 kHz()

1.240V

OSC

kΩ()

kHz

---------- -

9.1

⋅+ 200 kHz()

μA

kHz

---------- -

9.1

⋅– 200 kHz()

μA

11.284 103⋅

------------------------------- -

kΩ()

OSC

⋅

9.7916 10

------------------------------- -– R R

OSC

kΩ()

OSC

kΩ()⇒+

kΩ()⇒

kHz()200 kHz()–

9.7916 104⋅

----------------------------------------------------------- -== =kΩ[] 200 kHz()F

11.284 103⋅

----------------------------------------------------------- -== =kΩ[]

Maximum programmable switching frequency per phase must be limited to 1 MHz to avoid minimum Ton limitation. Anyway, device power dissipation must be checked prior to design high switching frequency systems.

Figure 27. R

vs. switching frequency

OSC

kHz()–

Doc ID 14521 Rev 3 45/57

Driver section L6716

21 Driver section

The integrated high-current drivers allow using different types of power MOS (also multiple MOS to reduce the equivalent R

The drivers for the high-side MOSFETs use BOOTx pins for supply and PHASEx pins for return. The drivers for the low-side MOSFETs use VCCDR pin for supply and PGND pin for return. A minimum voltage at VCCDR pin is required to start operations of the device.

The controller embodies a sophisticated anti-shoot-through system to minimize low side body diode conduction time maintaining good efficiency saving the use of Schottky diodes: when the high-side MOSFET turns off, the voltage on its source begins to fall; when the voltage reaches 2 V, the low-side MOSFET gate drive is suddenly applied. When the lowside MOSFET turns off, the voltage at LGATEx pin is sensed. When it drops below 1 V, the high-side MOSFET gate drive is suddenly applied.

If the current flowing in the inductor is negative, the source of high-side MOSFET will never drop. To allow the turning on of the low-side MOSFET even in this case, a watchdog controller is enabled: if the source of the high-side MOSFET doesn't drop, the low side MOSFET is switched on so allowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is negative.

The BOOTx and VCCDR pins are separated from IC's power supply (VCC pin) as well as signal ground (SGND pin) and power ground (PGND pin) in order to maximize the switching noise immunity.

), maintaining fast switching transition.

ds(ON)

46/57 Doc ID 14521 Rev 3

L6716 System control loop compensation

22 System control loop compensation

The control loop is composed by the current sharing control loop (see Figure 9) and the average current mode control loop. Each loop gives, with a proper gain, the correction to the PWM in order to minimize the error in its regulation: the current sharing control loop equalize the currents in the inductors while the average current mode control loop fixes the output voltage equal to the reference programmed by VID. Figure 28 shows the block diagram of the system control loop.

The system control loop is reported in Figure 29. The current information I the FB pin flows into R

implementing the dependence of the output voltage from the read

DROOP

sourced by

current.

Figure 28. Main control loop

REF

ZF(s) ZFB(s)

OUTROUT

DROOP

INFO2,IINFO4

2 / 5

CURRENT SHARING

DUTY CYCLE

CORRECTION

only applied when using 3-PHASE or 4-PHASE Operation)

I I I

INFO1

INFO2

INFO3

INFO4

PWM4

PWM3

PWM2

PWM1

3 / 5

ERROR AMPLIFIER

COMP FB

The system can be modeled with an equivalent single phase converter which only difference is the equivalent inductor L/N (where each phase has an L inductor). The control loop gain results (obtained opening the loop after the COMP pin):

LOOP

s()

PWM Z

-------------------------------------------------------------------------------------------------------------------–=

s() ZLs()+[]

s() R

-------------- 1

DROOPZP

s()

As()

s()+()⋅⋅

⎛⎞ ⎝⎠

----------- -+

As()

⋅+⋅

Where:

DCR is the inductor parasitic resistance;

is the equivalent output resistance determined by the droop function;

DCR

-------------

DROOP

(s) is the impedance resulting by the parallel of the output capacitor (and its ESR) and the

applied load R

⋅=

ZF(s) is the compensation network impedance

(s) is the parallel of the N inductor impedance

A(s) is the error amplifier gain

Doc ID 14521 Rev 3 47/57

System control loop compensation L6716

is the PWM transfer function where ΔV

PWM

is the oscillator ramp amplitude and has a typical

OSC

-- -

⋅=

------------------ -

ΔV

OSC

value of 1.5 V.

Removing the dependence from the error amplifier gain, so assuming this gain high enough, and with further simplifications, the control loop gain results:

ROR

LOOP

s()

--- -

----------------------

⋅⋅⋅ ⋅–=

ΔV

OSC

ZFs()

---------------

DROOP

------------------------------------------- -

-------+

1sCOR

--------------------------------------------------------------------------------------------------------------------------------------------

s2C

⋅⋅ s

-----

------------------- COESR⋅ C

N R

⋅

DROOP

//ROESR+()⋅⋅+

-------

⋅++ 1+⋅+

The system control loop gain (see Figure 28) is designed in order to obtain a high DC gain to minimize static error and to cross the 0 dB axes with a constant -20 dB/dec slope with the desired crossover frequency ω

. Neglecting the effect of ZF(s), the transfer function has one

zero and two poles; both the poles are fixed once the output filter is designed (LC filter resonance ω

) and the zero (ω

) is fixed by ESR and the Droop resistance.

ESR

Figure 29. Equivalent control loop block diagram (left) and bode diagram (right)

d V

L / N

PWM

DROOP

VREF

OUT

ESR

OUT

(s)

LOOP

FB COMP

ZF(s)

(s)

To obtain the desired shape an R implementation. A zero at ω

VSEN

FBRTN

series network is considered for the ZF(s)

F-CF

= 1/RFCF is then introduced together with an integrator. This

integrator minimizes the static error while placing the zero ω

RF[dB]

ESR

in correspondence with the L-

(s)

C resonance assures a simple -20 dB/dec shape of the gain.

In fact, considering the usual value for the output filter, the LC resonance results to be at frequency lower than the above reported zero.

Compensation network can be simply designed placing ω over frequency ω

1/10

of the switching frequency FSW):

as desired obtaining (always considering that ωT might be not higher than

RFBΔV

⋅

--------------------------------- -

OSC

⋅⋅ ⋅= C

------------------------------------------------------- -

-- -

DROOP

= ωLC and imposing the cross-

--- -

⋅

-------------------- -=

ESR+()⋅

Moreover, it is suggested to filter the high frequency ripple on the COMP pin adding also a capacitor between COMP pin and FB pin (it does not change the system bandwidth):

----------------------------------------------- -=

2 π R⋅

⋅⋅⋅

48/57 Doc ID 14521 Rev 3

L6716 Tolerance band (TOB) definition

23 Tolerance band (TOB) definition

Output voltage load-line varies considering component process variation, system temperature extremes, and age degradation limits. Moreover, individual tolerance of the components also varies among designs: it is then possible to define a manufacturing tolerance band (TOB nominal load line characteristic.

) that defines the possible output voltage spread across the

Manuf

TOB

can be sliced into different three main categories: controller tolerance, external

Manuf

current sense circuit tolerance and time constant matching error tolerance. All these parameters can be composed thanks to the RSS analysis so that the manufacturing variation on TOB results to be:

TOB

Manuf

Output voltage ripple (V

P=VPP

TOB

Controller

/2) and temperature measurement error (VTC) must be added

to the manufacturing TOB in order to get the system tolerance band as follow:

TOB TOB

All the component spreads and variations are usually considered at 3σ. Here follows an explanation on how to calculate these parameters for a reference L6716 application.

23.1 Controller tolerance (TOB

It can be further sliced as follow:

Reference tolerance. L6716 is trimmed during the production stage to ensure the output voltage to be within k device automatically adds a -19 mV offset avoiding the use of any external component. This offset is already included during the trimming process in order to avoid the use of any external circuit to generate this offsets and, moreover, avoiding the introduction of any further error to be considered in the TOB calculation.

= ±0.5% over temperature and line variations. In addition, the

VID

TOB

++=

ManufVPVTC

Controller

2 CurrSense

++=

)

TOB

2 TCMatching

Current reading circuit. The device reads the current flowing across the inductor DCR by using its dedicated differential inputs. The current sourced by the VRD is then reproduced and sourced from the FB pin scaled down by a proper designed gain as follow:

DCR

DROOP

This current multiplied by the R

resistor connected from FB pin vs. the load allows

programming the droop function according to the selected DCR/Rg gain and R

-------------

⋅=

OUT

resistor.

Deviations in the current sourced due to errors in the current reading, impacts on the output voltage depending on the size of R stage in order to guarantee a maximum deviation of k

resistor. The device is trimmed during the production

= ± 3 μA from the nominal value.

IFB

Controller tolerance results then to be:

TOB

Controller

VID 19mV–()k

Doc ID 14521 Rev 3 49/57

⋅[]

VID

IDROOPRFB

⋅()

Tolerance band (TOB) definition L6716

23.2 External current sense circuit tolerance (TOB

It can be further sliced as follow:

Inductor DCR tolerance (k voltage since the device reads a current that is different from the real current flowing into the sense element. As a results, the controller will source a I nominal. The results will be an AVP different from the nominal in the same percentage as the DCR is different from the nominal. Since all the sense elements results to be in parallel, the error related to the inductor DCR has to be divided by the number of phases (N).

Trans-conductance resistors tolerance (k current reading circuit gain and so impacts on the output voltage. The results will be an AVP different from the nominal in the same percentage as the Rg is different from the nominal. Since all the sense elements results to be in parallel, and so the three current reading circuits, the error related to the Rg resistors has to be divided by the number of phases (N).

NTC Initial Accuracy (k used for the thermal compensation impacts on the AVP in the same percentage as before. In addition, the benefit of the division by the number of phases N cannot be applied in this case.

NTC temperature accuracy (k output voltage positioning. The impact is bigger as big is the temperature variation from room to hot (ΔT).

All these parameters impacts the AVP, so they must be weighted on the maximum voltage swing from zero load up to the maximum electrical current (V current sense circuit results:

). Variations in the inductor DCR impacts on the output

DCR

current different from the

DROOP

). Variations in the Rg resistors impacts in the

). Variations in the NTC nominal value at room temperature

NTC_0

). NTC variations from room to hot also impacts on the

NTC

). Total error from external

AVP

CurrSense

)

TOB

CurrSense

2 AVP

DCR

------------- -

--------- k

++ +⋅=

NTC0

23.3 Time constant matching error tolerance (TOB

Inductance and capacitance tolerance (kL, kC). Variations in the inductance value and in the value of the capacitor used for the time constant matching causes over/under shoots after a load transient appliance. This impacts the output voltage and then the TOB. Since all the sense elements results to be in parallel, the error related to the time constant mismatch has to be divided by the number of phases (N).

Capacitance temperature variations (k also vary with temperature (ΔT

) impacting on the output voltage transients ad before. Since

all the sense elements results to be in parallel, the error related to the time constant mismatch has to be divided by the number of phases (N).

All these parameters impact the dynamic AVP, so they must be weighted on the maximum dynamic voltage swing (I

). Total error due to time constant mismatch results:

dyn

TOB

TCMatching

). The capacitor used for time constant matching

AVPDyn

--------------------------------------------------------- -

⋅=

αΔTk

⋅⋅

⎛⎞

--------------------------------- -

⎝⎠

DCR

NTC

TCMatching

kCtΔTC⋅()

)

50/57 Doc ID 14521 Rev 3

L6716 Tolerance band (TOB) definition

23.4 Temperature measurement error (VTC)

Error in the measured temperature (for thermal compensation) impacts on the output regulated voltage since the correction form the compensation circuit is not what required to keep the output voltage flat.

The measurement error (ε

) must be multiplied by the copper temp coefficient (α) and

Te m p

compared with the sensing resistance (R follow:

): this percentage affects the AVP voltage as

SENSE

αε

⋅

Temp

----------------------- -

SENSE

⋅=

AVP

Doc ID 14521 Rev 3 51/57

Layout guidelines L6716

24 Layout guidelines

Since the device manages control functions and high-current drivers, layout is one of the most important things to consider when designing such high current applications. A good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing radiation and a proper connection between signal and power ground can optimize the performance of the control loops.

Two kind of critical components and connections have to be considered when layouting a VRM based on L6716: power components and connections and small signal components connections.

24.1 Power components and connections

These are the components and connections where switching and high continuous current flows from the input to the load. The first priority when placing components has to be reserved to this power section, minimizing the length of each connection and loop as much as possible. To minimize noise and voltage spikes (EMI and losses) these interconnections must be a part of a power plane and anyway realized by wide and thick copper traces: loop must be anyway minimized. The critical components, i.e. the power transistors, must be close one to the other. The use of multi-layer printed circuit board is recommended.

Figure 30 shows the details of the power connections involved and the current loops. The

input capacitance (C

), or at least a portion of the total capacitance needed, has to be

placed close to the power section in order to eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be connected near the HS drain.

Figure 30. Power connections and related connections layout (same for all phases)

UGATEx

PHASEx

LGATEx

PGND

LOAD

To limit C

BOOTx

PHASEx

VCC

SGND

Extra-Charge

BOOT

+Vcc

Note: Boot capacitor extra charge. Systems that do not use Schottky diodes might show big

negative spikes on the phase pin. This spike can be limited as well as the positive spike but has an additional consequence: it causes the bootstrap capacitor to be over-charged. This extra-charge can cause, in the worst case condition of maximum input voltage and during particular transients, that boot-to-phase voltage overcomes the abs. max. ratings also causing device failures. It is then suggested in this cases to limit this extra-charge by adding a small resistor in series to the boot diode (one resistor can be enough for all the three diodes if placed upstream the diode anode, see Figure 30) and by using standard and lowcapacitive diodes.

LOAD

Use proper VIAs number when power traces have to move between different planes on the PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the

52/57 Doc ID 14521 Rev 3

L6716 Layout guidelines

same high-current trace on more than one PCB layer will reduce the parasitic resistance associated to that connection.

Connect output bulk capacitor as near as possible to the load, minimizing parasitic inductance and resistance associated to the copper trace also adding extra decoupling capacitors along the way to the load when this results in being far from the bulk capacitor bank.

Gate traces must be sized according to the driver RMS current delivered to the power MOSFET. The device robustness allows managing applications with the power section far from the controller without losing performances. External gate resistors help the device to dissipate power resulting in a general cooling of the device. When driving multiple MOSFETs in parallel, it is suggested to use one resistor for each MOSFET.

Device exposed pad is the power ground pin (LS drivers return path) as a consequence it has be tied to ground plane layer trough the lowest impedance connection. Connect it to the power ground plane using 5.2 x 5.2 mm square area on the PCB and with sixteen vias (uniformly distributed) to improve electrical and thermal conductivity, as shown in the

Figure 31.

Figure 31. Exposed pad VIAs number/location to ground plane

24.2 Small signal components and connections

These are small signal components and connections to critical nodes of the application as well as bypass capacitors for the device supply (see Figure 30). Locate the bypass capacitor (VCC and Bootstrap capacitor) close to the device and refer sensible components such as frequency set-up resistor R connect SGND to PGND plane in a single point to avoid that drops due to the high current delivered causes errors in the device behavior.

Remote sensing connection must be routed as parallel nets from the FBG/VSEN pins to the load in order to avoid the pick-up of any common mode noise. Connecting these pins in points far from the load will cause a non-optimum load regulation, increasing output tolerance.

Locate current reading components close to the device. The PCB traces connecting the reading point must use dedicated nets, routed as parallel traces in order to avoid the pick-up of any common mode noise. It's also important to avoid any offset in the measurement and, to get a better precision, to connect the traces as close as possible to the sensing elements. Small filtering capacitor can be added, near the controller, between V CSx- line to allow higher layout flexibility.

, overcurrent resistor R

OSC

Doc ID 14521 Rev 3 53/57

. Star grounding is suggested:

OCSET

and SGND, on the

OUT

Embedding L6716 - based VR L6716

25 Embedding L6716 - based VR

When embedding the VRD into the application, additional care must be taken since the whole VRD is a switching DC/DC regulator and the most common system in which it has to work is a digital system such as MB or similar. In fact, latest MB has become faster and powerful: high speed data bus are more and more common and switching-induced noise produced by the VRD can affect data integrity if not following additional layout guidelines. Few easy points must be considered mainly when routing traces in which high switching currents flow (high switching currents cause voltage spikes across the stray inductance of the trace causing noise that can affect the near traces):

Keep safe guarding distance between high current switching VRD traces and data buses, especially if high-speed data bus to minimize noise coupling.

Keep safe guard distance or filter properly when routing bias traces for I/O sub-systems that must walk near the VRD.

Possible causes of noise can be located in the PHASE connections, MOSFET gate drive and Input voltage path (from input bulk capacitors and HS drain). Also PGND connections must be considered if not insisting on a power ground plane. These connections must be carefully kept far away from noise-sensitive data bus.

Since the generated noise is mainly due to the switching activity of the VRM, noise emissions depend on how fast the current switches. To reduce noise emission levels, it is also possible, in addition to the previous guidelines, to reduce the current slope by properly tuning the HS gate resistor and the PHASE snubber network.

54/57 Doc ID 14521 Rev 3

L6716 Package mechanical data

26 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK

packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

Figure 32. VFQFPN-48 mechanical data and package dimensions

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

A 0.800 0.9 00 1.000 31.50 39.37

A3 0.200

b 0.180 0.250 0.300 7.087 9.843 11.81

D 6.900 7.000 7.100 271.6 275.6 279.5

D2 5.050 5.150 5.250 198.8 .202.7 206.7

E 6.900 7.0 00 7.100

E2 5.050 5.150 5.250

e 0.500

L 0.300 0.400 0.500 11.81

ddd 0.080 3.150

mils

35.43

7.874

271.6 275.6 279.5

198.8 202.7 206.7

19.68

15.75

OUTLINE AND

MECHANICAL DATA

VFQFPN-48 (7x7x1.0mm)

Very Fine Quad Flat Package No lead

ddd

Doc ID 14521 Rev 3 55/57

Revision history L6716

27 Revision history

Table 12. Document revision history

Date Revision Changes

28-May-2009 1 First release

12-Aug-2009 2 Updated Table 3 on page 13.

20-Jan-2010 3

Updated Table 2 on page 8, Table3 on page13, Chapter 13 on

page 29, Figure 14 on page 29 and Chapter 20 on page 45

56/57 Doc ID 14521 Rev 3

L6716

Please Read Carefully:

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www.st.com

Doc ID 14521 Rev 3 57/57

ST L6716 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Table 1. Device summary

1 Principle application circuit and block diagram

1.1 Principle application circuit

Figure 1. Principle application circuit for VR11.1 - 2 phase operation

Figure 2. Principle application circuit for VR11.1- 3 phase operation

Figure 3. Principle application circuit for VR11.1- 4 phase operation

1.2 Block diagram

Figure 4. Block diagram

2 Pin description and connection diagram

Figure 5. Pin connection (top view)

2.1 Pin description

Table 2. Pin description

3 Maximum ratings

3.1 Absolute maximum ratings

Table 3. Absolute maximum ratings

3.2 Thermal data

Table 4. Thermal data

4 Electrical characteristics

4.1 Electrical characteristics

Table 5. Electrical characteristics

5 Voltage identifications

Table 6. Voltage identification (VID) mapping for intel VR11.1 mode

Table 7. Voltage identification (VID) for Intel VR11.1 mode

6 Device description

7 DAC and Phase number selection

Table 8. Number of phases setting

8 Power dissipation

Figure 6. L6716 dissipated power (quiescent + switching)

9 Current reading and current sharing loop

Figure 7. Current reading connections

Figure 8. Current reading connections for the disabled phase

Figure 9. Current sharing loop

10 Differential remote voltage sensing

Figure 10. Differential remote voltage sensing connections

11 Voltage positioning

Figure 11. Voltage positioning (left) and droop function (right)

11.1 Offset (optional)

Figure 12. Voltage positioning with positive offset

11.2 Droop function

12 Droop thermal compensation

Figure 13. NTC connections for DC load line thermal compensation

13 Output current monitoring (IMON)

Figure 14. Output monitoring connection (left) and thermal compensation (right)

14 Load transient boost technology

Figure 15. LTB Technology™ control loop

Figure 16. LTB connections (left) and waveform (right)

15 Dynamic VID transitions

Figure 17. Dynamics VID transitions

16 Enable and disable

17 Soft-start

Figure 18. Soft-start

Figure 19. SSOSC connection

17.1 Low-side-less startup

Figure 22. Low-side-less start-up comparison.with LS-less start-up

18 Output voltage monitor and protections

18.1 Undervoltage

18.2 Preliminary overvoltage

Figure 23. Output voltage protections and typical principle connections

18.3 Overvoltage and programmable OVP

Table 9. Overvoltage protection threshold

Figure 24. OVP threshold during soft-start for tracking (left) and fixed (right) mode

18.4 Overcurrent protection

Figure 25. Overcurrent protection connection

Table 10. # phases when PSI is asserted

18.5 Feedback disconnection

Figure 26. Feedback disconnection

19 Low power state management and PSI#

20 Oscillator

21 Driver section

22 System control loop compensation

Figure 28. Main control loop

Figure 29. Equivalent control loop block diagram (left) and bode diagram (right)

23 Tolerance band (TOB) definition

23.4 Temperature measurement error (VTC)

24 Layout guidelines

24.1 Power components and connections