ST L6716 User Manual

2/3/4 phase controller with embedded drivers for Intel® VR11.1

Features

■ Load transient boost LTB Technology™ to

minimize the number of output capacitors

■ 2 or 3-phase operation with internal driver

■ 4-phase operation with external PWM driver

signal

■ PSI input with programmable strategy

■ Imon output

■ 0.5% output voltage accuracy

■ 8-bit programmable output up to 1.60000 V -

Intel VR11.1 DAC - backward compatible with
VR10/VR11

■ Full differential current sense across inductor

■ Differential remote voltage sensing

■ Adjustable voltage offset

■ LSLess startup to manage pre-biased output

■ Feedback disconnection protection

■ Preliminary overvoltage protection

■ Programmable overcurrent protection

■ Programmable overvoltage protection

■ Adjustable switching frequency

■ SS_END and OUTEN signal

■ VFQFPN-48 7x7 mm package with exposed

pad

Applications

■ High current VRM/VRD for desktop / server /

workstation CPUs

■ High density DC/DC converters

L6716

VFQFPN-48 - 7 x 7 mm

Description

The device implements a two-to-four phases step­down controller with three integrated high current
drivers in a compact 7x7 mm body package with
exposed pad.

Load transient boost LTB Technology™ reduces
system cost by providing the fastest response to
load transition therefore requiring less bulk and
ceramic output capacitors to satisfy load transient
requirements.

The device embeds VR11.x DACs: the output
voltage ranges up to 1.60000 V managing D-VID
with ±0.5% output voltage accuracy over line and
temperature variations.

The controller assures fast protection against load
overcurrent and under / overvoltage (in this last
case also before UVLO). Feedback disconnection
prevents from damaging the load in case of
disconnections in the system board.

In case of overcurrent, the system works in
constant current mode until UVP.

Table 1. Device summary

January 2010 Doc ID 14521 Rev 3 1/57

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Contents L6716

Contents

1 Principle application circuit and block diagram . . . . . . . . . . . . . . . . . . . 4

1.1 Principle application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Pin description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Voltage identifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7 DAC and Phase number selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

9 Current reading and current sharing loop . . . . . . . . . . . . . . . . . . . . . . 23

10 Differential remote voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

11 Voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

11.1 Offset (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

11.2 Droop function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

12 Droop thermal compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

13 Output current monitoring (IMON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

14 Load transient boost technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2/57 Doc ID 14521 Rev 3

L6716 Contents

15 Dynamic VID transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

16 Enable and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

17 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

17.1 Low-side-less startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

18 Output voltage monitor and protections . . . . . . . . . . . . . . . . . . . . . . . . 39

18.1 Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

18.2 Preliminary overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

18.3 Overvoltage and programmable OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

18.4 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

18.5 Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

19 Low power state management and PSI# . . . . . . . . . . . . . . . . . . . . . . . . 44

20 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

21 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

22 System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

23 Tolerance band (TOB) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

23.1 Controller tolerance (TOBController) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

23.2 External current sense circuit tolerance (TOBCurrSense) . . . . . . . . . . . . 50

23.3 Time constant matching error tolerance (TOBTCMatching) . . . . . . . . . . . 50

23.4 Temperature measurement error (VTC) . . . . . . . . . . . . . . . . . . . . . . . . . . 51

24 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

24.1 Power components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

24.2 Small signal components and connections . . . . . . . . . . . . . . . . . . . . . . . 53

25 Embedding L6716 - based VR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

26 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Doc ID 14521 Rev 3 3/57

Principle application circuit and block diagram L6716

1 Principle application circuit and block diagram

1.1 Principle application circuit

to BOOT1

to BOOT3

220nF

ROUT

(a)

Vcc_core

LOAD

GND_core

Figure 1. Principle application circuit for VR11.1 - 2 phase operation

L

42

VCCDR

3

VCC

2

SGND

12

OVPSEL

13

OCSET/PSI_A

11

OFFSET

10

LTBGAIN

14

OSC/FAULT

15

SSOSC

35

SSEND

33

VID7

32

VID6

31

VID5

30

VID4

29

VID3

28

VID2

27

VID1

26

VID0

34

PSI

16

OUTEN

9

IMON

8

LTB

4

COMP

5

FB

6

VSEN

FBG

7

IN

L6716

PWM4 /
PH_SEL

PGND

49

BOOT1

UGATE1

PHASE1

LGATE1

CS1-

CS1+

BOOT2

UGATE2

PHASE2

LGATE2

CS2-

CS2+

BOOT3

UGATE3

PHASE3

LGATE3

CS3-

CS3+

CS4-

CS4+

47

1

48

45

18

Rg

17

39

40

41

44

20

Rg

19

36

37

38

43

Rg

22

21

25

Rg

24

23

VIN

HS1

LS1

VIN

HS3

LS3

CIN

L1

R

C

220nF

220nF

COUT

L3

R

C

220nF

VIN

GNDIN

5V

SB

Optional:Pre-OVP

Vcc

ROVP

ROCSET

ROFFSET

RLTBGAIN

ROSC_SGND

ROSC_VCC

To Vcc

RSS_FLIM

RSSOSC

Optional:

See DS

VTT

1k

SS_END

+3V3

RIMON_OS

R1

RIMON_TOT

CLTB

RLTB

C

I

R

I

L6716 REF.SCH:
2Phase Operation

R3

CP

To GND CORE

RFLIMT

D

Q

10k

VID bus from CPU

To CPU

To Enable circuitry

R2

NTC

CF

RF

RFB

RFB1

RFB2

RFB3

NTC

CIMON

a. Refer to the application note for the reference schematic.

4/57 Doc ID 14521 Rev 3

L6716 Principle application circuit and block diagram

Figure 2. Principle application circuit for VR11.1- 3 phase operation

L

V

IN

GND

IN

42

5V

SB

Optional:Pre-OVP

V

cc

3

2

12

R

OVP

R

OCSET

13

R

OFFSET

11

R

LTBGAIN

10

R

OSC_SGND

14

R

Optional:

See DS

To Vcc

R

D

SSOSC

10k

OSC_VCC

R

SS_FLIM

15

R

FLIMT

Q

VTT

R

R

IMON_TOT

1k

IMON_OS

VID bus from CPU

To CPU

To Enable circuitry

R

1

R

2

R

3

NTC

35

33
32

31
30
29
28
27
26

34

16

9

CI

MON

SS_END

+3V3

To GND CORE

8

C

LTB

C

R

LTB

C

I

R

I

F

C

P

R

F

R

FB1

R

FB3

R

R

NTC

4

5

FB

FB2

6

7

L6716 REF.SCH:

3-Phase Operation

IN

VCCDR

VCC

SGND

OVPSEL

OCSET/PSI_A

OFFSET

LTBGAIN

OSC/FAULT

SSOSC

SSEND

VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0

PSI

OUTEN

IMON

LTB

COMP

FB

VSEN

FBG

PGND

BOOT1

UGATE1

47

PHASE1

LGATE1

CS1-

CS1+

BOOT2

UGATE2

PHASE2

LGATE2

CS2-

CS2+

BOOT3

L6716

UGATE3

38

PHASE3

LGATE3

CS3-

CS3+

PWM4 /
PH_SEL

CS4-

CS4+

49

41

1

48

HS1

V

IN

C

IN

L1

45

LS1

R

C

18

Rg

HS2

220nF

V

IN

17

39

40

L2

44

LS2

R

C

20

Rg

HS3

220nF

V

IN

19

36

37

L3

43

LS3

R

C

Rg

22

21

220nF

25

Rg

24

23

(b)

to BOOT1

to BOOT2

to BOOT3

Vcc_core

C

OUT

LOAD

R

OUT

GND_core

220nF

b. Refer to the application note for the reference schematic.

Doc ID 14521 Rev 3 5/57

Principle application circuit and block diagram L6716

Figure 3. Principle application circuit for VR11.1- 4 phase operation

L

V

IN

GND

IN

Optional:Pre-OVP

Optional:

See DS

VTT

SS_END

+3V3

R

R

IMON_TOT

To GND CORE

L6716 REF.SCH:
4-Phase Operation

5V

SB

1k

IMON_OS

C

LTB

R

LTB

C

I

R

I

V

To Vcc

R

SSOSC

D

10k

VID bus from CPU

To CPU

To Enable circuitry

R

1

R

2

R

3

NTC

C

F

C

P

R

F

R

FB1

R

FB3

cc

R

OVP

R

OCSET

R

OFFSET

R

LTBGAIN

R

OSC_SGND

R

OSC_VCC

R

SS_FLIM

R

R

NTC

42

3

2

12

13

11

10

14

15

R

FLIMT

Q

35

33
32

31
30

29
28
27
26

34

16

9

CI

MON

8

4

5

FB

FB2

6

7

IN

VCCDR

VCC

SGND

OVPSEL

OCSET/PSI_A

OFFSET

LTBGAIN

OSC/FAULT

SSOSC

SSEND

VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0

PSI

OUTEN

IMON

LTB

COMP

FB

VSEN

FBG

PGND

BOOT1

48

UGATE1

47

PHASE1

45

LGATE1

18

CS1-

17

CS1+

39

BOOT2

40

UGATE2

41

PHASE2

44

LGATE2

20

CS2-

19

CS2+

36

BOOT3

L6716

37

UGATE3

38

PHASE3

43

LGATE3

CS3-

CS3+

25
PWM4 /
PH_SEL

CS4-

CS4+

49

1

V

IN

C

IN

HS1

L1

LS1

R

C

Rg

220nF

V

IN

HS2

L2

LS2

R

C

Rg

220nF

V

IN

C

OUT

HS3

L3

LS3

R

C

Rg

22

21

220nF

VIN

Optional

VCC

EX_PAD

7

PVCC

BOOT

UGATE

PHASE

L6741

LGATE

V

IN

2

1

5

8

5

HS4

LS4

C

HF

6

3V3

1k

3

PWM

PWM

1k

4

GND

Rg

24

23

(c)

to BOOT1

to BOOT2

to BOOT3

L4

R

220nF

Vcc_core

LOAD

R

OUT

GND_core

C

c. Refer to the application note for the reference schematic.

6/57 Doc ID 14521 Rev 3

L6716 Principle application circuit and block diagram

1.2 Block diagram

Figure 4. Block diagram

BOOT1

UGATE1

PHASE1

LGATE1

BOOT2

UGATE2

PHASE2

LGATE2

BOOT3

UGATE3

PHASE3

LGATE3

SS_END

OSC / FAULT

SSOSC

VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7

PSI

2/4 PHASE

OSCILLATOR

DIGITAL

SOFT START

DAC

OUTEN

OUTEN

HS1 LS1

LTB

VID CONTROL

WITH DYNAMIC

10uA

HS2

LOGIC PWM

ADAPTIVE ANTI

CROSS CONDUCTION

CURRENT SHARING
CORRECTION

PWM1 PWM2 PWM3

VCC

VCCDR

OUTEN

SSOSC

DROOP

I

I

FFSET
O

LTB

PWM1

CONTROL LOGIC

AND PROTECTIONS

VREF

GND DROP
RECOVERY

FBG

ERROR

AMPLIFIER

FB

COMP

OFFSET

I

LS2 HS3

LOGIC PWM

ADAPTIVE ANTI

CROSS CONDUCTION

CURRENT SHARING
CORRECTION

PWM2

PWM3

L6716

TOTAL DELIVERED CURRENT

+175mV / 1.800V / OVP

COMPARATOR

+.1240V

50uA

VSEN

OFFSET

PWM4

OCP

I

PSI

OVP

LTB

LTB

CROSS CONDUCTION

CURRENT SHARING
CORRECTION

LTB

OCSET

+.1240V

LS3

LOGIC PWM

ADAPTIVE ANTI

AVERAGE

CURRENT

OCSET

I

/PSI_A

OCSET

PGND

LTB

CH4 CURRENT

CH1 CURRENT

CH2 CURRENT

CH3 CURRENT

20uA

OVP

OVPSEL

VCCDR

+.1240V

CURRENT SHARING
CORRECTION

PWM4

READING

READING

READING

READING

IMON

PWM4/PH_SEL

10uA

LTBGAIN

CS4-

CS4+

CS1­CS1+

CS2­CS2+

CS3-

CS3+

VCC

DROOP

I

VCC

SGND

Doc ID 14521 Rev 3 7/57

Pin description and connection diagram L6716

2 Pin description and connection diagram

Figure 5. Pin connection (top view)

BOOT3

SSEND

PSI

VID7

VID6

VID5

VID4

VID3

VID2

VID1

VID0

PWM4/

PH_SEL

UGATE3

PHASE3

BOOT2

UGATE2

PHASE2

VCCDR

LGATE3

LGATE2

LGATE1

N.C.

PHASE1

UGATE1

36 35 34 33 32 31 30 29 28 27 26 25

37

38

39

40

41

42

43

44

45

46

47

48

123456789101112

49 PGND

24

23

22

21

20

19

18

17

16

15

14

13

CS4-

CS4+

CS3-

CS3+

CS2-

CS2+

CS1-

CS1+

OUTEN

SSOSC

OSC/FAULT

OCSET/PSI_A

2.1 Pin description

Table 2. Pin description

N° Name Description

Channel 1 HS driver supply.

1BOOT1

2 SGND All the internal references are referred to this pin. Connect it to the PCB signal ground.

3VCC

4COMP

5FB

6VSEN

7FBG

Connect through a capacitor (100 nF typ.) to PHASE1 and provide necessary bootstrap diode.
A small resistor in series to the boot diode helps in reducing boot capacitor overcharge.

Device supply voltage pin.
The operative supply voltage is 12 V ±15%. Filter with at least 1 μF capacitor vs. SGND.

Error amplifier output. Connect with an R
The device cannot be disabled by pulling down this pin.

Error amplifier inverting input pin.
Connect with a resistor R
A current proportional to the load current is sourced from this pin in order to implement the

Droop effect. See “Droop function” Section for details.

Output voltage monitor, manages OVP/UVP protections and FB disconnection.
Connect to the positive side of the load to perform remote sense.

See “Layout guidelines” Section for proper layout of this connection.

Connect to the negative side of the load to perform remote sense.

See “Layout guidelines” Section for proper layout of this connection.

FB

VCC

SGND

BOOT1

FB

COMP

vs. VSEN and with an RF - CF//CP vs. COMP pin.

LT B

FBG

VSEN

IMON

LTBGAIN

- CF//CP vs. FB pin.

F

OFFSET

OVPSEL

8/57 Doc ID 14521 Rev 3

L6716 Pin description and connection diagram

Table 2. Pin description (continued)

N° Name Description

Load transient boost pin.
Internally fixed at 2 V, connecting a R

8LTB

boost technology™: as soon as the device detects a transient load it turns on all the PHASEs
at the same time. Short to SGND to disable the function.

See “Load transient boost technology” Section for details.

Current monitor output pin.

9IMON

A current proportional to the load current is sourced from this pin. Connect through a resistor

to FBG to implement a load indicator. Connect the load indicator directly to VR11.1

R

MON

CPUs.The pin voltage is clamped to 1.1 V max to preserve the CPU from excessive voltages.

Load transient boost technology™ gain pin.

10 LTBGAIN

Internally fixed at 1.24 V, connecting a R
the LTB action. See See “Load transient boost technology” Section for details.

Offset programming pin.
Internally fixed at 1.240 V, connecting a R

11 OFFSET

that is mirrored into FB pin in order to program a positive offset according to the selected R
Short to SGND to disable the function.

See “Offset (optional)” Section for details.

Overvoltage programming pin. Internally pulled up by 20 µA (typ) to 3.3 V.
Leave floating to use built-in protection thresholds (OVP

12 OVPSEL

Connect to SGND through a R
threshold to a fixed voltage according to the R

OVP

See “Overvoltage and programmable OVP” Section for details.

Connect to SGND to select VR10/VR11 table. In this case the OVP threshold becomes

1.800 V (typ).

Overcurrent setting, PSI action pin.

13

OCSET/

PSI_A

Connect to SGND through a R

OCSET

It also allows to select the number of phase when PSI mode is selected.

See “Overcurrent protection” Section for details.

Oscillator, FAULT pin.
It allows programming the switching frequency FSW of each channel: the equivalent switching

frequency at the load side results in being multiplied by the phase number N.

14

OSC/

FAULT

Frequency is programmed according to the resistor connected from the pin vs. SGND or VCC
with a gain of 9.1 kHz/µA (see relevant section for details).

Leaving the pin floating programs a switching frequency of 200 kHz per phase.
The pin is forced high (3.3 V typ) to signal an OVP/UVP fault: to recover from this condition,

cycle VCC or the OUTEN pin. See “Oscillator” Section for details.

Soft-start oscillator pin.
By connecting a resistor R

15 SSOSC

Soft-Start time T
implemented to reach V
V

to the programmed VID code. The pin is kept to a fixed 1.240 V.

BOOT

See “Soft-start” Section for details.

will proportionally change with a gain of 25 [µs / kΩ]. The same slope

SS

to GND, it allows programming the soft-start time.

SS

has to be considered also when the reference moves from

BOOT

- C

LT B

LT B

LTBGAIN

OFFSET

vs. V

resistor vs SGND allows setting the gain of

resistor vs. SGND allows setting a current

allows to enable the load transient

OUT

= VID + 175 mV typ).

TH

resistor and filter with 100 pF (max) to set the OVP

resistor.

OVP

resistor to set the OCP threshold for each phase.

FB

.

Doc ID 14521 Rev 3 9/57

Pin description and connection diagram L6716

Table 2. Pin description (continued)

N° Name Description

Output enable pin. Internally pulled up by 10 µA (typ) to 3 V.
Forced low, the device stops operations with all MOSFETs OFF: all the protections are

16 OUTEN

17 CS1+

18 CS1-

19 CS2+

20 CS2-

21 CS3+

22 CS3-

disabled except for preliminary overvoltage.
Leave floating, the device starts-up implementing soft-start up to the selected VID code.
Cycle this pin to recover latch from protections; filter with 1 nF (typ) vs. SGND.

Channel 1 current sense positive input.
Connect through an R-C filter to the phase-side of the channel 1 inductor.

See “Layout guidelines” Section for proper layout of this connection.

Channel 1 current sense negative input.
Connect through a Rg resistor to the output-side of the channel 1 inductor.

See “Layout guidelines” Section for proper layout of this connection.

Channel 2 current sense positive input.
Connect through an R-C filter to the phase-side of the channel 2 inductor.
Short to V

when using 2-phase operation.

OUT

See “Layout guidelines” Section for proper layout of this connection.

Channel 2 current sense negative input.
Connect through a Rg resistor to the output-side of the channel 2 inductor.
Still connect to V

through Rg resistor when using 2-phase operation.

OUT

See “Layout guidelines” Section for proper layout of this connection.

Channel 3 current sense positive input.
Connect through an R-C filter to the phase-side of the channel 3 inductor.

See “Layout guidelines” Section for proper layout of this connection.

Channel 3 current sense negative input.
Connect through a Rg resistor to the output-side of the channel 3 inductor.

See “Layout guidelines” Section for proper layout of this connection.

Channel 4 current sense positive input.

23 CS4+

Connect through an R-C filter to the phase-side of the channel 4 inductor.
Short to V

when using 2-phase or 3-phase operation.

OUT

See “Layout guidelines” Section for proper layout of this connection.

Channel 4 current sense negative input.

24 CS4-

Connect through a Rg resistor to the output-side of the channel 4 inductor.
Still connect to V

through Rg resistor when using 2-phase or 3-phase operation.

OUT

See “Layout guidelines” Section for proper layout of this connection.

PWM outputs, phase selection pin.
Internally pulled up by 10 µA to 3.3 V (until the soft-start has not finished), connect to external

driver PWM input when 4-phase operation is used.
The device is able to manage HiZ status by setting the pis floating.

25

PWM4/

PH_SEL

Short to SGND to select 3-phase operation and leave floating to select 2-phase operation.

26 to 33

VID0 to

VID7

Voltage identification pins. (not internally pulled up).
Connect to SGND to program a '0' or connect to the external pull-up resistor to program a '1'.

They allow programming output voltage as specified in Tab l e 7 .

10/57 Doc ID 14521 Rev 3

L6716 Pin description and connection diagram

Table 2. Pin description (continued)

N° Name Description

Power saving indicator pin.

34 PSI

35 SSEND

36 BOOT3

37 UGATE3

38 PHASE3

39 BOOT2

40 UGATE2

Connect to the PSI pin of the CPU to manage low-power state.
When asserted (pulled low), the controller will act as programmed on the OCSET/PSI_A.

Soft-start END signal.
Open drain output sets free after ss has finished and pulled low when triggering any

protection. Pull up to a voltage lower than 3.3 V, if not used it can be left floating.

Channel 3 HS driver supply.
Connect through a capacitor (100 nF typ.) to PHASE3 and provide necessary bootstrap

diode.A small resistor in series to the boot diode helps in reducing boot capacitor overcharge.

Channel 3HS driver output.
It must be connected to the HS3 MOSFET gate. A small series resistors helps in reducing

device-dissipated power.

Channel 3 HS driver return path.
It must be connected to the HS3 MOSFET source and provides return path for the HS driver

of channel 3.

Channel 2 HS driver supply.
Connect through a capacitor (100 nF typ.) to PHASE2 and provide necessary bootstrap diode.

A small resistor in series to the boot diode helps in reducing Boot capacitor overcharge. Leave
floating when using 2-Phase operation.

Channel 2HS driver output.
It must be connected to the HS2 MOSFET gate. A small series resistors helps in reducing

device-dissipated power. Leave floating when using 2-Phase operation.

Channel 2 HS driver return path.

41 PHASE2

It must be connected to the HS2 MOSFET source and provides return path for the HS driver
of channel 2. Leave floating when using 2-phase operation.

42 VCCDR

43 LGATE3

LS Driver Supply. VCDDR pin voltage has to be the same of VCC pin.
Filter with 2 x 1 µF MLCC capacitor vs. PGND.

Channel 3LS driver output.
A small series resistor helps in reducing device-dissipated power.

Channel 2LS driver output.

44 LGATE2

A small series resistor helps in reducing device-dissipated power.
Leave floating when using 2-phase operation.

45 LGATE1

Channel 1LS driver output.
A small series resistor helps in reducing device-dissipated power.

46 N.C. Not internally connected.

Channel 1 HS driver return path.

47 PHASE1

It must be connected to the HS1 MOSFET source and provides return path for the HS driver
of channel 1.

Doc ID 14521 Rev 3 11/57

Pin description and connection diagram L6716

Table 2. Pin description (continued)

N° Name Description

Channel 1HS driver output.

48 UGATE1

49 PGND

It must be connected to the HS1 MOSFET gate. A small series resistors helps in reducing
device-dissipated power.

Power ground pin (LS drivers return path). Connect to power ground plane.
Exposed pad connects also the silicon substrate. As a consequence it makes a good thermal

contact with the PCB to dissipate the power necessary to drive the external MOSFETs.
Connect it to the power ground plane using 5.2 x 5.2 mm square area on the PCB and with

sixteen vias (uniformly distributed), to improve electrical and thermal conductivity.

12/57 Doc ID 14521 Rev 3

L6716 Maximum ratings

3 Maximum ratings

3.1 Absolute maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

V

CC, VCCDR

V

BOOTx

V

PHASEx

V

UGATEx

V

PHASEx

To P GN D 1 5 V

­Boot voltage 15 V

-

LGATEx to PGND

All other pins to PGND -0.3 to 3.6 V

Negative peak voltage to PGND; T < 400 ns
VCC = VCCDR = 12 V

V

PHASE

Positive voltage to PGND
VCC = VCCDR = 12 V

Positive peak voltage to PGND; T < 200 ns
VCC = VCCDR = 12 V

Maximum withstanding voltage range test condition:
CDF-AEC-Q100-002- “human body model”
acceptance criteria: “normal performance”

3.2 Thermal data

15 V

-0.3 to

Vcc+0.3

-8 V

26 V

30 V

+/- 1750 V

V

Table 4. Thermal data

Symbol Parameter Value Unit

R

thJA

T

MAX

T

stg

T

J

P

tot

Thermal resistance junction to ambient
(Device soldered on 2s2p PC board)

40 °C / W

Maximum junction temperature 150 °C

Storage temperature range -40 to 150 °C

Junction temperature range -10 to 125 °C

Max power dissipation at TA = 25 °C 2.5 W

Doc ID 14521 Rev 3 13/57

Electrical characteristics L6716

4 Electrical characteristics

4.1 Electrical characteristics

V

= 12 V ± 15%, TJ = 0 °C to 70 °C unless otherwise specified.

CC

Table 5. Electrical characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

Supply current and power-on

I

CC

I

CCDR

I

BOOTx

VCC supply current

VCCDR supply current LGATEx = OPEN; VCCDR = 12 V 5 7 mA

BOOTx supply current

UGATEx and LGATEx open;
VCC = VBOOTx = 12 V

UGATEx = OPEN; PHASEx to PGND;
VCC = BOOTx = 12V

22 25 mA

1.8 2.7 mA

Power-on

VCC turn-ON VCC rising; VCCDR = VCC 3.7 4.0 V

UVLO

VCC

VCC turn-OFF VCC falling; VCCDR = VCC 3.3 3.5 V

Pre-OVP turn-ON VCC rising; VCCDR = VCC 3.7 4.0 V

UVLO

Pre-OVP

Pre-OVP turn-OFF VCC falling; VCCDR = VCC 3.3 3.5 V

Oscillator and inhibit

F

OSC

TD

TD

TD

Initial accuracy OSC=OPEN; TJ = 0 to 125 °C 180 200 220 kHz

SS delay time 1 1.5 ms

1

SS TD2 time R

2

SS TD3 time 150 250 μs

3

= 20 kΩ 500 μs

SSOSC

Rising thresholds voltage 0.80 0.85 0.90 V

Output enable

OUTEN

Hysteresis 100 mV

Output pull-up current OUTEN to SGND 10 μA

ΔVosc Ramp amplitude 1.5 V

FAULT Voltage at pin OSC/FAULT OVP and UVP Active 3.3 V

Reference and DAC

VID = 1.000 V to VID = 1.600 V
FB = VOUT; FBG = GNDOUT

K

VID

V

BOOT

Output voltage accuracy

Boot voltage 1.081 V

VID = 0.800 V to VID = 1.000 V
FB = VOUT; FBG = GNDOUT

VID = 0.500 V to VID = 0.800 V
FB = VOUT; FBG = GNDOUT

14/57 Doc ID 14521 Rev 3

-0.5 - 0.5 %

-5 - +5 mV

-8 - +8 mV

L6716 Electrical characteristics

Table 5. Electrical characteristics (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

I

VID

VID

VID

VID pull-up current VIDx to SGND 0 μA

IH

IL

VID thresholds

Input low 0.35 V

Input high 0.8 V

Input low 0.4

PSI thresholds

PSI

Input high 0.8

PSI pull-up current PSI to SGND 0 μA

Error amplifier

A

0

EA DC gain 130 dB

SR EA slew-rate COMP = 10 pF to SGND 25 V/μs

Differential current sensing and offset

I

CSx+

V

OCSET

Bias current 0 μA

OCSET pin voltage 1.105 1.245 1.385 mV

Rg = 1 kΩ;

DROOP

DROOP

DROOP

DROOP

= 25 μA;
= 50 μA;
= 75 μA;
= 100 μA;

-3 - +3 μA

K

IDROOP

K

IOFFSET

I

OFFSET

V

OFFSET

Droop current deviation from
nominal value

1-PHASE, I
2-PHASE, I
3-PHASE, I
4-PHASE, I

Offset current accuracy I

= 50 μA to 250 μA-5-5%

OFFSET

OFFSET current range 0 250 μA

OFFSET pin bias I

= 0 to 250 μA1.240V

OFFSET

Gate drivers

V

t

RISE UGATE

I

UGATEx

R

UGATEx

t

RISE LGATE

I

LGATEx

R

LGATEx

PWM output

PWM4

I

PWM4

High side rise time

BOOTx-PHASEx = 12 V;
C

to PHASEx = 3.3 nF

UGATEx

20 ns

High side source current BOOTx-PHASEx = 12 V 1.5 A

High side sink resistance BOOTx-PHASEx = 12 V 2 Ω

Low side rise time

VCCDR = 12 V;
C

to PGNDx = 5.6 nF

LGATEx

25 ns

Low side source current VCCDR = 12 V 2 A

Low side sink resistance VCCDR = 12 V 1 Ω

Output high I = 1 mA 3 V

Output low I = -1 mA 0.2 V

PWM4 pull-up current Before SSEND = 1; PWM4 to SGND 10 μA

Doc ID 14521 Rev 3 15/57

Electrical characteristics L6716

Table 5. Electrical characteristics (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

Protections

OVP

Programmab

le OVP

Pre- OVP

Overvoltage protection
(VSEN rising)

current OVP = SGND 20 22 24 μA

I

OVP

Before V

BOOT

Above VID-19 mV (after TD

) 150 175 200 mV

3

Comparator offset voltage OVP = 1.800 V -20 0 20 mV

< VCC < UVLO

OVP

VCC

VCC

and OUTEN = SGND

1.750 1.800 1.850 V

Preliminary overvoltage
protection

UVLO
VCC> UVLO
VSEN rising

1.24 1.300 V

Hysteresis 350 mV

UVP Under voltage threshold VSEN falling; below VID-19 mV 550 600 650 mV

V

SSEND

SS_END voltage low I = -4 mA 0.4 V

16/57 Doc ID 14521 Rev 3

L6716 Voltage identifications

5 Voltage identifications

Table 6. Voltage identification (VID) mapping for intel VR11.1 mode

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

800 mV 400 mV 200 mV 100 mV 50 mV 25 mV 12.5 mV 6.25 mV

Table 7. Voltage identification (VID) for Intel VR11.1 mode

HEX code

Output

voltage

(1)

HEX code

Output

voltage

HEX code

(1)

Output

voltage

HEX code

(1)

Output

voltage

0 0 OFF 4 0 1.21250 8 0 0.81250 C 0 0.41250

0 1 OFF 4 1 1.20625 8 1 0.80625 C 1 0.40625

0 2 1.60000 4 2 1.20000 8 2 0.80000 C 2 0.40000

0 3 1.59375 4 3 1.19375 8 3 0.79375 C 3 0.39375

0 4 1.58750 4 4 1.18750 8 4 0.78750 C 4 0.38750

0 5 1.58125 4 5 1.18125 8 5 0.78125 C 5 0.38125

0 6 1.57500 4 6 1.17500 8 6 0.77500 C 6 0.37500

0 7 1.56875 4 7 1.16875 8 7 0.76875 C 7 0.36875

0 8 1.56250 4 8 1.16250 8 8 0.76250 C 8 0.36250

0 9 1.55625 4 9 1.15625 8 9 0.75625 C 9 0.35625

0 A 1.55000 4 A 1.15000 8 A 0.75000 C A 0.35000

0 B 1.54375 4 B 1.14375 8 B 0.74375 C B 0.34375

0 C 1.53750 4 C 1.13750 8 C 0.73750 C C 0.33750

0 D 1.53125 4 D 1.13125 8 D 0.73125 C D 0.33125

0 E 1.52500 4 E 1.12500 8 E 0.72500 C E 0.32500

0 F 1.51875 4 F 1.11875 8 F 0.71875 C F 0.31875

(1)

1 0 1.51250 5 0 1.11250 9 0 0.71250 D 0 0.31250

1 1 1.50625 5 1 1.10625 9 1 0.70625 D 1 0.30625

1 2 1.50000 5 2 1.10000 9 2 0.70000 D 2 0.30000

1 3 1.49375 5 3 1.09375 9 3 0.69375 D 3 0.29375

1 4 1.48750 5 4 1.08750 9 4 0.68750 D 4 0.28750

1 5 1.48125 5 5 1.08125 9 5 0.68125 D 5 0.28125

1 6 1.47500 5 6 1.07500 9 6 0.67500 D 6 0.27500

1 7 1.46875 5 7 1.06875 9 7 0.66875 D 7 0.26875

1 8 1.46250 5 8 1.06250 9 8 0.66250 D 8 0.26250

1 9 1.45625 5 9 1.05625 9 9 0.65625 D 9 0.25625

Doc ID 14521 Rev 3 17/57

Voltage identifications L6716

Table 7. Voltage identification (VID) for Intel VR11.1 mode (continued)

HEX code

Output

voltage

(1)

HEX code

Output

voltage

HEX code

(1)

Output

voltage

HEX code

(1)

Output

voltage

1 A 1.45000 5 A 1.05000 9 A 0.65000 D A 0.25000

1 B 1.44375 5 B 1.04375 9 B 0.64375 D B 0.24375

1 C 1.43750 5 C 1.03750 9 C 0.63750 D C 0.23750

1 D 1.43125 5 D 1.03125 9 D 0.63125 D D 0.23125

1 E 1.42500 5 E 1.02500 9 E 0.62500 D E 0.22500

1 F 1.41875 5 F 1.01875 9 F 0.61875 D F 0.21875

2 0 1.41250 6 0 1.01250 A 0 0.61250 E 0 0.21250

2 1 1.40625 6 1 1.00625 A 1 0.60625 E 1 0.20625

2 2 1.40000 6 2 1.00000 A 2 0.60000 E 2 0.20000

2 3 1.39375 6 3 0.99375 A 3 0.59375 E 3 0.19375

2 4 1.38750 6 4 0.98750 A 4 0.58750 E 4 0.18750

2 5 1.38125 6 5 0.98125 A 5 0.58125 E 5 0.18125

2 6 1.37500 6 6 0.97500 A 6 0.57500 E 6 0.17500

2 7 1.36875 6 7 0.96875 A 7 0.56875 E 7 0.16875

2 8 1.36250 6 8 0.96250 A 8 0.56250 E 8 0.16250

2 9 1.35625 6 9 0.95625 A 9 0.55625 E 9 0.15625

2 A 1.35000 6 A 0.95000 A A 0.55000 E A 0.15000

(1)

2 B 1.34375 6 B 0.94375 A B 0.54375 E B 0.14375

2 C 1.33750 6 C 0.93750 A C 0.53750 E C 0.13750

2 D 1.33125 6 D 0.93125 A D 0.53125 E D 0.13125

2 E 1.32500 6 E 0.92500 A E 0.52500 E E 0.12500

2 F 1.31875 6 F 0.91875 A F 0.51875 E F 0.11875

3 0 1.31250 7 0 0.91250 B 0 0.51250 F 0 0.11250

3 1 1.30625 7 1 0.90625 B 1 0.50625 F 1 0.10625

3 2 1.30000 7 2 0.90000 B 2 0.50000 F 2 0.10000

3 3 1.29375 7 3 0.89375 B 3 0.49375 F 3 0.09375

3 4 1.28750 7 4 0.88750 B 4 0.48750 F 4 0.08750

3 5 1.28125 7 5 0.88125 B 5 0.48125 F 5 0.08125

3 6 1.27500 7 6 0.87500 B 6 0.47500 F 6 0.07500

3 7 1.26875 7 7 0.86875 B 7 0.46875 F 7 0.06875

3 8 1.26250 7 8 0.86250 B 8 0.46250 F 8 0.06250

3 9 1.25625 7 9 0.85625 B 9 0.45625 F 9 0.05625

3 A 1.25000 7 A 0.85000 B A 0.45000 F A 0.05000

3 B 1.24375 7 B 0.84375 B B 0.44375 F B 0.04375

18/57 Doc ID 14521 Rev 3