ST L6713A User Manual
L6713A
2/3 phase controller with embedded drivers for Intel VR10, VR11
and AMD 6 bit CPUs
Features
■ Load transient boost LTB Technology™ to
minimize the number of output capacitors
(patent pending)
■ Dual-edge asynchronous PWM
■ Selectable 2 or 3 phase operation
■ 0.5 % output voltage accuracy
■ 7/8 bit programmable output up to 1.60000 V -
Intel VR10.x, VR11 DAC
■ 6 bit programmable output up to 1.5500 V -
AMD 6 bit DAC
■ High current integrated gate drivers
■ Full differential current sensing across inductor
■ Embedded VRD thermal monitor
■ Differential remote voltage sensing
■ Dynamic VID management
■ Adjustable voltage offset
■ Low-side-less startup
■ Programmable soft-start
■ Programmable over voltage protection
■ Preliminary over voltage protection
■ Programmable over current protection
■ Adjustable switching frequency
■ Output enable
■ SS_END / PGOOD signal
■ TQFP64 10x10 mm package with exposed pad
Applications
■ High current VRD for desktop CPUs
■ Workstation and server CPU power supply
■ VRM modules
Table 1. Device summary
Description
L6713A implements a two/three phase step-down
controller with 180º/120º phase-shift between
each phase with integrated high current drivers in
a compact 10x10 mm body package with exposed
pad.The 2 or 3 phase operation can be easily
selected through PHASE_SEL pin.
Load transient boost LTB Technology™ (patent
pending) reduces system cost by providing the
fastest response to load transition therefore
requiring less bulk and ceramic output capacitors
to satisfy load transient requirements.
LTB Technology™ can be disabled and in this
condition the device works as a dual-edge
asynchronous PWM.
The device embeds selectable DACs: the output
voltage ranges up to 1.60000 V (both Intel VR10.x
and VR11 DAC) or up to 1.5500 V (AMD 6BIT
DAC) managing D-VID with ± 0.5% output voltage
accuracy over line and temperature variations.
The controller assures fast protection against load
over current and under / over voltage (in this last
case also before UVLO). In case of over-current
the device turns off all MOSFET and latches the
condition.
System thermal monitor is also provided allowing
system protection from over-temperature
conditions.
TQFP64 (Exposed pad)
Order codes Package Packaging
L6713A
TQFP64 (Exposed pad)
L6713ATR Tape and reel
August 2008 Rev 3 1/64
Tube
www.st.com
64
Contents L6713A
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 VID Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 Mapping for the Intel VR11 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 Voltage identification (VID) for Intel VR11 mode . . . . . . . . . . . . . . . . . . . 16
5.3 Voltage identifications (VID) for Intel VR10 mode + 6.25 mV . . . . . . . . . . 18
5.4 Mapping for the AMD 6 bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.5 Voltage identifications (VID) codes for AMD 6 bit mode . . . . . . . . . . . . . . 20
6 Reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8 Configuring the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.1 Number of phases selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.2 DAC selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10 Current reading and current sharing loop . . . . . . . . . . . . . . . . . . . . . . 32
11 Differential remote voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2/64
L6713A Contents
12 Voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
12.1 Offset (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
12.2 Droop function (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
13 Load transient boost technology™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
13.1 LTB™ gain modification (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
14 Dynamic VID transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
15 Enable and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
16 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
16.1 Intel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
16.1.1 SS/LTB/AMD connections when using LTB™ gain = 2 . . . . . . . . . . . . . 43
16.1.2 SS/LTB/AMD connections when using LTB™ gain < 2 . . . . . . . . . . . . . 44
16.2 AMD mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
16.3 Low-side-less startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
17 Output voltage monitor and protections . . . . . . . . . . . . . . . . . . . . . . . . 47
17.1 Under voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
17.2 Preliminary over voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
17.3 Over voltage and programmable OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
17.4 PGOOD (only for AMD mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
18 Over current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
19 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
20 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
21 System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
22 Thermal monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3/64
Contents L6713A
23 Tolerance band (TOB) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
23.1 Controller tolerance (TOBController) . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
23.2 Ext. current sense circuit tolerance (TOBCurrSense) . . . . . . . . . . . . . . . 56
23.3 Time constant matching error tolerance (TOBTCMatching) . . . . . . . . . . 56
23.4 Temperature measurement error (VTC) . . . . . . . . . . . . . . . . . . . . . . . . . . 57
24 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
24.1 Power components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
24.2 Small signal components and connections . . . . . . . . . . . . . . . . . . . . . . . 59
25 Embedding L6713A - based VR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
26 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4/64
L6713A Block diagram
1 Block diagram
Figure 1. Block diagram
BOOT1
UGATE1
PHASE1
VCCDR1
LGATE1
PGND1
BOOT2
UGATE2
PHASE2
VCCDR2
LGATE2
PGND2
BOOT3
UGATE3
PHASE3
VCCDR3
LGATE3
PGND3
SS_END / PGOOD
OSC / FAULT
SS/ LTBG/ AMD
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7 / D-VID
VID_SEL
2/3 PHASE
OSCILLATOR
DIGITAL
SOFT START
DAC
12.5μA
OUTEN
HS1 LS1 HS2 LS2 HS3 LS3
VID CONTROL
WITH DYNAMIC
OUTEN
LOGIC PWM
ADAPTIVE ANTI
CROSS CONDUCTION
CURRENT SHARING
CORRECTION
PWM1 PWM2 PWM3
VCC
VCCDR
OUTEN
SSOSC/AMD
DROOP
I
VREF
GND DROP
RECOVERY
FBG
ERROR
AMPLIFIER
FB
DROOP
LOGIC PWM
ADAPTIVE ANTI
CROSS CONDUCTION
CURRENT SHARING
CORRECTION
LTBLTB LTB
PWM1
L6713A
CONTROL LOGIC
AND PROTECTIONS
PWM3
PWM2
TOTAL DELIVERED CURRENT
+175mV / 1.800V / OVP
OVP
COMPARATOR
OFFSET
I
VSEN
COMP
TO OCP
LTB
LTB
OCP
COMPARATOR
LOGIC PWM
ADAPTIVE ANTI
CROSS CONDUCTION
CURRENT SHARING
CORRECTION
AVERAGE
CURRENT
+.1240V
OCP
OCSET
I
OCSET
12.5μA
3.600V
CH1 CURRENT
READING
CH2 CURRENT
READING
CH3 CURRENT
READING
12.5μA
OVP
OVP
3.200V
VCC
PHASE_SEL
PHASE _SEL
VR_HOT
VR_FAN
TM
CS1CS1+
CS2CS2+
CS3CS3+
VCC
SGND
5/64
Pin settings L6713A
2 Pin settings
2.1 Pin connection
Figure 2. Pin connection (top view)
VID4
VID5
VID6
VID7 / D-VID
VR_FAN
VR_HOT
SS_END / PGOOD
VID0
VID1
VID2
VID3
FBG
VID_SEL
OCSET
OVP
OSC / FAULT
TM
SGND
N.C.
N.C.
N.C.
PGND2
LGATE2
VCCDR2
VCCDR3
LGATE3
PGND3
PGND1
LGATE1
VCCDR1
PHASE1
N.C.
48 47 46 45 44 43 42 41 40 39 38 37
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
123 45678 9 101112
N.C.
BOOT1
UAGTE1
UGATE3
PHASE3
L6713A
N.C.
BOOT3
PHASE2
UGATE2
BOOT2
36 35 34 33
13 14 15 16
N.C.
N.C.
32
SS / LTBG / AMD
31
CS1-
30
CS1+
29
CS3-
28
CS3+
27
CS2-
26
CS2+
25
N.C.
24
N.C.
23
COMP
22
FB
21
DROOP
20
VSEN
19
SGND
18
LT B
17
OUTEN
N.C.
N.C.
VCC
PHASE_SEL
6/64
L6713A Pin settings
2.2 Pin description
Table 2. Pin description
N° Pin Function
1UGATE1
2BOOT1
3 N.C. Not internally connected.
4 PHASE3
5UGATE3
6BOOT3
7 N.C. Not internally connected.
8 PHASE2
9UGATE2
10 BOOT2
11 N.C. Not internally connected.
12 N.C. Not internally connected.
Channel 1 HS driver output.
A small series resistors helps in reducing device-dissipated power.
Channel 1 HS driver supply.
Connect through a capacitor (100 nF typ.) to PHASE1 and provide necessary
Bootstrap diode. A small resistor in series to the boot diode helps in reducing
Boot capacitor overcharge.
Channel 3 HS driver return path.
It must be connected to the HS3 MOSFET source and provides return path for
the HS driver of channel 3.
Channel 3 HS driver output.
A small series resistors helps in reducing device-dissipated power.
Channel 3 HS driver supply.
Connect through a capacitor (100 nF typ.) to PHASE3 and provide necessary
Bootstrap diode. A small resistor in series to the boot diode helps in reducing
Boot capacitor overcharge.
Channel 2 HS driver return path.
It must be connected to the HS2 MOSFET source and provides return path for
the HS driver of channel 2. Leave floating when using 2 phase operation.
Channel 2 HS driver output.
A small series resistors helps in reducing device-dissipated power.
Leave floating when using 2 phase operation.
Channel 2 HS driver supply.
Connect through a capacitor (100 nF typ.) to PHASE2 and provide necessary
Bootstrap diode. A small resistor in series to the boot diode helps in reducing
Boot capacitor overcharge.Leave floating when using 2 phase operation.
13 N.C. Not internally connected.
14 N.C. Not internally connected.
15 VCC
PHASE_
16
SEL
Device supply voltage. The operative voltage is 12 V ±15 %. Filter with 1 µF
(typ) MLCC vs. SGND.
Phase selection pin. Internally pulled up by 12.5 µA(typ) to 5 V.
It allows selecting between 2 phase and 3 phase operation. See Table 11 for
details.
7/64
Pin settings L6713A
Table 2. Pin description (continued)
N° Pin Function
Output enable pin. Internally pulled up by 12.5 µA(typ) to 5 V.
Forced low, the device stops operations with all MOSFETs OFF: all the
17 OUTEN
18 LTB
19 SGND
20 VSEN
protections are disabled except for Preliminary over voltage.
Leave floating, the device starts-up implementing soft-start up to the selected
VID code.
Cycle this pin to recover latch from protections; filter with 1 nF (typ) vs. SGND.
Load transient boost pin.
- C
Internally fixed at 1 V, connecting a R
LTB
vs. VOUT allows to enable the
LTB
Load transient boost technology™: as soon as the device detects a transient
load it turns on all the PHASEs at the same time. Short to SGND to disable the
function.
All the internal references are referred to this pin. Connect to the PCB Signal
Ground.
It manages OVP and UVP protections and PGOOD (when applicable).
See “Output voltage monitor and protections” Section.
100 µA constant current
(I
generate a positive offset in according to the R
, See Table 5) is sunk by VSEN pin in order to
OFFSET
resistor between VSEN
OFFSET
pin and VOUT. See “Offset (Optional)” Section for details.
A current proportional to the total current read is sourced from this pin
according to the current reading gain.
21 DROOP
Short to FB to implement droop function or short to SGND to disable the
function. Connecting to SGND through a resistor and filtering with a capacitor,
the current info can be used for other purposes.
22 FB
23 COMP
Error amplifier inverting input. Connect with a resistor R
an RF - CF vs. COMP.
Error amplifier output. Connect with an R
The device cannot be disabled by pulling down this pin.
24 N.C. Not internally connected.
25 N.C. Not internally connected.
Channel 2 current sense positive input.
26 CS2+
Connect through an R-C filter to the phase-side of the channel 2 inductor.
Short to SGND or to V
OUT
See “Layout guidelines” Section for proper layout of this connection.
Channel 2 current sense negative input.
27 CS2-
Connect through a Rg resistor to the output-side of the channel 2 inductor.
Leave floating when using 2 Phase operation.
See “Layout guidelines” Section for proper layout of this connection.
Channel 3 current sense positive input.
28 CS3+
Connect through an R-C filter to the phase-side of the channel 3 inductor.
See “Layout guidelines” Section for proper layout of this connection.
Channel 3 current sense negative input.
29 CS3-
Connect through a Rg resistor to the output-side of the channel 3 inductor.
See “Layout guidelines” Section for proper layout of this connection.
FB
- CF vs. FB.
F
when using 2 Phase operation.
vs. VSEN and with
8/64
L6713A Pin settings
Table 2. Pin description (continued)
N° Pin Function
Channel 1 current sense positive input.
30 CS1+
31 CS1-
SS/ LTBG/
32
AMD
33 OVP
Connect through an R-C filter to the phase-side of the channel 1 inductor.
See “Layout guidelines” Section for proper layout of this connection.
Channel 1 current sense negative input.
Connect through a Rg resistor to the output-side of the channel 1 inductor.
See “Layout guidelines” Section for proper layout of this connection.
Soft-start oscillator, LTB gain and AMD selection pin.
It allows selecting between INTEL DACs and AMD DAC.
Short to SGND to select AMD DAC otherwise INTEL mode is selected.
When INTEL mode is selected trough this pin it is possible to select the soft-
start time and also the gain of LTB Technology™. See “Soft-start” Section” and
See “Load transient boost technologyTM” Section for details.
Over voltage programming pin. Internally pulled up by 12.5 µA (typ) to 5 V.
Leave floating to use built-in protection thresholds as reported into Ta b l e 1 2 .
Connect to SGND through a R
the OVP threshold to a fixed voltage according to the R
resistor and filter with 100 pF (max) to set
OVP
OVP
resistor.
See “Over voltage and programmable OVP” Section Section for details.
34 VID_SEL
35 OCSET
36 FBG
37
OSC/
FAULT
38 VID7/DVID
39 VID6
Intel mode. Internally pulled up by 12.5 µA (typ) to 5 V.
It allows selecting between VR10 (short to SGND, Ta bl e 8 ) or VR11 (floating,
See Table 7) DACs. See “Configuring the device” Section for details.
AMD mode. Not applicable. Needs to be shorted to SGND.
Over current set pin.
Connect to SGND through a R
also a C
capacitor to set a delay for the OCP intervention.
OCSET
resistor to set the OCP threshold. Connect
OCSET
See “Over current protection” Section for details.
Connect to the negative side of the load to perform remote sense.
See “Layout guidelines” Section for proper layout of this connection.
Oscillator pin.
It allows programming the switching frequency F
of each channel: the
SW
equivalent switching frequency at the load side results in being multiplied by the
phase number N.
Frequency is programmed according to the resistor connected from the pin vs.
SGND or VCC with a gain of 8 kHz/µA (see relevant section for details).
Leaving the pin floating programs a switching frequency of 200kHz per phase.
The pin is forced high (5 V) to signal an OVP FAULT: to recover from this
condition, cycle VCC or the OUTEN pin. See “Oscillator” Section for details.
VID7 - Intel mode. See VID5 to VID0 section.
DVID - AMD mode. DVID output.
CMOS output pulled high when the controller is performing a D-VID transition
(with 32 clock cycle delay after the transition has finished). See “Dynamic VID
transitions” Section Section for details.
Intel mode. See VID5 to VID0 section.
AMD mode. Not applicable. Needs to be shorted to SGND.
9/64
Pin settings L6713A
Table 2. Pin description (continued)
N° Pin Function
Intel mode. Voltage identification pins (also applies to VID6, VID7).
Internally pulled up by 25 µA to 5 V, connect to SGND to program a '0' or leave
floating to program a '1'.
They allow programming output voltage as specified in Tab l e 7 and Tab l e 8
according to VID_SEL status. OVP and UVP protection comes as a
40 to 45VID5 to
VID0
SS_END/
46
PGOOD
consequence of the programmed code (See Table 12).
AMD mode. Voltage identification pins.
Internally pulled down by 12.5 µA, leave floating to program a '0' while pull up to
more than 1.4 V to program a '1'.
They allow programming the output voltage as specified in Ta bl e 1 0 (VID7
doesn’t care). OVP and UVP protection comes as a consequence of the
programmed code (See Table 12).
Note. VID6 not used, need to be shorted to SGND.
SSEND - Intel mode. soft-start end signal.
Open drain output sets free after SS has finished and pulled low when
triggering any protection. Pull up to a voltage lower than 5 V (typ), if not used it
can be left floating.
PGOOD - AMD mode.
Open drain output set free after SS has finished and pulled low when VSEN is
lower than the relative threshold. Pull up to a voltage lower than 5 V (typ), if not
used it can be left floating.
Voltage regulator hot. Over temperature alarm signal.
47 VR_HOT
Open drain output, set free when TM overcomes the alarm threshold.
Thermal monitoring output enabled if Vcc > UVLO
See “Thermal monitor” Section for details and typical connections.
Voltage regulator fan. Over temperature warning signal.
48 VR_FAN
Open drain output, set free when TM overcomes the warning threshold.
Thermal monitoring output enabled if Vcc > UVLO
See “Thermal monitor” Section for details and typical connections.
Thermal monitor input.
49 TM
It senses the regulator temperature through apposite network and drives
VR_FAN and VR_HOT accordingly. Short TM pin to SGND if not used.
See “Thermal monitor” Section for details and typical connections.
50 SGND
All the internal references are referred to this pin. Connect to the PCB signal
Ground.
51 N.C. Not internally connected.
52 N.C. Not internally connected.
53 N.C. Not internally connected.
Channel 2 LS driver return path. Connect to power ground plane.
54 PGND2
It must be connected to power ground plane also when using 2-phase
operation.
Channel 2 LS driver output. A small series resistor helps in reducing device-
55 LGATE2
dissipated power.
Leave floating when using 2 phase operation.
VCC.
VCC.
10/64
L6713A Pin settings
Table 2. Pin description (continued)
N° Pin Function
Channel 2 LS driver supply.
It must be connected to others VCCDRx pins also when using 2-phase
56 VCCDR2
57 VCCDR3
operation.
LS driver supply can range from 5 Vbus up to 12 Vbus, filter with 1 µF MLCC
cap vs. PGND2.
Channel 3 LS driver supply.
It must be connected to others VCCDRx pins.
LS driver supply can range from 5 Vbus up to 12 Vbus, filter with 1 µF MLCC
cap vs. PGND3.
58 LGATE3
59 PGND3 Channel 3 LS driver return path. Connect to power ground plane.
60 PGND1 Channel 1 LS driver return path. Connect to power ground plane.
61 LGATE1
62 VCCDR1
63 PHASE1
64 N.C. Not internally connected.
PA D
Thermal
pad
Channel 3 LS driver output. A small series resistor helps in reducing devicedissipated power.
Channel 1 LS driver output. A small series resistor helps in reducing devicedissipated power.
Channel 1 LS driver supply.
It must be connected to others VCCDRx pins.
LS driver supply can range from 5 Vbus up to 12 Vbus, filter with 1 µF MLCC
cap vs. PGND1.
Channel 1 HS driver return path.
It must be connected to the HS1 MOSFET source and provides return path for
the HS driver of channel 1.
Thermal pad connects the silicon substrate and makes good thermal contact
with the PCB to dissipate the power necessary to drive the external MOSFETs.
Connect to the PGND plane with several VIAs to improve thermal conductivity.
11/64
Electrical data L6713A
3 Electrical data
3.1 Maximum ratings
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
V
V
BOOTx
V
UGATEx
V
, V
CC
- V
CC
V
PHASEx
CCDRx
- V
- V
BOOTx
PHASEx
PHASEx
to PGNDx 15 V
Boot voltage 15 V
15 V
7.5 V
LGATEx, PHASEx, to PGNDx -0.3 to V
+ 0.3 V
CC
VID0 to VID7, VID_SEL -0.3 to 5 V
All other pins to PGNDx -0.3 to 7 V
Static condition to PGNDx,
VCC = 14 V, BOOTx = 7 V,
-7.5 V
PHASEx = -7.5 V
Positive peak voltage to PGNDx;
T < 20 ns @ 600 kHz
26 V
3.2 Thermal data
Table 4. Thermal data
Symbol Parameter Value Unit
R
T
T
P
MAX
STG
T
Thermal resistance junction to ambient
thJA
(Device soldered on 2s2p PC board)
Maximum junction temperature 150 °C
Storage temperature range -40 to 150 °C
Junction temperature range 0 to 125 °C
J
Maximum power dissipation at TA = 25 °C 2.5 W
TOT
40 °C/W
12/64
L6713A Electrical characteristics
4 Electrical characteristics
V
= 12 V ± 15 %, TJ = 0 °C to 70 °C, unless otherwise specified
CC
Table 5. Electrical characteristics
Symbol Parameter Test condition Min. Typ. Max. Unit
Supply current
I
CC
I
CCDRx
I
BOOTx
VCC supply current
VCCDRx supply current LGATEx = OPEN; VCCDRx = 12 V 1 mA
BOOTx supply current
Power-ON
VCC turn-ON VCC Rising; VCCDRx = 5 V 8.9 9.3 V
UVLO
VCC
VCC turn-OFF VCC Falling; VCCDRx = 5 V 7.3 7.7 V
VCCDR turn-ON VCCDRx Rising; VCC = 12 V 4.5 4.8 V
UVLO
VCCDR
VCCDR turn-OFF VCCDRx Falling; VCC = 12 V 3.9 4.3 V
Pre-OVP turn-ON VCC Rising; VCCDRx = 5 V 3.6 4.2 V
UVLO
OVP
Pre-OVP turn-OFF VCC Falling; VCCDRx = 5 V 3.05 3.3 V
Oscillator and inhibit
F
OSC
T
1
T
2
T
3
Main oscillator accuracy
SS delay time Intel mode 1 ms
SS time T2 Intel mode; R
SS time T3 Intel mode 50 μs
Output enable intel mode
HGATEx and LGATEx = OPEN
VCCDRx = BOOTx = 12 V
HGATEx = OPEN; PHASEx to
PGNDx VCC = BOOTx = 12 V
OSC = OPEN
OSC = OPEN; T
= 0 °C to 125 °C
J
= 25 kΩ 500 μs
SSOSC
180
175
17 mA
0.75 mA
200 220
225
kHz
Rising thresholds voltage 0.80 0.85 0.90 V
Hysteresis 100 mV
OUTEN
Input low 0.80 V
Output enable AMD mode
Input high 1.40 V
OUTEN pull-up current OUTEN to SGND 12.5 μA
ΔV
OSC
PWMx ramp amplitude 3 V
FAULT Voltage at pin OSC OVP active 5 V
13/64
Electrical characteristics L6713A
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
Reference and DAC
Intel mode
VID = 1.000 V to VID = 1.600 V
FB = VOUT; FBG = GNDOUT
k
VID
Output voltage accuracy
AMD mode
VID = 1.000 V to VID = 1.550 V
FB = VOUT; FBG = GNDOUT
-0.5 - 0.5 %
-0.6 - 0.6 %
V
BOOT
Boot voltage Intel mode 1.081 V
VID pull-up current Intel mode; VIDx to SGND 25 μA
I
VID
VID
VID pull-down current AMD mode; VIDx to 5.4 V 12.5 μA
Intel mode; Input low
IL
AMD mode; Input low
0.3
0.8
VID thresholds
VID
IH
VID_SEL
VID_SEL threshold
(Intel mode)
Intel mode; Input high
AMD mode; Input high
Input low
Input high 0.8
0.8
1.35
0.3
VID_SEL pull-up current VIDSEL to SGND 12.5 μA
Error amplifier
A
0
EA DC gain 80 dB
SR EA slew rate COMP = 10 pF to SGND 20 V/μs
Differential current sensing and offset
I
CSx+
I
INFOxIAVG
--------------------------------- ---------
I
AVG
V
OCTH
Bias current Inductor sense 0 μA
–
Current sense mismatch Rg = 1 kΩ; I
Over current threshold V
(OCP) 1.215 1.240 1.265 V
OCSET
= 25 μA-3-3%
INFOx
Rg = 1 kΩ
K
IOCSET
k
IDROOP
I
OFFSET
OCSET current accuracy
Droop current deviation from
nominal value
2-PHASE, I
3-PHASE, I
Rg = 1kΩ
2-PHASE, I
3-PHASE, I
OCSET
OCSET
DROOP
DROOP
= 60 μA;
= 90 μA;
= 0 to 40 μA;
= 0 to 60 μA;
-5 - 5 %
-1 - 1 μA
Offset current VSEN = 0.500 V to 1.600 V 90 100 110 μA
Gate driver
V
V
V
t
RISE_UGATEx
I
UGATEx
R
UGATEx
HS rise time
HS source current BOOTx - PHASEx = 10 V 2 A
HS sink resistance BOOTx - PHASEx = 12 V 1.5 2 2.5 Ω
BOOTx - PHASEx = 10 V;
C
to PHASEx = 3.3 nF
UGATEx
14/64
15 30 ns
L6713A Electrical characteristics
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
t
RISE_LGATEx
I
LGATEx
R
LGATEx
LS rise time
LS source current VCCDRx = 10 V 1.8 A
LS sink resistance VCCDRx = 12 V 0.7 1.1 1.5 Ω
VCCDRx = 10 V;
C
to PGNDx = 5.6 nF
LGATEx
30 55 ns
Protections
1.300 V
OVP
Over voltage protection
(VSEN rising)
Intel mode; Before V
BOOT
Intel mode; Above VID 150 175 200 mV
AMD mode 1.700 1.740 1.780 V
current OVP = SGND 11.5 12.5 13.5 μA
I
Program-
mable OVP
Pre-OVP
OVP
Comparator offset voltage OVP = 1.8 V -20 0 20 mV
Preliminary over voltage
protection
UVLO
VCC > UVLO
SGND
< VCC < UVLO
OVP
VCC
VCC
& OUTEN =
1.800 V
Hysteresis 350 mV
UVP Under voltage protection VSEN falling; Below VID -750 mV
PGOOD PGOOD threshold
V
SSEND/
PGOOD
SSEND / PGOOD
voltage low
AMD mode;
VSEN falling; Below VID
I = -4 mA 0.4 V
-300
mV
Thermal monitor
TM warning (VR_FAN) V
V
TM
TM alarm (VR_HOT) V
TM hysteresis 100 mV
V
VR_HOT
V
VR_FAN
VR_HOT voltage low;
;
VR_FAN voltage low
rising 3.2 V
TM
rising 3.420 3.6 3.770 V
TM
I = -4 mA
0.4
0.4
V
V
15/64
VID Tables L6713A
5 VID Tables
5.1 Mapping for the Intel VR11 mode
Table 6. Voltage identification (VID) mapping for Intel VR11 mode
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
800 mV 400 mV 200 mV 100 mV 50 mV 25 mV 12.5 mV 6.25 mV
5.2 Voltage identification (VID) for Intel VR11 mode
Table 7. Voltage identification (VID) for Intel VR11 mode (See Note)
Output
HEX code
0 0 OFF 4 0 1.21250 8 0 0.81250 C 0 0.41250
0 1 OFF 4 1 1.20625 8 1 0.80625 C 1 0.40625
0 2 1.60000 4 2 1.20000 8 2 0.80000 C 2 0.40000
0 3 1.59375 4 3 1.19375 8 3 0.79375 C 3 0.39375
0 4 1.58750 4 4 1.18750 8 4 0.78750 C 4 0.38750
0 5 1.58125 4 5 1.18125 8 5 0.78125 C 5 0.38125
0 6 1.57500 4 6 1.17500 8 6 0.77500 C 6 0.37500
0 7 1.56875 4 7 1.16875 8 7 0.76875 C 7 0.36875
0 8 1.56250 4 8 1.16250 8 8 0.76250 C 8 0.36250
0 9 1.55625 4 9 1.15625 8 9 0.75625 C 9 0.35625
0 A 1.55000 4 A 1.15000 8 A 0.75000 C A 0.35000
0 B 1.54375 4 B 1.14375 8 B 0.74375 C B 0.34375
0 C 1.53750 4 C 1.13750 8 C 0.73750 C C 0.33750
0 D 1.53125 4 D 1.13125 8 D 0.73125 C D 0.33125
0 E 1.52500 4 E 1.12500 8 E 0.72500 C E 0.32500
0 F 1.51875 4 F 1.11875 8 F 0.71875 C F 0.31875
1 0 1.51250 5 0 1.11250 9 0 0.71250 D 0 0.31250
voltage
(1)
HEX code
Output
voltage
(1)
HEX code
Output
voltage
(1)
HEX code
Output
voltage
(1)
1 1 1.50625 5 1 1.10625 9 1 0.70625 D 1 0.30625
1 2 1.50000 5 2 1.10000 9 2 0.70000 D 2 0.30000
1 3 1.49375 5 3 1.09375 9 3 0.69375 D 3 0.29375
1 4 1.48750 5 4 1.08750 9 4 0.68750 D 4 0.28750
1 5 1.48125 5 5 1.08125 9 5 0.68125 D 5 0.28125
1 6 1.47500 5 6 1.07500 9 6 0.67500 D 6 0.27500
16/64
L6713A VID Tables
Table 7. Voltage identification (VID) for Intel VR11 mode (See Note) (continued)
HEX code
Output
voltage
(1)
HEX code
Output
voltage
(1)
HEX code
Output
voltage
(1)
HEX code
Output
voltage
(1)
1 7 1.46875 5 7 1.06875 9 7 0.66875 D 7 0.26875
1 8 1.46250 5 8 1.06250 9 8 0.66250 D 8 0.26250
1 9 1.45625 5 9 1.05625 9 9 0.65625 D 9 0.25625
1 A 1.45000 5 A 1.05000 9 A 0.65000 D A 0.25000
1 B 1.44375 5 B 1.04375 9 B 0.64375 D B 0.24375
1 C 1.43750 5 C 1.03750 9 C 0.63750 D C 0.23750
1 D 1.43125 5 D 1.03125 9 D 0.63125 D D 0.23125
1 E 1.42500 5 E 1.02500 9 E 0.62500 D E 0.22500
1 F 1.41875 5 F 1.01875 9 F 0.61875 D F 0.21875
2 0 1.41250 6 0 1.01250 A 0 0.61250 E 0 0.21250
2 1 1.40625 6 1 1.00625 A 1 0.60625 E 1 0.20625
2 2 1.40000 6 2 1.00000 A 2 0.60000 E 2 0.20000
2 3 1.39375 6 3 0.99375 A 3 0.59375 E 3 0.19375
2 4 1.38750 6 4 0.98750 A 4 0.58750 E 4 0.18750
2 5 1.38125 6 5 0.98125 A 5 0.58125 E 5 0.18125
2 6 1.37500 6 6 0.97500 A 6 0.57500 E 6 0.17500
2 7 1.36875 6 7 0.96875 A 7 0.56875 E 7 0.16875
2 8 1.36250 6 8 0.96250 A 8 0.56250 E 8 0.16250
2 9 1.35625 6 9 0.95625 A 9 0.55625 E 9 0.15625
2 A 1.35000 6 A 0.95000 A A 0.55000 E A 0.15000
2 B 1.34375 6 B 0.94375 A B 0.54375 E B 0.14375
2 C 1.33750 6 C 0.93750 A C 0.53750 E C 0.13750
2 D 1.33125 6 D 0.93125 A D 0.53125 E D 0.13125
2 E 1.32500 6 E 0.92500 A E 0.52500 E E 0.12500
2 F 1.31875 6 F 0.91875 A F 0.51875 E F 0.11875
3 0 1.31250 7 0 0.91250 B 0 0.51250 F 0 0.11250
3 1 1.30625 7 1 0.90625 B 1 0.50625 F 1 0.10625
3 2 1.30000 7 2 0.90000 B 2 0.50000 F 2 0.10000
3 3 1.29375 7 3 0.89375 B 3 0.49375 F 3 0.09375
3 4 1.28750 7 4 0.88750 B 4 0.48750 F 4 0.08750
3 5 1.28125 7 5 0.88125 B 5 0.48125 F 5 0.08125
3 6 1.27500 7 6 0.87500 B 6 0.47500 F 6 0.07500
3 7 1.26875 7 7 0.86875 B 7 0.46875 F 7 0.06875
17/64
VID Tables L6713A
Table 7. Voltage identification (VID) for Intel VR11 mode (See Note) (continued)
HEX code
Output
voltage
(1)
HEX code
Output
voltage
(1)
HEX code
Output
voltage
(1)
HEX code
Output
voltage
(1)
3 8 1.26250 7 8 0.86250 B 8 0.46250 F 8 0.06250
3 9 1.25625 7 9 0.85625 B 9 0.45625 F 9 0.05625
3 A 1.25000 7 A 0.85000 B A 0.45000 F A 0.05000
3 B 1.24375 7 B 0.84375 B B 0.44375 F B 0.04375
3 C 1.23750 7 C 0.83750 B C 0.43750 F C 0.03750
3 D 1.23125 7 D 0.83125 B D 0.43125 F D 0.03125
3 E 1.22500 7 E 0.82500 B E 0.42500 F E OFF
3 F 1.21875 7 F 0.81875 B F 0.41875 F F OFF
1. According to VR11 specs, the device automatically regulates output voltage 19 mV lower to avoid any
external offset to modify the built-in 0.5 % accuracy improving TOB performances. Output regulated
voltage is than what extracted from the table lowered by 19 mV built-in offset.
5.3 Voltage identifications (VID) for Intel VR10 mode + 6.25 mV
(VID7 does not care)
Table 8. Voltage identifications (VID) for Intel VR10 mode + 6.25 mV (See Note)
VID4VID3VID2VID1VID0VID5VID
6
Output
voltage
(1)
VID4VID3VID2VID1VID0VID5VID
6
Output
voltage
(1)
01010111.60000 11010111.20000
01010101.59375 11010101.19375
01011011.58750 11011011.18750
01011001.58125 11011001.18125
01011111.57500 11011111.17500
01011101.56875 11011101.16875
01100011.56250 11100011.16250
01100001.55625 11100001.15625
01100111.55000 11100111.15000
01100101.54375 11100101.14375
01101011.53750 11101011.13750
01101001.53125 11101001.13125
01101111.52500 11101111.12500
01101101.51875 11101101.11875
01110011.51250 11110011.11250
01110001.50625 11110001.10625
18/64
L6713A VID Tables
Table 8. Voltage identifications (VID) for Intel VR10 mode + 6.25 mV (See Note)
VID4VID3VID2VID1VID0VID5VID
6
Output
voltage
(1)
VID4VID3VID2VID1VID0VID5VID
6
Output
voltage
(1)
01110111.50000 11110111.10000
01110101.49375 11110101.09375
01111011.48750 1111101 OFF
01111001.48125 1111100 OFF
01111111.47500 1111111 OFF
01111101.46875 1111110 OFF
10000011.46250 00000011.08750
10000001.45625 00000001.08125
10000111.45000 00000111.07500
10000101.44375 00000101.06875
10001011.43750 00001011.06250
10001001.43125 00001001.05625
10001111.42500 00001111.05000
10001101.41875 00001101.04375
10010011.41250 00010011.03750
10010001.40625 00010001.03125
10010111.40000 00010111.02500
10010101.39375 00010101.01875
10011011.38750 00011011.01250
10011001.38125 00011001.00625
10011111.37500 00011111.00000
10011101.36875 00011100.99375
10100011.36250 00100010.98750
10100001.35625 00100000.98125
10100111.35000 00100110.97500
10100101.34375 00100100.96875
10101011.33750 00101010.96250
10101001.33125 00101000.95625
10101111.32500 00101110.95000
10101101.31875 00101100.94375
10110011.31250 00110010.93750
10110001.30625 00110000.93125
10110111.30000 00110110.92500
19/64
VID Tables L6713A
Table 8. Voltage identifications (VID) for Intel VR10 mode + 6.25 mV (See Note)
6
Output
voltage
(1)
VID4VID3VID2VID1VID0VID5VID
VID4VID3VID2VID1VID0VID5VID
10110101.29375 00110100.91875
10111011.28750 00111010.91250
10111001.28125 00111000.90625
10111111.27500 00111110.90000
10111101.26875 00111100.89375
11000011.26250 01000010.88750
11000001.25625 01000000.88125
11000111.25000 01000110.87500
11000101.24375 01000100.86875
11001011.23750 01001010.86250
11001001.23125 01001000.85625
11001111.22500 01001110.85000
11001101.21875 01001100.84375
11010011.21250 01010010.83750
11010001.20625 01010000.83125
1. According to VR10.x specs, the device automatically regulates output voltage 19 mV lower to avoid any
external offset to modify the built-in 0.5 % accuracy improving TOB performances. Output regulated
voltage is than what extracted from the table lowered by 19mVbuilt-in offset. VID7 doesn’t care.
6
Output
voltage
(1)
5.4 Mapping for the AMD 6 bit mode
Table 9. Voltage identifications (VID) mapping for AMD 6 bit mode
VID4 VID3 VID2 VID1 VID0
400 mV 200 mV 100 mV 50 mV 25 mV
5.5 Voltage identifications (VID) codes for AMD 6 bit mode
Table 10. Voltage identifications (VID) codes for AMD 6 bit mode (See Note)
VID5 VID4 VID3 VID2 VID1 VID0
0000001.5500 1 000000.7625
0000011.5250 1 000010.7500
0000101.5000 1 000100.7375
0000111.4750 1 000110.7250
20/64
Output
voltage
VID5 VID4 VID3 VID2 VID1 VID0
(1)
Output
voltage
(1)
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