ST L6712, L6712A User Manual

L6712

L6712A

TWO-PHASE INTERLEAVED DC/DC CONTROLLER

1 Features

■2 PHASE OPERATION WITH SYNCHRONOUS RECTIFIER CONTROL

■ULTRA FAST LOAD TRANSIENT RESPONSE

■INTEGRATED HIGH CURRENT GATE DRIVERS: UP TO 2A GATE CURRENT

■3 BIT PROGRAMMABLE OUTPUT FROM

0.900V TO 3.300V OR WITH EXTERNAL REF.

■±0.9% OUTPUT VOLTAGE ACCURACY

■3mA CAPABLE AVAILABLE REFERENCE

■INTEGRATED PROGRAMMABLE REMOTE SENSE AMPLIFIER

■PROGRAMMABLE DROOP EFFECT

■10% ACTIVE CURRENT SHARING ACCURACY

■DIGITAL 2048 STEP SOFT-START

■CROWBAR LATCHED OVERVOLTAGE PROT.

■NON-LATCHED UNDERVOLTAGE PROT.

■OVERCURRENT PROTECTION REALIZED USING THE LOWER MOSFET'S RdsON OR A SENSE RESISTOR

■OSCILLATOR EXTERNALLY ADJUSTABLE AND INTERNALLY FIXED AT 150kHZ

■POWER GOOD OUTPUT AND INHIBIT FUNCTION

■PACKAGES: SO-28 & VFQFPN-36

Figure 1. Packages

SO28

VFQFPN-36 (6x6x1.0mm)

Table 1. Order Codes

	Package	Tube	Tape & Reel
	SO	L6712D,	L6712DTR,
		L6712AD	L6712ADTR
	VFQFPN	L6712Q,	L6712QTR,
		L6712AQ	L6712AQTR

optimized for high current DC/DC applications.

Output voltage can be programmed through the integrated DAC from 0.900V to 3.300V; programming the "111" code, an external reference from 0.800V to 3.300V is used for the regulation.

Programmable Remote Sense Amplifier avoids use of external resistor divider and recovers losses along distribution line.

1.1 Applications

■HIGH CURRENT DC/DC CONVERTERS

■DISTRIBUTED POWER SUPPLY

2 Description

The device implements a dual-phase step-down controller with a 180 phase-shift between each phase

The device assures a fast protection against load over current and Over / Under voltage.An internal crowbar is provided turning on the low side mosfet if Over-voltage is detected.

Output current is limited working in Constant Current mode: when Under Voltage is detected, the device resets, restarting operation.

	Rev. 3
June 2005	1/29

L6712A L6712

Figure 2. Block Diagram

			OSC / INH			SGND			VCCDR
											BOOT1
	BAND-GAP									HS	UGATE1
	REFERENCE		PHASE
PGOOD						PWM1					PHASE1
			2
			LOGIC ANDOSCILLATOR		VCC	CURRENT CORRECTION	CH1	ADAPTIVEANTI	CONDUCTIONCROSS	LS	LGATE1
							OCP
VID2					VCCDR		PWMLOGIC				ISEN1
VID1	DAC	PROTECTIONS
VID0						TOTAL	CURRENT				PGNDS1
			CH1 OCP	CH2 OCP		CURRENT	READING
						CURRENT AVG					PGND
	DIGITAL						CURRENT				PGNDS2
	SOFT-START						READING
			VPROG								ISEN2
						CURRENT CORRECTION			CROSS CONDUCTION	LS	LGATE2
REF_IN/OUT							CH2
								ADAPTIVE ANTI
							OCP
FBG			DROOP				LOGIC PWM				PHASE2
			I
FBR						PWM2
		FB START								HS
											UGATE2
	REMOTE
	AMPLIFIER	I					Vcc
					ERROR						BOOT2
					AMPLIFIER
	VSEN		DROOP FB		COMP		Vcc

Table 2. Absolute Maximum Ratings

	Symbol	Parameter	Value	Unit
	VCC, VCCDR	To PGND	15	V
	VBOOT-VPHASE	Boot Voltage	15	V
	VUGATE1-VPHASE1		15	V
	VUGATE2-VPHASE2
		LGATE1, PHASE1, LGATE2, PHASE2 to PGND	-0.3 to Vcc+0.3	V
		VID0 to VID2	-0.3 to 5	V
		All other pins to PGND	-0.3 to 7	V
	VPHASEx	Sustainable Peak Voltage. T<20ns @ 600kHz	26	V
	UGATEX Pins	Maximum Withstanding Voltage Range	±1500	V
		Test Condition: CDF-AEC-Q100-002”Human Body Model”
	OTHER PINS		±2000	V
		Acceptance Criteria: “Normal Performance”

Table 3. Thermal Data

Symbol	Parameter	SO28	VFQFPN36	Unit
Rthj-amb	Thermal Resistance Junction to Ambient	60	30	°C/W
	4 layer PCB (2s2p)
Tmax	Maximum junction temperature	150	150	°C
Tstg	Storage temperature range	-40 to 150	-40 to 150	°C
Tj	Junction Temperature Range	-40 to 125	-40 to 125	°C
PMAX	Max power dissipation at Tamb = 25°C	2	3.5	W

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L6712A L6712

Figure 3. Pin Connection (Top view)

LGATE1	1	28	PGND
VCCDR	2	27	LGATE2
PHASE1	3	26	PHASE2
UGATE1	4	25	UGATE2
BOOT1	5	24	BOOT2
VCC	6	23	PGOOD
SGND	7	22	VID2
COMP	8	21	VID1
FB	9	20	VID0
DROOP	10	19	FBR
REF_IN/OUT	11	18	FBG
VSEN	12	17	OSC/INH/FAULT
ISEN1	13	16	ISEN2
PGNDS1	14	15	PGNDS2

SO28

	OT2OB	N.C.	GPOOD	VID2	VID1	VID0	FBR	FBG	N.C.
	27	26	25	24	23	22	21	20	19
UGATE2	28								18	OSC
PHASE2	29								17	N.C.
LGATE2	30								16	ISEN2
PGND	31								15	PGNDS2
PGND	32								14	PGNDS1
LGATE1	33								13	ISEN1
VCCDR	34								12	VSEN
PHASE1	35								11	REF_IN/OUT
UGATE1	36								10	N.C.
	1	2	3	4	5	6	7	8	9
	N.C	BOOT1	N.C.	VCC	SGND	SGND	COMP	FB	DROOP

VFQFPN-36

Corner Pin internally connected to the Exposed Pad.

Table 4. Electrical Characteristcs

(VCC = 12V±10%, TJ = 0°C to 70°C unless otherwise specified)

Symbol	Parameter	Test Condition	Min.	Typ.	Max.	Unit
Vcc SUPPLY CURRENT
ICC	VCC supply current	HGATEx and LGATEx open	7.5	10	12.5	mA
		VCCDR=BOOTx=12V
ICCDR	VCCDR supply current	LGATEx open; VCCDR=12V	1.5	3	4	mA
IBOOTx	Boot supply current	HGATEx open; PHASEx to	0.5	1	1.5	mA
		PGND; VCC=BOOTx=12V
POWER-ON
	Turn-On VCC threshold	VCC Rising; VCCDR=5V	8.2	9.2	10.2	V
	Turn-Off VCC threshold	VCC Falling; VCCDR=5V	6.5	7.5	8.5	V
	Turn-On VCCDR	VCCDR Rising	4.2	4.4	4.6	V
	Threshold	VCC=12V
	Turn-Off VCCDR	VCCDR Falling	4.0	4.2	4.4	V
	Threshold	VCC=12V
OSCILLATOR AND INHIBIT
fOSC	Initial Accuracy	OSC = OPEN	135	150	165	kHz
		OSC = OPEN; Tj=0°C to 125°C	127		178	kHz
INH	Inhibit threshold	ISINK=5mA	0.5			V
dMAX	Maximum duty cycle	L6712, OSC = OPEN: IDROOP=0	72	80	-	%
		OSC = OPEN; IDROOP=70µA	30	40	-	%
		L6712A, OSC = OPEN	85	90		%
∆Vosc	Ramp Amplitude			3		V
FAULT	Voltage at pin OSC	OVP Active	4.75	5.0	5.25	V

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L6712A L6712

Table 4. Electrical Characteristcs (continued)

(VCC = 12V±10%, TJ = 0°C to 70°C unless otherwise specified)

Symbol	Parameter	Test Condition	Min.	Typ.	Max.	Unit
REFERENCE AND DAC
(1)	Output Voltage Accuracy	VIDx See Table 5, VID ≠ “11x“	-0.9	-	0.9	%
VOUT
		VID = “110“	-1.0	-	1.0	%
REF_IN/OUT	Reference Accuracy	VIDx See Table 5, VID ≠ “111”	VOUT -5	VOUT	VOUT+5	mV
	Current Capability		3			mA
	Load Regulation	IREF = from 0 to 3mA			5.0	mV
VPROG / REF_IN/	Accuracy with external	VID=“111”;	-2.0		2.0	%
OUT	reference	REF_IN/OUT = 0.8V to 3.3V
REF_IN/OUT	Input impedance			400		kΩ
IVID	VID pull-up Current	VIDx =SGND		5		µA
VVID	VID pull-up Voltage	VIDx = OPEN		3		V
VIDIL	VID Input Levels	Input Low			0.4	V
VIDIH		Input High	1.0			V
ERROR AMPLIFIER
VOS_EA	Offset	FB = COMP	-5		5	mV
	DC Gain			80		dB
SR	Slew-Rate	COMP=10pF		15		V/µs
IFB_START	Start-up Current	FB=SGND; During Soft Start…	65			µA
DIFFERENTIAL AMPLIFIER (REMOTE BUFFER)
VOS_RA	Offset	VSEN = FBG	-8		8	mV
	DC Gain			80		dB
SR	Slew Rate	VSEN = 10pF		15		V/µs
DIFFERENTIAL CURRENT SENSING
IISEN1, IISEN2	Bias Current	ILOAD = 0	45	50	55	µA
IPGNDSx	Bias Current		45	50	55	µA
IISEN1, IISEN2	Bias Current at		80	85	90	µA
	Over Current Threshold
IDROOP	Droop Current	ILOAD ≤ 0		0	1	µA
		ILOAD = 100%	47.5	50	52.5	µA
GATE DRIVERS
tRISE HGATE	High Side	BOOTx-PHASEx=10V;		15	30	ns
	Rise Time	CHGATEx to PHASEx=3.3nF
IHGATEx	High Side	BOOTx-PHASEx=10V		2		A
	Source Current
RHGATEx	High Side	BOOTx-PHASEx=12V;	1.5	2	2.5	Ω
	Sink Resistance
tRISE LGATE	Low Side	VCCDR=10V;		30	55	ns
	Rise Time	CLGATEx to PGNDx=5.6nF
ILGATEx	Low Side	VCCDR=10V		1.8		A
	Source Current
RLGATEx	Low Side	VCCDR=12V	0.7	1.1	1.5	Ω
	Sink Resistance

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L6712A L6712

Table 4. Electrical Characteristcs (continued)

(VCC = 12V±10%, TJ = 0°C to 70°C unless otherwise specified)

Symbol	Parameter	Test Condition	Min.	Typ.	Max.	Unit
PROTECTIONS
PGOOD	Upper Threshold	VSEN Rising	108	112	115	%
	Lower Threshold	VSEN Falling	84	88	92	%
OVP	Over Voltage Threshold	VSEN Rising	115	122	130	%
UVP	Under Voltage Trip	VSEN Falling	55	60	65	%
VPGOODL	PGOOD Voltage Low	IPGOOD = -4mA			0.4	V
IPGOODH	PGOOD Leakage	VPGOOD = 5V			1	µA

Note: 1. Output voltage is specified including Error Amplifier Offset in the trimming chain. Remote Amplifier is not included.

Table 5. Voltage Identification (VID) Codes.

VID2	VID1	VID0	Output Voltage (V)
1	1	1	Ext. Ref.
1	1	0	0.900
1	0	1	1.250
1	0	0	1.500
0	1	1	1.715
0	1	0	1.800
0	0	1	2.500
0	0	0	3.300

Table 6. Pin Function

	N. (*)		Name	Description
SO		VFQFPN
1		33	LGATE1	Channel 1 LS driver output.
				A little series resistor helps in reducing device-dissipated power.
2		34	VCCDR	LS drivers supply: it can be varied from 5V to 12V buses.
				Filter locally with at least 1µF ceramic cap vs. PGND.
3		35	PHASE1	Channel 1 HS driver return path. It must be connected to the HS1 mosfet source
				and provides the return path for the HS driver of channel 1.
4		36	UGATE1	Channel 1 HS driver output.
				A little series resistor helps in reducing device-dissipated power.
5		2	BOOT1	Channel 1 HS driver supply. This pin supplies the relative high side driver.
				Connect through a capacitor (100nF typ.) to the PHASE1 pin and through a diode
				to VCC (cathode vs. boot).
6		4	VCC	Device supply voltage. The operative supply voltage is 12V ±10%.
				Filter with 1µF (Typ.) capacitor vs. GND.
7		5,6	SGND	All the internal references are referred to this pin. Connect it to the PCB signal
				ground.
8		7	COMP	This pin is connected to the error amplifier output and is used to compensate the
				control feedback loop.
9		8	FB	This pin is connected to the error amplifier inverting input and is used to
				compensate the control feedback loop.

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L6712A L6712

Table 6. Pin Function (continued)

	N. (*)		Name	Description
SO		VFQFPN
10		9	DROOP	A current proportional to the sum of the current sensed in both channel is
				sourced from this pin (50µA at full load, 70µA at the Constant Current threshold).
				Short to FB to implement the Droop effect: the resistor connected between FB
				and VSEN (or the regulated output) allows programming the droop effect.
				Otherwise, connect to GND directly or through a resistor (43kΩ max) and filter
				with 1nF capacitor. In this last case, current information can be used for other
				purposes.
11		11	REF_IN /	Reference input/output. Filter vs. GND with 1nF ceramic capacitor (a total of
			OUT	100nF capacitor is allowed).
				It reproduces the reference used for the regulation following VID code: when
				VID=111, the reference for the regulation must be connected on this pin.
				References ranging from 0.800V up to 3.300V can be accepted.
12		12	VSEN	Connected to the output voltage it is able to manage Over & Under-voltage
				conditions and the PGOOD signal. It is internally connected with the output of the
				Remote Sense Amplifier for Remote Sense of the regulated voltage.
				Connecting 1nF capacitor max vs. GND can help in reducing noise injection at
				this pin.
				If no Remote Sense is implemented, connect it directly to the regulated voltage in
				order to manage OVP, UVP and PGOOD.
13		13	ISEN1	Channel 1 current sense pin. The output current may be sensed across a sense
				resistor or across the low-side mosfet RdsON. This pin has to be connected to the
				low-side mosfet drain or to the sense resistor through a resistor Rg.
				The net connecting the pin to the sense point must be routed as close as
				possible to the PGNDS net in order to couple in common mode any picked-up
				noise.
14		14	PGNDS1	Channel 1 Power Ground sense pin. The net connecting the pin to the sense
				point must be routed as close as possible to the ISEN1 net in order to couple in
				common mode any picked-up noise.
15		15	PGNDS2	Channel 2 Power Ground sense pin. The net connecting the pin to the sense
				point must be routed as close as possible to the ISEN2 net in order to couple in
				common mode any picked-up noise.
16		16	ISEN2	Channel 2 current sense pin. The output current may be sensed across a sense
				resistor or across the low-side mosfet RdsON. This pin has to be connected to the
				low-side mosfet drain or to the sense resistor through a resistor Rg.
				The net connecting the pin to the sense point must be routed as close as
				possible to the PGNDS net in order to couple in common mode any picked-up
				noise.
17		18	OSC/INH	Oscillator pin.
			FAULT	It allows programming the switching frequency of each channel: the equivalent
				switching frequency at the load side results in being doubled.
				Internally fixed at 1.24V, the frequency is varied proportionally to the current sunk
				(forced) from (into) the pin with an internal gain of 6kHz/µA (See relevant section
				for details). If the pin is not connected, the switching frequency is 150kHz for
				each channel (300kHz on the load).
				The pin is forced high (5V Typ.) when an Over Voltage is detected; to recover
				from this condition, cycle VCC.
				Forcing the pin to a voltage lower than 0.6V, the device stops operation and
				enters the inhibit state.
18		20	FBG	Remote sense amplifier inverting input. It has to be connected to the negative
				side of the load to perform programmable remote sensing through apposite
				resistors (see relative section).
19		21	FBR	Remote sense amplifier non-inverting input. It has to be connected to the positive
				side of the load to perform programmable remote sensing through apposite
				resistors (see relative section).

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			L6712A L6712
Table 6. Pin Function (continued)
N. (*)		Name	Description
SO	VFQFPN
20 to 22	22 to 24	VID0-2	Voltage IDentification pins. These input are internally pulled-up. They are used to
			program the output voltage as specified in Table 1 and to set the PGOOD, OVP
			and UVP thresholds.
			Connect to GND to program a ‘0’ while leave floating to program a ‘1’.
23	25	PGOOD	This pin is an open collector output and is pulled low if the output voltage is not
			within the above specified thresholds and during soft-start.
			It cannot be pulled up above 5V. If not used may be left floating.
24	27	BOOT2	Channel 2 HS driver supply. This pin supplies the relative high side driver.
			Connect through a capacitor (100nF typ.) to the PHASE2 pin and through a diode
			to VCC (cathode vs. boot).
25	28	UGATE2	Channel 2 HS driver output.
			A little series resistor helps in reducing device-dissipated power.
26	29	PHASE2	Channel 2 HS driver return path. It must be connected to the HS2 mosfet source
			and provides the return path for the HS driver of channel 2.
27	30	LGATE2	Channel 2 LS driver output.
			A little series resistor helps in reducing device-dissipated power.
28	31,	PGND	LS drivers return path.
	32		This pin is common to both sections and it must be connected through the
			closest path to the LS mosfets source pins in order to reduce the noise injection
			into the device.
	PAD	THERMAL	Thermal pad connects the silicon substrate and makes a good thermal contact
		PAD	with the PCB to dissipate the power necessary to drive the external
			mosfets.Connect to the GND plane with several vias to improve thermal
			conductivity.

(*) Pin not reported in QFN column have to be considered as Not Connected, not internally bonded.

Figure 4. Reference Schematic

Vin
GNDin							CIN
			VCCDR			VCC
			BOOT1			BOOT2
		HS1	UGATE1			UGATE2	HS2
	L1		PHASE1			PHASE2	L2
		LS1	LGATE1			LGATE2	COUT	LOAD
							LS2
			ISEN1			ISEN2
			Rg				Rg
			PGNDS1		L6712	PGNDS2
			Rg	L6712A		PGND	Rg
S2
			VID2			PGOOD
S1								PGOOD
			VID1			COMP
S0
			VID0
			REF_IN/OUT				CF
						DROOP	RF
			OSC / INH
						FB
			SGND				RFB
						VSEN
				FBR	FBG
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L6712A L6712

3 Device Description

The device is an integrated circuit realized in BCD technology. It provides complete control logic and protections for a high performance dual-phase step-down converter optimized for high current DC/DC applications. It is designed to drive N-Channel Mosfets in a two-phase synchronous-rectified buck topology. A 180 deg phase shift is provided between the two phases allowing reduction in the input capacitor current ripple, reducing also the size and the losses. The output voltage of the converter can be precisely regulated, programming the VID pins, from 0.900 to 3.300V with a maximum tolerance of ±0.9% over temperature and line voltage variations. The programmable Remote Sense Amplifier avoids the use of external resistor divider allowing recovering drops across distribution lines and also adjusting output voltage to different values from the available reference. The device provides an average current-mode control with fast transient response. It includes a 150kHz free-running oscillator externally adjustable through a resistor. The error amplifier features a 15V/µs slew rate that permits high converter bandwidth for fast transient performances. Current information is read across the lower mosfets RdsON or across a sense resistor placed in series to the LS mos in fully differential mode. The current information corrects the PWM outputs in order to equalize the average current carried by each phase. Current sharing between the two phases is then limited at ±10% over static and dynamic conditions unless considering the sensing element spread. Droop effect can be programmed in order to minimize output filter and load transient response: the function can be disabled and the current information available on the pin can be used for other purposes. The device protects against Over-Current, with an OC threshold for each phase, entering in constant current mode. Since the current is read across the low side mosfets, the device keeps constant the bottom of the inductors current triangular waveform. When an Under Voltage is detected the device resets with all mosfets OFF and suddenly re-starts. The device also performs a crowbar Over-Voltage protection that immediately latches the operations turning ON the lower driver and driving high the FAULT pin.

3.1 OSCILLATOR

The switching frequency is internally fixed at 150kHz. Each phase works at the frequency fixed by the oscillator so that the resulting switching frequency at the load side results in being doubled.

The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the oscillator is typically 25µA (Fsw=150kHz) and may be varied using an external resistor (ROSC) connected between OSC pin and SGND or Vcc. Since the OSC pin is maintained at fixed voltage (Typ. 1.237V), the frequency is varied proportionally to the current sunk (forced) from (into) the pin considering the internal gain of 6KHz/µA.

In particular connecting it to SGND the frequency is increased (current is sunk from the pin), while connecting ROSC to Vcc=12V the frequency is reduced (current is forced into the pin), according to the following relationships:

ROSC vs. GND: FSW

=

150[KHz] +

1.237

6

kHz

7.422 106

---------------

----------

= 150[kHz] + -----------------------------[kHz]

ROSC

µA

ROSC[KΩ]

ROSC vs. 12V: FSW =

150[KHz]–

12–1.237

6

kHz

6.457 107

[kHz]

------------------------

----------µA

= 150[kHz] – -----------------------------

ROSC

ROSC[KΩ]

Forcing 25µA into this pin, the device stops switching because no current is delivered to the oscillator

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L6712A L6712

Figure 5. ROSC vs. Switching Frequency

	14000
12V	12000
	10000
) vs.
	8000
Rosc(K	6000
	4000
	2000
	0
	25	50	75	100	125	150

Frequency (kHz)

	800
GND	700
	600
)vs.	500
	400
Rosc(KΩ
	300
	200
	100
	0
	150	250	350	450	550	650

Frequency (kHz)

3.2 DIGITAL TO ANALOG CONVERTER AND REFERENCE

The built-in digital to analog converter allows the adjustment of the output voltage from 0.900V to 3.300V as shown in Figure 6. Different voltages can be reached simply changing the Remote Amplifier Gain that acts as a resistor divider (See relevant section).

The internal reference is trimmed during production process to have an output voltage accuracy of ±0.9% and a zero temperature coefficient around 70°C including also error amplifier offset compensation. It is programmed through the voltage identification (VID) pins. These are inputs of an internal DAC that is realized by means of a series of resistors providing a partition of the internal voltage reference. The VID code drives a multiplexer that select a voltage on a precise point of the divider (see Figure 6). The DAC output is delivered to an amplifier obtaining the VPROG voltage reference (i.e. the set-point of the error amplifier). Internal pull-ups are provided (realized with a 5µA current generator up to 3V typ.); in this way, to program a logic "1" it is enough to leave the pin floating, while to program a logic "0" it is enough to short the pin to SGND.

The device offers a bi-directional pin REF_IN/OUT: the internal reference used for the regulation is usually available on this pin with 3mA of maximum current capability except when VID code 111 is programmed; in this case the device accepts an external reference through the REF_IN/OUT pin and regulates on it. When external reference is used, it must range from 0.800V up to 3.300V to assure proper functionality of the device.

Figure 6 shows a block schematic of how the Reference for the regulation is managed when internal or external reference is used.

The voltage identification (VID) pin configuration or the external reference provided also sets the powergood thresholds (PGOOD) and the Over/Under voltage protection (OVP/UVP) thresholds.

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