L6712
L6712A
TWO-PHASE INTERLEAVED DC/DC CONTROLLER
■2 PHASE OPERATION WITH SYNCHRONOUS RECTIFIER CONTROL
■ULTRA FAST LOAD TRANSIENT RESPONSE
■INTEGRATED HIGH CURRENT GATE DRIVERS: UP TO 2A GATE CURRENT
■3 BIT PROGRAMMABLE OUTPUT FROM
0.900V TO 3.300V OR WITH EXTERNAL REF.
■±0.9% OUTPUT VOLTAGE ACCURACY
■3mA CAPABLE AVAILABLE REFERENCE
■INTEGRATED PROGRAMMABLE REMOTE SENSE AMPLIFIER
■PROGRAMMABLE DROOP EFFECT
■10% ACTIVE CURRENT SHARING ACCURACY
■DIGITAL 2048 STEP SOFT-START
■CROWBAR LATCHED OVERVOLTAGE PROT.
■NON-LATCHED UNDERVOLTAGE PROT.
■OVERCURRENT PROTECTION REALIZED USING THE LOWER MOSFET'S RdsON OR A SENSE RESISTOR
■OSCILLATOR EXTERNALLY ADJUSTABLE AND INTERNALLY FIXED AT 150kHZ
■POWER GOOD OUTPUT AND INHIBIT FUNCTION
■PACKAGES: SO-28 & VFQFPN-36
SO28
VFQFPN-36 (6x6x1.0mm)
Package |
Tube |
Tape & Reel |
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SO |
L6712D, |
L6712DTR, |
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L6712AD |
L6712ADTR |
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VFQFPN |
L6712Q, |
L6712QTR, |
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L6712AQ |
L6712AQTR |
optimized for high current DC/DC applications.
Output voltage can be programmed through the integrated DAC from 0.900V to 3.300V; programming the "111" code, an external reference from 0.800V to 3.300V is used for the regulation.
Programmable Remote Sense Amplifier avoids use of external resistor divider and recovers losses along distribution line.
■HIGH CURRENT DC/DC CONVERTERS
■DISTRIBUTED POWER SUPPLY
The device implements a dual-phase step-down controller with a 180 phase-shift between each phase
The device assures a fast protection against load over current and Over / Under voltage.An internal crowbar is provided turning on the low side mosfet if Over-voltage is detected.
Output current is limited working in Constant Current mode: when Under Voltage is detected, the device resets, restarting operation.
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Rev. 3 |
June 2005 |
1/29 |
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L6712A L6712
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OSC / INH |
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SGND |
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VCCDR |
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BOOT1 |
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BAND-GAP |
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HS |
UGATE1 |
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REFERENCE |
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PHASE |
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PGOOD |
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PWM1 |
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PHASE1 |
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LOGIC ANDOSCILLATOR |
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VCC |
CURRENT CORRECTION |
CH1 |
ADAPTIVEANTI |
CONDUCTIONCROSS |
LS |
LGATE1 |
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OCP |
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VID2 |
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VCCDR |
PWMLOGIC |
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ISEN1 |
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VID1 |
DAC |
PROTECTIONS |
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VID0 |
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TOTAL |
CURRENT |
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PGNDS1 |
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CH1 OCP |
CH2 OCP |
CURRENT |
READING |
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CURRENT AVG |
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PGND |
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DIGITAL |
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CURRENT |
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PGNDS2 |
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SOFT-START |
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READING |
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VPROG |
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ISEN2 |
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CURRENT CORRECTION |
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CROSS CONDUCTION |
LS |
LGATE2 |
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REF_IN/OUT |
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CH2 |
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ADAPTIVE ANTI |
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OCP |
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FBG |
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DROOP |
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LOGIC PWM |
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PHASE2 |
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I |
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FBR |
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PWM2 |
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FB START |
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HS |
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UGATE2 |
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REMOTE |
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AMPLIFIER |
I |
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Vcc |
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ERROR |
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BOOT2 |
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AMPLIFIER |
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VSEN |
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DROOP FB |
COMP |
Vcc |
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Symbol |
Parameter |
Value |
Unit |
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VCC, VCCDR |
To PGND |
15 |
V |
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VBOOT-VPHASE |
Boot Voltage |
15 |
V |
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VUGATE1-VPHASE1 |
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15 |
V |
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VUGATE2-VPHASE2 |
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LGATE1, PHASE1, LGATE2, PHASE2 to PGND |
-0.3 to Vcc+0.3 |
V |
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VID0 to VID2 |
-0.3 to 5 |
V |
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All other pins to PGND |
-0.3 to 7 |
V |
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VPHASEx |
Sustainable Peak Voltage. T<20ns @ 600kHz |
26 |
V |
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UGATEX Pins |
Maximum Withstanding Voltage Range |
±1500 |
V |
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Test Condition: CDF-AEC-Q100-002”Human Body Model” |
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OTHER PINS |
±2000 |
V |
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Acceptance Criteria: “Normal Performance” |
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Symbol |
Parameter |
SO28 |
VFQFPN36 |
Unit |
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Rthj-amb |
Thermal Resistance Junction to Ambient |
60 |
30 |
°C/W |
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4 layer PCB (2s2p) |
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Tmax |
Maximum junction temperature |
150 |
150 |
°C |
Tstg |
Storage temperature range |
-40 to 150 |
-40 to 150 |
°C |
Tj |
Junction Temperature Range |
-40 to 125 |
-40 to 125 |
°C |
PMAX |
Max power dissipation at Tamb = 25°C |
2 |
3.5 |
W |
2/29
L6712A L6712
LGATE1 |
1 |
28 |
PGND |
VCCDR |
2 |
27 |
LGATE2 |
PHASE1 |
3 |
26 |
PHASE2 |
UGATE1 |
4 |
25 |
UGATE2 |
BOOT1 |
5 |
24 |
BOOT2 |
VCC |
6 |
23 |
PGOOD |
SGND |
7 |
22 |
VID2 |
COMP |
8 |
21 |
VID1 |
FB |
9 |
20 |
VID0 |
DROOP |
10 |
19 |
FBR |
REF_IN/OUT |
11 |
18 |
FBG |
VSEN |
12 |
17 |
OSC/INH/FAULT |
ISEN1 |
13 |
16 |
ISEN2 |
PGNDS1 |
14 |
15 |
PGNDS2 |
SO28
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OT2OB |
N.C. |
GPOOD |
VID2 |
VID1 |
VID0 |
FBR |
FBG |
N.C. |
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27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
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UGATE2 |
28 |
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18 |
OSC |
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PHASE2 |
29 |
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17 |
N.C. |
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LGATE2 |
30 |
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16 |
ISEN2 |
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PGND |
31 |
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15 |
PGNDS2 |
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PGND |
32 |
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14 |
PGNDS1 |
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LGATE1 |
33 |
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13 |
ISEN1 |
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VCCDR |
34 |
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12 |
VSEN |
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PHASE1 |
35 |
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11 |
REF_IN/OUT |
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UGATE1 |
36 |
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10 |
N.C. |
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1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
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N.C |
BOOT1 |
N.C. |
VCC |
SGND |
SGND |
COMP |
FB |
DROOP |
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VFQFPN-36
Corner Pin internally connected to the Exposed Pad.
Table 4. Electrical Characteristcs
(VCC = 12V±10%, TJ = 0°C to 70°C unless otherwise specified)
Symbol |
Parameter |
Test Condition |
Min. |
Typ. |
Max. |
Unit |
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Vcc SUPPLY CURRENT |
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ICC |
VCC supply current |
HGATEx and LGATEx open |
7.5 |
10 |
12.5 |
mA |
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VCCDR=BOOTx=12V |
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ICCDR |
VCCDR supply current |
LGATEx open; VCCDR=12V |
1.5 |
3 |
4 |
mA |
IBOOTx |
Boot supply current |
HGATEx open; PHASEx to |
0.5 |
1 |
1.5 |
mA |
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PGND; VCC=BOOTx=12V |
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POWER-ON |
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Turn-On VCC threshold |
VCC Rising; VCCDR=5V |
8.2 |
9.2 |
10.2 |
V |
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Turn-Off VCC threshold |
VCC Falling; VCCDR=5V |
6.5 |
7.5 |
8.5 |
V |
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Turn-On VCCDR |
VCCDR Rising |
4.2 |
4.4 |
4.6 |
V |
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Threshold |
VCC=12V |
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Turn-Off VCCDR |
VCCDR Falling |
4.0 |
4.2 |
4.4 |
V |
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Threshold |
VCC=12V |
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OSCILLATOR AND INHIBIT |
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fOSC |
Initial Accuracy |
OSC = OPEN |
135 |
150 |
165 |
kHz |
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OSC = OPEN; Tj=0°C to 125°C |
127 |
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178 |
kHz |
INH |
Inhibit threshold |
ISINK=5mA |
0.5 |
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V |
dMAX |
Maximum duty cycle |
L6712, OSC = OPEN: IDROOP=0 |
72 |
80 |
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% |
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OSC = OPEN; IDROOP=70µA |
30 |
40 |
- |
% |
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L6712A, OSC = OPEN |
85 |
90 |
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% |
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∆Vosc |
Ramp Amplitude |
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3 |
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V |
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FAULT |
Voltage at pin OSC |
OVP Active |
4.75 |
5.0 |
5.25 |
V |
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3/29
L6712A L6712
Table 4. Electrical Characteristcs (continued)
(VCC = 12V±10%, TJ = 0°C to 70°C unless otherwise specified)
Symbol |
Parameter |
Test Condition |
Min. |
Typ. |
Max. |
Unit |
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REFERENCE AND DAC |
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(1) |
Output Voltage Accuracy |
VIDx See Table 5, VID ≠ “11x“ |
-0.9 |
- |
0.9 |
% |
VOUT |
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VID = “110“ |
-1.0 |
- |
1.0 |
% |
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REF_IN/OUT |
Reference Accuracy |
VIDx See Table 5, VID ≠ “111” |
VOUT -5 |
VOUT |
VOUT+5 |
mV |
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Current Capability |
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3 |
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mA |
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Load Regulation |
IREF = from 0 to 3mA |
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5.0 |
mV |
VPROG / REF_IN/ |
Accuracy with external |
VID=“111”; |
-2.0 |
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2.0 |
% |
OUT |
reference |
REF_IN/OUT = 0.8V to 3.3V |
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REF_IN/OUT |
Input impedance |
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400 |
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kΩ |
IVID |
VID pull-up Current |
VIDx =SGND |
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5 |
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µA |
VVID |
VID pull-up Voltage |
VIDx = OPEN |
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3 |
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V |
VIDIL |
VID Input Levels |
Input Low |
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0.4 |
V |
VIDIH |
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Input High |
1.0 |
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V |
ERROR AMPLIFIER |
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VOS_EA |
Offset |
FB = COMP |
-5 |
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5 |
mV |
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DC Gain |
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80 |
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dB |
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SR |
Slew-Rate |
COMP=10pF |
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15 |
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V/µs |
IFB_START |
Start-up Current |
FB=SGND; During Soft Start… |
65 |
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µA |
DIFFERENTIAL AMPLIFIER (REMOTE BUFFER) |
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VOS_RA |
Offset |
VSEN = FBG |
-8 |
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8 |
mV |
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DC Gain |
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80 |
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dB |
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SR |
Slew Rate |
VSEN = 10pF |
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15 |
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V/µs |
DIFFERENTIAL CURRENT SENSING |
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IISEN1, IISEN2 |
Bias Current |
ILOAD = 0 |
45 |
50 |
55 |
µA |
IPGNDSx |
Bias Current |
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45 |
50 |
55 |
µA |
IISEN1, IISEN2 |
Bias Current at |
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80 |
85 |
90 |
µA |
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Over Current Threshold |
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IDROOP |
Droop Current |
ILOAD ≤ 0 |
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0 |
1 |
µA |
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ILOAD = 100% |
47.5 |
50 |
52.5 |
µA |
GATE DRIVERS |
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tRISE HGATE |
High Side |
BOOTx-PHASEx=10V; |
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15 |
30 |
ns |
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Rise Time |
CHGATEx to PHASEx=3.3nF |
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IHGATEx |
High Side |
BOOTx-PHASEx=10V |
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A |
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Source Current |
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RHGATEx |
High Side |
BOOTx-PHASEx=12V; |
1.5 |
2 |
2.5 |
Ω |
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Sink Resistance |
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tRISE LGATE |
Low Side |
VCCDR=10V; |
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30 |
55 |
ns |
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Rise Time |
CLGATEx to PGNDx=5.6nF |
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ILGATEx |
Low Side |
VCCDR=10V |
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1.8 |
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A |
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Source Current |
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RLGATEx |
Low Side |
VCCDR=12V |
0.7 |
1.1 |
1.5 |
Ω |
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Sink Resistance |
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4/29
L6712A L6712
Table 4. Electrical Characteristcs (continued)
(VCC = 12V±10%, TJ = 0°C to 70°C unless otherwise specified)
Symbol |
Parameter |
Test Condition |
Min. |
Typ. |
Max. |
Unit |
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PROTECTIONS |
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PGOOD |
Upper Threshold |
VSEN Rising |
108 |
112 |
115 |
% |
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Lower Threshold |
VSEN Falling |
84 |
88 |
92 |
% |
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OVP |
Over Voltage Threshold |
VSEN Rising |
115 |
122 |
130 |
% |
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UVP |
Under Voltage Trip |
VSEN Falling |
55 |
60 |
65 |
% |
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VPGOODL |
PGOOD Voltage Low |
IPGOOD = -4mA |
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0.4 |
V |
IPGOODH |
PGOOD Leakage |
VPGOOD = 5V |
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1 |
µA |
Note: 1. Output voltage is specified including Error Amplifier Offset in the trimming chain. Remote Amplifier is not included.
VID2 |
VID1 |
VID0 |
Output Voltage (V) |
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1 |
1 |
1 |
Ext. Ref. |
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1 |
1 |
0 |
0.900 |
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1 |
0 |
1 |
1.250 |
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1 |
0 |
0 |
1.500 |
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0 |
1 |
1 |
1.715 |
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0 |
1 |
0 |
1.800 |
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0 |
0 |
1 |
2.500 |
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0 |
0 |
0 |
3.300 |
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Table 6. Pin Function
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N. (*) |
Name |
Description |
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SO |
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VFQFPN |
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1 |
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33 |
LGATE1 |
Channel 1 LS driver output. |
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A little series resistor helps in reducing device-dissipated power. |
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2 |
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34 |
VCCDR |
LS drivers supply: it can be varied from 5V to 12V buses. |
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Filter locally with at least 1µF ceramic cap vs. PGND. |
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3 |
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35 |
PHASE1 |
Channel 1 HS driver return path. It must be connected to the HS1 mosfet source |
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and provides the return path for the HS driver of channel 1. |
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4 |
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36 |
UGATE1 |
Channel 1 HS driver output. |
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A little series resistor helps in reducing device-dissipated power. |
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5 |
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2 |
BOOT1 |
Channel 1 HS driver supply. This pin supplies the relative high side driver. |
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Connect through a capacitor (100nF typ.) to the PHASE1 pin and through a diode |
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to VCC (cathode vs. boot). |
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6 |
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4 |
VCC |
Device supply voltage. The operative supply voltage is 12V ±10%. |
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Filter with 1µF (Typ.) capacitor vs. GND. |
7 |
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5,6 |
SGND |
All the internal references are referred to this pin. Connect it to the PCB signal |
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ground. |
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8 |
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7 |
COMP |
This pin is connected to the error amplifier output and is used to compensate the |
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control feedback loop. |
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9 |
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8 |
FB |
This pin is connected to the error amplifier inverting input and is used to |
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compensate the control feedback loop. |
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5/29
L6712A L6712
Table 6. Pin Function (continued)
|
N. (*) |
Name |
Description |
|
SO |
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VFQFPN |
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10 |
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9 |
DROOP |
A current proportional to the sum of the current sensed in both channel is |
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sourced from this pin (50µA at full load, 70µA at the Constant Current threshold). |
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Short to FB to implement the Droop effect: the resistor connected between FB |
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and VSEN (or the regulated output) allows programming the droop effect. |
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Otherwise, connect to GND directly or through a resistor (43kΩ max) and filter |
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with 1nF capacitor. In this last case, current information can be used for other |
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purposes. |
11 |
|
11 |
REF_IN / |
Reference input/output. Filter vs. GND with 1nF ceramic capacitor (a total of |
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OUT |
100nF capacitor is allowed). |
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It reproduces the reference used for the regulation following VID code: when |
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VID=111, the reference for the regulation must be connected on this pin. |
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References ranging from 0.800V up to 3.300V can be accepted. |
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12 |
|
12 |
VSEN |
Connected to the output voltage it is able to manage Over & Under-voltage |
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conditions and the PGOOD signal. It is internally connected with the output of the |
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Remote Sense Amplifier for Remote Sense of the regulated voltage. |
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Connecting 1nF capacitor max vs. GND can help in reducing noise injection at |
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this pin. |
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If no Remote Sense is implemented, connect it directly to the regulated voltage in |
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order to manage OVP, UVP and PGOOD. |
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13 |
|
13 |
ISEN1 |
Channel 1 current sense pin. The output current may be sensed across a sense |
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resistor or across the low-side mosfet RdsON. This pin has to be connected to the |
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low-side mosfet drain or to the sense resistor through a resistor Rg. |
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The net connecting the pin to the sense point must be routed as close as |
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possible to the PGNDS net in order to couple in common mode any picked-up |
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noise. |
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14 |
|
14 |
PGNDS1 |
Channel 1 Power Ground sense pin. The net connecting the pin to the sense |
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point must be routed as close as possible to the ISEN1 net in order to couple in |
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common mode any picked-up noise. |
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15 |
|
15 |
PGNDS2 |
Channel 2 Power Ground sense pin. The net connecting the pin to the sense |
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point must be routed as close as possible to the ISEN2 net in order to couple in |
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common mode any picked-up noise. |
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16 |
|
16 |
ISEN2 |
Channel 2 current sense pin. The output current may be sensed across a sense |
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resistor or across the low-side mosfet RdsON. This pin has to be connected to the |
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low-side mosfet drain or to the sense resistor through a resistor Rg. |
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The net connecting the pin to the sense point must be routed as close as |
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possible to the PGNDS net in order to couple in common mode any picked-up |
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noise. |
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17 |
|
18 |
OSC/INH |
Oscillator pin. |
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FAULT |
It allows programming the switching frequency of each channel: the equivalent |
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switching frequency at the load side results in being doubled. |
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Internally fixed at 1.24V, the frequency is varied proportionally to the current sunk |
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(forced) from (into) the pin with an internal gain of 6kHz/µA (See relevant section |
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for details). If the pin is not connected, the switching frequency is 150kHz for |
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each channel (300kHz on the load). |
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The pin is forced high (5V Typ.) when an Over Voltage is detected; to recover |
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from this condition, cycle VCC. |
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Forcing the pin to a voltage lower than 0.6V, the device stops operation and |
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enters the inhibit state. |
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18 |
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20 |
FBG |
Remote sense amplifier inverting input. It has to be connected to the negative |
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side of the load to perform programmable remote sensing through apposite |
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resistors (see relative section). |
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19 |
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21 |
FBR |
Remote sense amplifier non-inverting input. It has to be connected to the positive |
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side of the load to perform programmable remote sensing through apposite |
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resistors (see relative section). |
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6/29
|
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|
L6712A L6712 |
Table 6. Pin Function (continued) |
|||
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|
N. (*) |
Name |
Description |
|
SO |
VFQFPN |
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||
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20 to 22 |
22 to 24 |
VID0-2 |
Voltage IDentification pins. These input are internally pulled-up. They are used to |
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program the output voltage as specified in Table 1 and to set the PGOOD, OVP |
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and UVP thresholds. |
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Connect to GND to program a ‘0’ while leave floating to program a ‘1’. |
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23 |
25 |
PGOOD |
This pin is an open collector output and is pulled low if the output voltage is not |
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within the above specified thresholds and during soft-start. |
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It cannot be pulled up above 5V. If not used may be left floating. |
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24 |
27 |
BOOT2 |
Channel 2 HS driver supply. This pin supplies the relative high side driver. |
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Connect through a capacitor (100nF typ.) to the PHASE2 pin and through a diode |
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to VCC (cathode vs. boot). |
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25 |
28 |
UGATE2 |
Channel 2 HS driver output. |
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A little series resistor helps in reducing device-dissipated power. |
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26 |
29 |
PHASE2 |
Channel 2 HS driver return path. It must be connected to the HS2 mosfet source |
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and provides the return path for the HS driver of channel 2. |
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27 |
30 |
LGATE2 |
Channel 2 LS driver output. |
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A little series resistor helps in reducing device-dissipated power. |
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28 |
31, |
PGND |
LS drivers return path. |
|
32 |
|
This pin is common to both sections and it must be connected through the |
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closest path to the LS mosfets source pins in order to reduce the noise injection |
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into the device. |
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PAD |
THERMAL |
Thermal pad connects the silicon substrate and makes a good thermal contact |
|
|
PAD |
with the PCB to dissipate the power necessary to drive the external |
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mosfets.Connect to the GND plane with several vias to improve thermal |
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conductivity. |
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(*) Pin not reported in QFN column have to be considered as Not Connected, not internally bonded.
Vin |
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GNDin |
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CIN |
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VCCDR |
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VCC |
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BOOT1 |
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BOOT2 |
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HS1 |
UGATE1 |
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UGATE2 |
HS2 |
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||
|
L1 |
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PHASE1 |
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PHASE2 |
L2 |
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LS1 |
LGATE1 |
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LGATE2 |
COUT |
LOAD |
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LS2 |
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ISEN1 |
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ISEN2 |
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Rg |
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Rg |
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PGNDS1 |
|
L6712 |
PGNDS2 |
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Rg |
L6712A |
PGND |
Rg |
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S2 |
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VID2 |
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PGOOD |
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S1 |
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PGOOD |
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VID1 |
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COMP |
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S0 |
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VID0 |
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REF_IN/OUT |
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CF |
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DROOP |
RF |
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OSC / INH |
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FB |
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SGND |
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RFB |
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VSEN |
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FBR |
FBG |
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7/29 |
L6712A L6712
The device is an integrated circuit realized in BCD technology. It provides complete control logic and protections for a high performance dual-phase step-down converter optimized for high current DC/DC applications. It is designed to drive N-Channel Mosfets in a two-phase synchronous-rectified buck topology. A 180 deg phase shift is provided between the two phases allowing reduction in the input capacitor current ripple, reducing also the size and the losses. The output voltage of the converter can be precisely regulated, programming the VID pins, from 0.900 to 3.300V with a maximum tolerance of ±0.9% over temperature and line voltage variations. The programmable Remote Sense Amplifier avoids the use of external resistor divider allowing recovering drops across distribution lines and also adjusting output voltage to different values from the available reference. The device provides an average current-mode control with fast transient response. It includes a 150kHz free-running oscillator externally adjustable through a resistor. The error amplifier features a 15V/µs slew rate that permits high converter bandwidth for fast transient performances. Current information is read across the lower mosfets RdsON or across a sense resistor placed in series to the LS mos in fully differential mode. The current information corrects the PWM outputs in order to equalize the average current carried by each phase. Current sharing between the two phases is then limited at ±10% over static and dynamic conditions unless considering the sensing element spread. Droop effect can be programmed in order to minimize output filter and load transient response: the function can be disabled and the current information available on the pin can be used for other purposes. The device protects against Over-Current, with an OC threshold for each phase, entering in constant current mode. Since the current is read across the low side mosfets, the device keeps constant the bottom of the inductors current triangular waveform. When an Under Voltage is detected the device resets with all mosfets OFF and suddenly re-starts. The device also performs a crowbar Over-Voltage protection that immediately latches the operations turning ON the lower driver and driving high the FAULT pin.
The switching frequency is internally fixed at 150kHz. Each phase works at the frequency fixed by the oscillator so that the resulting switching frequency at the load side results in being doubled.
The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the oscillator is typically 25µA (Fsw=150kHz) and may be varied using an external resistor (ROSC) connected between OSC pin and SGND or Vcc. Since the OSC pin is maintained at fixed voltage (Typ. 1.237V), the frequency is varied proportionally to the current sunk (forced) from (into) the pin considering the internal gain of 6KHz/µA.
In particular connecting it to SGND the frequency is increased (current is sunk from the pin), while connecting ROSC to Vcc=12V the frequency is reduced (current is forced into the pin), according to the following relationships:
ROSC vs. GND: FSW |
= |
150[KHz] + |
1.237 |
6 |
|
kHz |
|
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|
7.422 106 |
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|||
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||||||||||||
--------------- |
|
---------- |
|
|
|
= 150[kHz] + -----------------------------[kHz] |
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ROSC |
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µA |
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ROSC[KΩ] |
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||||||
ROSC vs. 12V: FSW = |
150[KHz]– |
12–1.237 |
6 |
|
kHz |
|
|
6.457 107 |
[kHz] |
|||||
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|||||||||||||
------------------------ |
|
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|
----------µA |
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|
= 150[kHz] – ----------------------------- |
|||||||
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ROSC |
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ROSC[KΩ] |
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Forcing 25µA into this pin, the device stops switching because no current is delivered to the oscillator
8/29
L6712A L6712
|
14000 |
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12V |
12000 |
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10000 |
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) vs. |
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8000 |
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Rosc(K |
6000 |
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4000 |
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2000 |
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0 |
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25 |
50 |
75 |
100 |
125 |
150 |
Frequency (kHz)
|
800 |
|
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GND |
700 |
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600 |
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)vs. |
500 |
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400 |
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Rosc(KΩ |
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300 |
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200 |
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100 |
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0 |
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150 |
250 |
350 |
450 |
550 |
650 |
Frequency (kHz)
The built-in digital to analog converter allows the adjustment of the output voltage from 0.900V to 3.300V as shown in Figure 6. Different voltages can be reached simply changing the Remote Amplifier Gain that acts as a resistor divider (See relevant section).
The internal reference is trimmed during production process to have an output voltage accuracy of ±0.9% and a zero temperature coefficient around 70°C including also error amplifier offset compensation. It is programmed through the voltage identification (VID) pins. These are inputs of an internal DAC that is realized by means of a series of resistors providing a partition of the internal voltage reference. The VID code drives a multiplexer that select a voltage on a precise point of the divider (see Figure 6). The DAC output is delivered to an amplifier obtaining the VPROG voltage reference (i.e. the set-point of the error amplifier). Internal pull-ups are provided (realized with a 5µA current generator up to 3V typ.); in this way, to program a logic "1" it is enough to leave the pin floating, while to program a logic "0" it is enough to short the pin to SGND.
The device offers a bi-directional pin REF_IN/OUT: the internal reference used for the regulation is usually available on this pin with 3mA of maximum current capability except when VID code 111 is programmed; in this case the device accepts an external reference through the REF_IN/OUT pin and regulates on it. When external reference is used, it must range from 0.800V up to 3.300V to assure proper functionality of the device.
Figure 6 shows a block schematic of how the Reference for the regulation is managed when internal or external reference is used.
The voltage identification (VID) pin configuration or the external reference provided also sets the powergood thresholds (PGOOD) and the Over/Under voltage protection (OVP/UVP) thresholds.
9/29