ST L6706 User Manual

Features

L6706

VR11.1 single phase controller with integrated driver

■ 8-bit programmable output up to 1.60000 V -

■ High current embedded driver

■ High output voltage accuracy

■ Programmable droop function

■ Imon output

■ Load transient boost LTB Technology™ to

Intel

VR11.1 DAC

minimize the number of output capacitors

■ Full differential current sense across inductor

■ Differential remote voltage sensing

■ Adjustable voltage offset

■ LSLess startup to manage pre-biased output

■ Feedback disconnection protection

■ Preliminary overvoltage protection

■ Programmable overcurrent protection

■ Programmable overvoltage protection

■ Adjustable switching frequency

■ SSEND and OUTEN signal

■ VFQFPN-40 6x6 mm package with exp. pad

VFQFPN-40 6 x 6 mm

Description

The device implements a single phase step-down controller with integrated high current driver in a compact 6x6 mm body package with exposed pad.

The device embeds VR11.x DACs: the output voltage ranges up to 1.60000 V managing D-VID with high output voltage accuracy over line and temperature variations.

Imon capability guarantee full compatibility with VR11.1 enabling additional power saving technique.

Programmable droop function allows to supply all the latest Intel CPU rails.

Applications

■ VTT and VAXG rails

■ CPU power supply

■ High density DC/DC converters

Load transient boost LTB Technology™ reduces system cost by providing the fastest response to load transition.

The controller assures fast protection against load over current and under / over voltage. Feedback disconnection prevents from damaging the load in case of disconnections in the system board.

In case of over-current, the system works in constant current mode until UVP.

Table 1. Device summary

January 2010 Doc ID 15698 Rev 2 1/47

Order codes Package Packing

L6706

Tr ay

VFQFPN-40

L6706TR Tape and reel

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Contents L6706

Contents

1 Principle application circuit and block diagram . . . . . . . . . . . . . . . . . . . 4

1.1 Principle application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Voltage identifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 DAC and current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7 Differential remote voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8 Voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8.1 Offset (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8.2 Droop function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

9 Droop thermal compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

10 Output current monitoring (IMON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

11 Load transient boost technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

12 Dynamic VID transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

13 Enable and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

14 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2/47 Doc ID 15698 Rev 2

L6706 Contents

14.1 Low-side-less startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

15 Output voltage monitor and protections . . . . . . . . . . . . . . . . . . . . . . . . 34

15.1 Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

15.2 Preliminary overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

15.3 Over voltage and programmable OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

15.4 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

15.5 Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

16 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

17 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

18 System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

19 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

20 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

20.1 Power components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

20.2 Small signal components and connections . . . . . . . . . . . . . . . . . . . . . . . 43

20.3 Embedding L6706 - Based VR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

21 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Doc ID 15698 Rev 2 3/47

Principle application circuit and block diagram L6706

1 Principle application circuit and block diagram

1.1 Principle application circuit

Figure 1. Principle application circuit

= 12V

GND

SS_END

Optional:Pre-OVP

Optional:

See DS

VTT

To Vcc

SSOSC

10k

VID bus from CPU

To Enable circuitry

L6706 REF.SCH

OVP

OCSET

OFFSET

LTBGAIN

OSC_SGND

OSC_VCC

SS_FLIM

FLIMT

27 26

25 24 23 22 21 20

VCCDR

PGND

DGND

VCC

SGND

OVPSEL

OCSET

OFFSET

LTBGAIN

OSC/FAULT

SSOSC/FLIMIT

SSEND

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

OUTEN

EXPAD

UGATE

PHASE

L6706

BOOT

LGATE

COMP

VSEN

IMON

INT1

INT3

INT4

INT2

CS-

CS+

LTB

FBG

(a)

HS1

LS1

220nF

Vcc_core

OUT

LOAD

OUT

GND_core

FB1

FB2

FB3

Optional:

See DS

LTB

NTC

MON

+3V3

+12V

NTC

IMON_OS

IMON_TOT

Optional:

See DS

+3V3

a. Refer to the application note for the reference schematic.

4/47 Doc ID 15698 Rev 2

L6706 Principle application circuit and block diagram

1.2 Block diagram

Figure 2. Block diagram

OSC / FAULT

SSOSC/

FLIMT

VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7

OSCILLATOR

DIGITAL

SOFT START

DAC

WITH DYNAMIC

VID CONTROL

GND DROP RECOVERY

INT1

INT2

FBG

INT3

VREF

INT4

BOOT

UGATE

PHASE

VCCDR

LGATE

PGND

VCC

SGND

DGND

SSEND

50uA

INFO

+.1240V

CH CURRENT

READING

+.1240V

20uA

LTB

OUTEN

DROOP

OVP

10uA

LTBGAIN

CS-

CS+

OCSET

OVPSEL

IMON

LOGIC PWM

ADAPTIVE ANTI

CROSS CONDUCTION

PWM

LTB

INT1

INT2

SSOSC

OUTEN

DROOP

CONTROL LOGIC

AND PROTECTIONS

DELIVERED CURRENT

OFFSET

ERROR

AMPLIFIER

COMP

INT3

L6706

INT4

OFFSET

PWM1

OFFSET

VCC

VCCDR

OCSET

INFO

OVP

COMPARATOR

+.1240V

+175mV

1.800V / OVP

VSEN

Doc ID 15698 Rev 2 5/47

Pins description and connection diagrams L6706

2 Pins description and connection diagrams

Figure 3. Pins connection (top view)

SSEND

INT2

VID7

VID6

VID5

VID4

VID3

VID2

VID1

VID0

INT1

CS-

CS+

OUTEN

SSOSC/FLIMIT

OSC/FAULT

OCSET

OVPSEL

OFFSET

INT3

N.C.

INT4

N.C.

VCCDR

LGATE

PGND

PHASE

UGATE

BOOT

N.C.

27 26 25 24 23 22 21

123456789

L6706

2.1 Pin description

Table 2. Pin description

N° Name Description

1DGND

2SGND

3VCC

4COMP

5FB

Digital GND. It must be connected to PGND (power ground).

All the internal references are referred to this pin. Connect it to the PCB signal ground.

Device supply voltage pin. The operative supply voltage is 12 V ±15%. Filter with 1 x 1 µF MLCC capacitor

vs. SGND.

Error amplifier output. Connect with an R

pulling down this pin.

Error amplifier inverting input pin. Connect with a resistor R

current proportional to the load current is sourced from this pin in order to implement the droop effect. See “Droop function” Section for details.

SGND

DGND

VCC

COMP

VSEN

FBG

LT B

IMON

LTBGAIN

- CF//CP vs. FB pin. The device cannot be disabled by

vs. VSEN and with an RF - CF//CP vs. COMP pin. A

6 VSEN

Output voltage monitor, manages OVP/UVP protections and FB disconnection. Connect to the positive side of the load to perform remote sense. See “Layout

guidelines” Section for proper layout of this connection.

7FBG

Connect to the negative side of the load to perform remote sense. See “Layout

guidelines” Section for proper layout of this connection.

6/47 Doc ID 15698 Rev 2

L6706 Pins description and connection diagrams

Table 2. Pin description (continued)

N° Name Description

Load transient boost pin.

- C

Internally fixed at 2 V, connecting a R

8LTB

load transient boost technology™: as soon as the device detects a transient load it turns on the PHASE. Short to SGND to disable the function.See “Load

transient boost technology” Section for details.

Current monitor output pin.

9IMON

A current proportional to the load current is sourced from this pin. Connect through a resistor R pin voltage is clamped to 1.1 V max.

Load transient boost technology™ gain pin.

10 LTBGAIN

Internally fixed at 1.24 V, connecting a R setting the GAIN of the LTB action. See See “Load transient boost technology”

Section for details.

Offset programming pin. Internally fixed at 1.240 V, connecting a R

11 OFFSET

setting a current that is mirrored into FB pin in order to program a positive offset according to the selected RFB. Short to SGND to disable the function.

See “Offset (optional)” Section for details.

Over voltage programming pin. Internally pulled up by 20 µA (min) to 3.3 V. Leave floating to use built-in

12 OVPSEL

protection thresholds (OVPTH= VID + 175 mV typ). Connect to SGND through a R voltage according to the R

OVP” Section for details.

LT B

LTBGAIN

OFFSET

vs. V

resistor vs SGND allows

LT B

to SGND (or FBG) to implement a load indicator. The

MON

resistor and filter with 100 pF (max) to set the OVP threshold to a fixed

OVP

resistor.See “Over voltage and programmable

OVP

allows to enable the

OUT

resistor vs. SGND allows

Over current setting, psi action pin.

13 OCSET

Connect to SGND through a R

resistor to set the OCP threshold. See

OCSET

“Overcurrent protection” Section for details.

Oscillator, fault pin.

. Frequency is programmed

OSC/

FAULT

It allows programming the switching frequency F according to the resistor connected from the pin vs. SGND or VCC with a gain of 9.1 kHz/µA (see relevant section for details). Leaving the pin floating programs a switching frequency of 200 kHz. The pin is forced high (3.3 V typ) to signal an OVP/UVP fault: to recover from this condition, cycle VCC or the OUTEN pin. See “Oscillator” Section for details.

Soft-start oscillator pin. By connecting a resistor RSS to GND, it allows programming the soft-start time.

will proportionally change with a gain of 25 [µs / kΩ]. The

to the programmed VID code. The pin is kept to a

BOOT

has to be considered also when the

BOOT

SSOSC/

FLIMIT

Soft-start time T same slope implemented to reach V reference moves from V fixed 1.240 V. See “Soft-start” Section for details. It also allows to select maximum LTB frequency. See “Load transient boost technology” Sectionfor details.

Doc ID 15698 Rev 2 7/47

Pins description and connection diagrams L6706

Table 2. Pin description (continued)

N° Name Description

Output enable pin. Internally pulled up by 10 µA (typ) to 3 V. Forced low, the device stops

16 OUTEN

17 CS+

18 CS-

operations with all MOSFETs OFF: all the protections are disabled except for preliminary over voltage. Leave floating, the device starts-up implementing softstart up to the selected VID code. Cycle this pin to recover latch from protections; filter with 1 nF (typ) vs. SGND.

Current sense positive input. Connect through an R-C filter to the phase-side of the output inductor. See Section 20: Layout guidelines on page 43 for proper layout of this

connection.

Current sense negative input. Connect through a Rg resistor to the output-side of the output inductor. See Section 20: Layout guidelines on page 43 for proper layout of this

connection.

19 INT1

20 to 27

28 INT2

VID0 to

VID7

Test mode pin. It must be left unconnected or connected to 3.3 V.

Voltage identification pins. (not internally pulled up). Connect to SGND to program a '0' or connect to the external Pull-up resistor to

program a '1'. They allow programming output voltage as specified in Ta bl e 7 .

Test mode pin. It must be connected to SGND.

Soft-start end signal.

29 SSEND

Open drain output sets free after SS has finished and pulled low when triggering any protection. Pull up to a voltage lower than 3.3 V, if not used it can be left floating.

30 N.C. Not internally connected.

31 INT3

Test mode pin. It must be connected to 12 V.

32 N.C. Not internally connected.

33 INT4

Test mode pin. It must be connected to 12 V.

34 N.C. Not internally connected.

LS driver supply.

35 VCCDR

VCDDR pin voltage has to be the same of VCC pin. Filter with 1 x 1 µF MLCC capacitor vs. PGND.

36 LGATE

37 PGND

LS driver output. A small series resistor helps in reducing device-dissipated power.

Power ground pin (LS drivers return path). Connect to power ground plane.

HS driver return path.

38 PHASE

It must be connected to the HS MOSFET source and provides return path for the HS driver.

8/47 Doc ID 15698 Rev 2

L6706 Pins description and connection diagrams

Table 2. Pin description (continued)

N° Name Description

HS driver output.

39 UGATE

It must be connected to the HS MOSFET gate. A small series resistors helps in reducing device-dissipated power.

HS driver supply.

40 BOOT

Connect through a capacitor (100 nF typ.) to PHASE and provide necessary Bootstrap diode. A small resistor in series to the boot diode helps in reducing Boot capacitor overcharge.

Exposed pad connects the silicon substrate. As a consequence it makes a good thermal contact with the PCB to dissipate the power necessary to drive the external MOSFETs.

Connect it to the power ground plane using 4.3 x 4.3 mm square area on the

PA D

Thermal

PA D

PCB and with nine vias, to improve thermal conductivity.

2.2 Thermal data

Table 3. Thermal data

Symbol Parameter Value Unit

thJA

thJC

MAX

stg

Thermal resistance junction to ambient (Device soldered on 2s2p PC board)

35 °C / W

Thermal resistance junction to case 1 °C / W

Maximum junction temperature 150 °C

Storage temperature range -40 to 150 °C

Junction temperature range -10 to 125 °C

Doc ID 15698 Rev 2 9/47

Electrical specifications L6706

3 Electrical specifications

3.1 Absolute maximum ratings

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit

CC, VCCDR

BOOT

PHASE

UGATE

PHASE

To P GN D 1 5 V

Boot voltage 15 V

15 V

LGATE to PGND -0.3 to Vcc+0.3 V

All other pins to PGND -0.3 to 3.6 V

Negative peak voltage to PGND; T < 400 ns VCC = VCCDR = 12 V

Positive voltage to PGND VCC = VCCDR = 12 V

Positive peak voltage to PGND; T < 200 ns VCC = VCCDR = 12 V

-8 V

26 V

30 V

Maximum withstanding voltage range test condition: CDF-AEC-Q100-002- “human body model”

+/- 1750 V

acceptance criteria: “normal performance”

10/47 Doc ID 15698 Rev 2

L6706 Electrical specifications

3.2 Electrical characteristics

VCC = 12 V ± 15%, TJ = 0 °C to 70 °C unless otherwise specified

Table 5. Electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

Supply current and power-on

CCDR

BOOT

VCC supply current

VCCDR supply current LGATE = OPEN, VCCDR = 12 V 5 7 mA

BOOT supply current

UGATE and LGATE open; VCC = VBOOT = 12 V

UGATE = OPEN, PHASE to PGND; VCC = BOOT = 12 V

23 27 mA

23mA

Power-on

VCC turn-ON VCC rising; VCCDR = VCC 3.7 4.0 V

UVLO

VCC

VCC turn-OFF VCC falling; VCCDR = VCC 3.3 3.5 V

Oscillator and inhibit

OSC

Initial accuracy

SS delay time 1 1.5 ms

SS TD2 time R

SS TD3 time 50 200 μs

OSC = OPEN OSC = OPEN; TJ = 0 to 125 °C

= 20 kΩ 500 μs

SSOSC

180 175

200 200

Rising thresholds voltage 0.80 0.85 0.90 V

Output enable

OUTEN

Hysteresis 100 mV

Output pull-up current OUTEN to SGND 10 μA

ΔVosc Ramp amplitude 1.5 V

FAULT Voltage at pin OSC/FAULT OVP and UVP Active 3.3 V

220 225

kHz kHz

Reference and DAC

VID

Error amplifier

VID

BOOT

Output voltage accuracy

VID = 1.000 V to VID = 1.600 V FB = VOUT; FBG = GNDOUT

VID = 0.800 V to VID = 1.000 V FB = VOUT; FBG = GNDOUT

VID = 0.500 V to VID = 0.800 V FB = VOUT; FBG = GNDOUT

-0.5 - 0.5 %

-5 - +5 mV

-8 - +8 mV

Boot voltage 1.081 V

Input low 0.35 V

VID thresholds

Input high 0.8 V

EA DC gain 130 dB

Doc ID 15698 Rev 2 11/47

Electrical specifications L6706

Table 5. Electrical characteristics (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

SR EA slew-rate COMP = 10 pF to SGND 25 V/μs

Differential current sensing and offset

OCSET

IDROOP

IOFFSET

OFFSET

Gate drivers

RISE UGATE

UGATE

RISE LGATE

LGATE

Protections

OVP

Programmable

OVP

OCSET pin voltage 1.120 1.260 1.400 mV

Droop current deviation from nominal value

Offset current accuracy I

Rg = 1 kΩ; I

= 50 μA to 250 μA-5-5%

OFFSET

= 25 μA; -2 - +2 μA

DROOP

OFFSET current range 0 250 μA

OFFSET pin bias I

High side rise time

BOOT-PHASE = 12 V; C

= 0 to 250 μA1.240V

OFFSET

to PHASE = 3.3 nF

UGATE

20 ns

High side source current BOOT-PHASE = 12 V 1.5 A

High side sink resistance BOOT-PHASE = 12 V 1.8 Ω

Low side rise time

VCCDR = 12 V; C

to PGND = 5.6 nF

LGATE

25 ns

Low side source current VCCDR = 12 V 2 A

Low side sink resistance VCCDR = 12 V 1.2 Ω

Over voltage protection (VSEN rising)

current OVP = SGND 20 22 24 μA

OVP

Before V

BOOT

Above VID (after TD

) 150 175 200 mV

1.24 1.300 V

Comparator offset voltage OVP = 1.800 V -20 0 20 mV

UVLO

OVP

Pre-OVP

Preliminary over voltage protection

VCC> UVLO VSEN rising

Hysteresis 350 mV

UVP Under voltage threshold VSEN falling; below VID 550 600 650 mV

SSEND

SS_END voltage low I = -4 mA 0.4 V

12/47 Doc ID 15698 Rev 2

< VCC < UVLO

and OUTEN = SGND

VCC

1.750 1.800 1.850 V

L6706 Voltage identifications

4 Voltage identifications

Table 6. Voltage Identification (VID) mapping Intel VR11.x

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

800 mV 400 mV 200 mV 100 mV 50 mV 25 mV 12.5 mV 6.25 mV

Table 7. Voltage Identification (VID) Intel VR11.x

HEX code

Output

voltage

(1)

HEX code

Output

voltage

HEX code

(1)

Output

voltage

HEX code

(1)

Output

voltage

0 0 OFF 4 0 1.21250 8 0 0.81250 C 0 0.41250

0 1 OFF 4 1 1.20625 8 1 0.80625 C 1 0.40625

0 2 1.60000 4 2 1.20000 8 2 0.80000 C 2 0.40000

0 3 1.59375 4 3 1.19375 8 3 0.79375 C 3 0.39375

0 4 1.58750 4 4 1.18750 8 4 0.78750 C 4 0.38750

0 5 1.58125 4 5 1.18125 8 5 0.78125 C 5 0.38125

0 6 1.57500 4 6 1.17500 8 6 0.77500 C 6 0.37500

0 7 1.56875 4 7 1.16875 8 7 0.76875 C 7 0.36875

0 8 1.56250 4 8 1.16250 8 8 0.76250 C 8 0.36250

0 9 1.55625 4 9 1.15625 8 9 0.75625 C 9 0.35625

0 A 1.55000 4 A 1.15000 8 A 0.75000 C A 0.35000

0 B 1.54375 4 B 1.14375 8 B 0.74375 C B 0.34375

0 C 1.53750 4 C 1.13750 8 C 0.73750 C C 0.33750

0 D 1.53125 4 D 1.13125 8 D 0.73125 C D 0.33125

0 E 1.52500 4 E 1.12500 8 E 0.72500 C E 0.32500

0 F 1.51875 4 F 1.11875 8 F 0.71875 C F 0.31875

(1)

1 0 1.51250 5 0 1.11250 9 0 0.71250 D 0 0.31250

1 1 1.50625 5 1 1.10625 9 1 0.70625 D 1 0.30625

1 2 1.50000 5 2 1.10000 9 2 0.70000 D 2 0.30000

1 3 1.49375 5 3 1.09375 9 3 0.69375 D 3 0.29375

1 4 1.48750 5 4 1.08750 9 4 0.68750 D 4 0.28750

1 5 1.48125 5 5 1.08125 9 5 0.68125 D 5 0.28125

1 6 1.47500 5 6 1.07500 9 6 0.67500 D 6 0.27500

1 7 1.46875 5 7 1.06875 9 7 0.66875 D 7 0.26875

1 8 1.46250 5 8 1.06250 9 8 0.66250 D 8 0.26250

1 9 1.45625 5 9 1.05625 9 9 0.65625 D 9 0.25625

Doc ID 15698 Rev 2 13/47

Voltage identifications L6706

Table 7. Voltage Identification (VID) Intel VR11.x

HEX code

Output

voltage

(1)

HEX code

Output

voltage

HEX code

(1)

(continued)

Output

voltage

HEX code

(1)

Output

voltage

1 A 1.45000 5 A 1.05000 9 A 0.65000 D A 0.25000

1 B 1.44375 5 B 1.04375 9 B 0.64375 D B 0.24375

1 C 1.43750 5 C 1.03750 9 C 0.63750 D C 0.23750

1 D 1.43125 5 D 1.03125 9 D 0.63125 D D 0.23125

1 E 1.42500 5 E 1.02500 9 E 0.62500 D E 0.22500

1 F 1.41875 5 F 1.01875 9 F 0.61875 D F 0.21875

2 0 1.41250 6 0 1.01250 A 0 0.61250 E 0 0.21250

2 1 1.40625 6 1 1.00625 A 1 0.60625 E 1 0.20625

2 2 1.40000 6 2 1.00000 A 2 0.60000 E 2 0.20000

2 3 1.39375 6 3 0.99375 A 3 0.59375 E 3 0.19375

2 4 1.38750 6 4 0.98750 A 4 0.58750 E 4 0.18750

2 5 1.38125 6 5 0.98125 A 5 0.58125 E 5 0.18125

2 6 1.37500 6 6 0.97500 A 6 0.57500 E 6 0.17500

2 7 1.36875 6 7 0.96875 A 7 0.56875 E 7 0.16875

2 8 1.36250 6 8 0.96250 A 8 0.56250 E 8 0.16250

2 9 1.35625 6 9 0.95625 A 9 0.55625 E 9 0.15625

2 A 1.35000 6 A 0.95000 A A 0.55000 E A 0.15000

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2 B 1.34375 6 B 0.94375 A B 0.54375 E B 0.14375

2 C 1.33750 6 C 0.93750 A C 0.53750 E C 0.13750

2 D 1.33125 6 D 0.93125 A D 0.53125 E D 0.13125

2 E 1.32500 6 E 0.92500 A E 0.52500 E E 0.12500

2 F 1.31875 6 F 0.91875 A F 0.51875 E F 0.11875

3 0 1.31250 7 0 0.91250 B 0 0.51250 F 0 0.11250

3 1 1.30625 7 1 0.90625 B 1 0.50625 F 1 0.10625

3 2 1.30000 7 2 0.90000 B 2 0.50000 F 2 0.10000

3 3 1.29375 7 3 0.89375 B 3 0.49375 F 3 0.09375

3 4 1.28750 7 4 0.88750 B 4 0.48750 F 4 0.08750

3 5 1.28125 7 5 0.88125 B 5 0.48125 F 5 0.08125

3 6 1.27500 7 6 0.87500 B 6 0.47500 F 6 0.07500

3 7 1.26875 7 7 0.86875 B 7 0.46875 F 7 0.06875

3 8 1.26250 7 8 0.86250 B 8 0.46250 F 8 0.06250

3 9 1.25625 7 9 0.85625 B 9 0.45625 F 9 0.05625

3 A 1.25000 7 A 0.85000 B A 0.45000 F A 0.05000

3 B 1.24375 7 B 0.84375 B B 0.44375 F B 0.04375

14/47 Doc ID 15698 Rev 2

L6706 Voltage identifications

Table 7. Voltage Identification (VID) Intel VR11.x

HEX code

Output

voltage

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HEX code

Output

voltage

HEX code

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(continued)

Output

voltage

HEX code

(1)

Output

voltage

3 C 1.23750 7 C 0.83750 B C 0.43750 F C 0.03750

3 D 1.23125 7 D 0.83125 B D 0.43125 F D 0.03125

3 E 1.22500 7 E 0.82500 B E 0.42500 F E OFF

3 F 1.21875 7 F 0.81875 B F 0.41875 F F OFF

1. According to INTEL specs, the device automatically regulates output voltage 19 mV lower to avoid any external offset to modify the built-in 0.5% accuracy improving TOB performances. Output regulated voltage is than what extracted from the table lowered by 19 mV.

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Doc ID 15698 Rev 2 15/47

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