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3 Phase Controller for VR10, VR9 and K8 CPUs
Features
■ MULTI-DAC: VR9, VR10 AND K8 DAC
SELECTABLE THROU GH SING L E PIN
■ 0.7% OUTPUT VOLTAGE ACCURACY
■ ADJUSTABLE REFEREN CE OFFSET
■ HIGH CURRENT INTEGRATED DRIVERS
■ DYNAMIC VID MANAGEMENT
■ ACCURATE FULLY-DIFFERENTIAL LOAD-
LINE CURRENT-SENSE ACROSS MAIN
INDUCTORS MAKES BOM INDEPENDENT
ON THE LAYOUT
■ PRECISE CURRENT-SHARING AND OCP
ACROSS LS M OSFET S
■ CONSTANT OVER-CURRENT PROTECTION
■ FEEDBACK DISCONNECTION
PROTECTION
■ PRELIMINARY OV PROTE CTIO N
■ OSCILLATOR INTERNALLY FIXED AT
100kHz (300kHz RIPPLE) EXT ADJUSTABLE
■ SS_END / PGOOD SIGNAL
■ INTEGRATED REMOTE-SENSE BUFFER
■ PWSSO36 PACKAGE WITH EXPOSED PAD
Applications
■ HIGH CURRENT VRM / VRD FOR DESKTOP
/ SERVER/ WORKSTATION CPUs
■ HIGH DENSITY DC / DC CONVERTERS
L6701
PowerSSO-36
Description
L6701 is an extremely simple, low-cost solution to
implement a three phase step-down controller
with integrated high-current drivers in a com pact
PowerSSO-36 package with exposed pad.
The device embeds three selectable DACs: with a
single pin it is possible to pro gram the device to
work in compatibility with VR9, VR10 or K8
applications managing D-VID with ±0.7% output
voltage accuracy over line and temperature
variations. Additional programmable offset can be
added to the reference voltage with a single
external resistor.
Fast protection against load over current let the
system works in Constant Current mode until
UVP. Preliminary OVP allows full load protection
in case of startup with failed HS. Furthermore,
feedback disconnection prevents from damaging
the load in case o f misconnections in the system
board.
Combined use of DCR and R
sensing assures precision in voltage positioning
and safe current sharing and OCP per each
phase.
DS(on)
current
Order co des
Part number Package Packing
L6701 PowerSSO-36 Tube
L6701TR PowerSSO-36 Tape & Reel
Rev 1
December 2005 1/44
www.st.com
44
L6701
Contents
1 Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . . 11
5.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 VID Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7 Configuring the Device: DAC Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.1 Single-Wire CPU Automatic Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8 Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.1 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9 Current Sharing Loop and Current Reading . . . . . . . . . . . . . . . . . . . . . . . 20
9.1 Current Sharing Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.2 Current Reading for Current Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10 Output Voltage Positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10.1 Load-Line (Droop Function - Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10.2 Fully-Differential Load-Line (Droop Function - Optional) . . . . . . . . . . . . . . . 22
10.3 Offset (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
10.4 Remote Voltage Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
10.5 Maximum Duty Cycle limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/44
L6701
11 Dynamic VID Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
12 Soft Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12.1 Low-Side-Less Startup (LSLess) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
13 Output voltage Monitor and Protections . . . . . . . . . . . . . . . . . . . . . . . . . . 29
13.1 Under Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
13.2 Preliminary Over Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
13.3 Over Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
13.4 Feedback Disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
13.5 PGOOD (Only for VR9 and K8 Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
13.6 Over Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
14 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
15 System Control Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
15.1 Compensation Network Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
16 Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
16.1 Power Components and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
16.2 Small Signal Components and Connections . . . . . . . . . . . . . . . . . . . . . . . . . 39
16.3 Embedding L6701-based VRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
17 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3/44
1 Device Descr iption L6701
1 Device Description
L6701 is multi-phase PWM controller with embedded high-current drivers that provides
complete control logic and protections for a high-performance step-down DC-DC voltage
regulator, optimized for advanced microprocessor power supply. Multi-phase buck is the
simplest and most cost-effective topology employable to satisfy the increasing current demand
of newer microprocessors and the modern high-current DC/DC converters and POLs
requirements. It allows distributing equally load and power between the phases using smaller,
cheaper and most common external power MOSF ETs and inductors. Moreover, thanks to the
equal phase-shift between each phase, the input and output capacitor count results in being
reduced. Phase-interleaving causes in fact input rms current and output ripple voltage
reduction and shows an effective output switching frequency increase: the 100kHz free-running
frequency per phase, externally adjustable through a resistor, results multiplied on the output
by the number of phases so reaching 300kHz in free-running.
L6701 includes multiple DACs, selectable through an apposite pin, allowing compatibility with
both Intel VR9, VR10 and AMD Hammer specifications, also performing D-VID transitions
accordingly. In particular for Intel CPUs, it allows to automatically recognize the CPU with a
single-wire connection, without any additional external component, by proper connecting the
selector pin to the proper CPU pin.
Precise voltage positioning (LL) is possible thanks to an accurate fully-differential current-sense
across the main inductors still using only two pins for current-reading (pat. pend.): this makes
any BOM insensitive to the board layout saving time in the design stage.
The device internally balance the current driven by each phase by sensing the voltage drop
across the LS MOSFET R
causing the device to work in constant-current mode.
The controller provides output voltage protections to avoid any load damage due to failed
components and/or feedback misconnec tions. Over-Voltage protects the load from dangerous
over stress latching immediately the device by turning-on the lower driver and driving high the
FAULT pin. Furthermore, preliminary-OVP protection also allows the device to protect the load
from dangerous OVP when V
causes the device to stop switching when set while Over-Current protection, with a threshold
for each phase, causes the device to enter in constant current mode until the latched UVP.
L6701 implements soft-start increasing the reference up to the final value in 2048 clock cycles
in closed loop regulation. Low-Side-Less feature allows the device to perform soft-start over
pre-biased output avoiding dangerous current return through the main inductors as well as
negative spike at the load side.
The compact PowerSSO-36 package with exposed thermal pad allows dissipating the power to
drive the external MOSFET through the system board.
. OC protection is effective with a threshold for each phase
DS(on)
is not above the UVLO threshold. Under-Voltage protection
CC
4/44
L6701 2 Pins descrip tion and connection diagrams
2 Pins description a nd connection diagram s
Figure 1. Pins connection (Top view)
SSEND / PGOOD
OSC / EN / FAULT
2.1 Pin description
Table 1. Pins description
Pin n°
1SGND
2VCC
Name Function
SGND
VCC
LGATE1
PGND
LGATE2
LGATE3
BOOT1
UGATE1
PHASE1
BOOT2
UGATE2
PHASE2
BOOT3
UGATE3
PHASE3
DAC_SEL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
COMP
FB
VSEN
CSCS+
ISEN1
ISEN2
ISEN3
FBG
FBR
VID5
VID0
VID1
VID2
VID3
VID4
REF_OUT
REF_IN
All the internal references are referred to this pin. Co nnect to the PCB Signal
Ground.
Device Power Supply and LS driver supply.
Operative voltage is 12V ±15%. Filter with at least 1µF MLCC vs. ground.
3LGATE1
Channel 1 LS Driver Output.
A small series resist or hel ps in reducing device-dissipat ed power.
4 PGND LS Drivers return path. Connect to Power ground Plane.
5LGATE2
6LGATE3
Channel 2 LS Driver Output.
A small series resist or hel ps in reducing device-dissipat ed power.
Channel 3 LS Driver Output.
A small series resist or hel ps in reducing device-dissipat ed power.
Channel 1 HS driver supply.
Connect through a capacitor (100nF typ.) to PHASE1 and provide necessary
7 BOOT1
Bootstrap dio de.
A small series resistor upstream the boot diode helps i n reducing Boot cap acitor
overcharge.
8UGATE1
Channel 1 HS driver output.
A small series resistors helps in reducing device-dissipated power.
Channel 1 HS driver return path.
9 PHASE1
It must be connected to the HS1 MOSFET sour ce and provides return path for
the HS driver of channel 1.
5/44
2 Pins description and connection diagrams L6701
Table 1. Pins description (continued)
Pin n°
Name Function
10 BOOT2
11 UGATE2
12 PHASE2
13 BOOT3
14 UGATE3
15 PHASE3
Channel 2 HS driver supply.
Connect through a capacitor (100nF typ.) to PHASE2 and provide necessary
Bootstrap dio de.
A small series resistor upstream the boot diode helps i n reducing Boot cap acitor
overcharge.
Channel 2 HS driver output.
A small series resistors helps in reducing device-dissipated power.
Channel 2 HS driver return path.
It must be connected to the HS2 MOSFET sour ce and provides return path for
the HS driver of channel 2.
Channel 3 HS driver supply.
Connect through a capacitor (100nF typ.) to PHASE3 and provide necessary
Bootstrap dio de.
A small series resistor upstream the boot diode helps i n reducing Boot cap acitor
overcharge.
Channel 3 HS driver output.
A small series resistors helps in reducing device-dissipated power.
Channel 3 HS driver return path.
It must be connected to the HS3 MOSFET sour ce and provides return path for
the HS driver of channel 3.
16
SSEND /
PGOOD
17 DAC_SEL
18
OSC / EN /
FAULT
SSEND - Intel VR10 Mode. Soft Start END Signal.
Open Drain Output set free af ter SS has finished and pulled low when triggering
any protection. Pull up to 5V (typ) or lower , if not used it can be left floating.
PGOOD - Intel VR9 & AMD Hammer Mode.
Open Drain Output set free after SS has finished and pulled low when VSEN is
lower than t he relative threshold. Pull up to 5V (typ) or lower, if n ot used it can be
left floati ng.
DAC SELection pin.
It allows progr ammin g the DAC tabl e for th e regul atio n. Int ernal ly pull ed- up to 5V.
Short to GND to program VR9 DAC, leave floating to progr am K8 DAC while
connect to GND t hrough 82kΩ to program VR10 DAC.
Information about the selected DAC is latched bef ore the system start-up. See
Section 7.1 for connections to enab le CPU auto-detection.
OSC: It allows programming t he swit ching frequency F
of each channel.
SW
Switching frequency can be increased according to the resistor connected from
the pin vs. SGND with a gain of 4kHz/µA (see Section 14). Leaving the pin
floating it program s a switching frequency of 100kHz per phase (300kHz on the
load).
EN: Forced low, the device stops operations with all MOSFETs OFF: all the
protections are disabled except for Preliminary Over Voltage. When set low it
resets the devi ce from any latching condition.
FAULT: The pin is forc ed high (5V) to signal an OVP / UVP FAULT: to recover
from this conditio n, cycle VCC or the OSC pin. See Section13 for details.
6/44
L6701 2 Pins descrip tion and connection diagrams
Table 1. Pins description (continued)
Pin n°
Name Function
19 REF_IN
20 REF_OUT
VID4
21 to 26
VID0, VID5
27 FBR
28 FBG
ISEN3
29 to 31
ISEN1
to
to
Reference Input for the regul ation.
Connect directly or through a resistor to the REF_OUT pin. See Section 10.3 for
details. This pi n is used as input for the protections.
Reference Output.
Connect directly or through a resistor to the REF_IN pin. See Section 10.3 for
details.
Voltage IDentific ati on Pins.
Internally pulled up by 12.5µA to 5V , connect to SGND to program a '0' or leave
floating to progra m a '1' . They allow programming outp ut vol tage as specified in
Table 5, Table 6 and Table 7 according to DAC_SEL status.
Remote Buffer Non Inverting Input.
Connect to the positiv e side of the load to perform remote sense.
See Section 16 for proper layout of this connection.
Remote Buffer Inverting Input.
Connect to the negative si de of the load to perform remot e sense.
See Section 16 for proper layout of this connection.
LS Current Sense Pins.
These pins are used for current balance phase-to-phase as well as for the
system OCP. Connect through a resi stor R
to the relative PHASEx pin. See
ISEN
Section 9 and Section 13.6 for details.
32 CS+
33 CS-
34 VSEN
35 FB
36 COMP
PAD
THERMAL
PAD
Droop Current Sense non-inverting input.
Connect through R
network to the main inductors. Directly connect to
PH-CPH
output voltage wh en Droop function is not required. See Section 10.1 and
Section 10.2 for details.
Droop Current Sense inverting input.
Connect through resistor R
to the main inductors common node. Le ave floating
D
when Droop Function is not required. See Section 10.1 and Section 10.2 for
details.
This pin also monitors t he output for any feedback di sconnection. See
Section 13.4 for details.
Remote Buffer Out put. It manages OVP and UVP protections and PGOOD
(when applicable). See Section 13 for details.
Error Amplifier Inver ting I nput. Conn ect with a resi stor R
R
- CF toward COMP.
F
Error Amplifier Output . Connect with an R
- CF vs. FB.
F
vs. VSEN and with an
FB
The device cannot be disabled by pulling down this pin.
Thermal pad connects the Silicon substrate and makes good thermal contact
with the PCB to dissipate the power necessary to drive the ext ernal MOSFETs.
Connect to the PGND plane with sever al VI As to i mprove thermal conductivity.
7/44
3 Maximum Ratings L6701
3 Maximum Ratings
3.1 Absolute maxi mum ratings
Table 2. Absolute Maximum Ratings
Symbol Parameter Value Unit
V
CC
V
BOOTx
V
UGATEx
- V
- V
PHASEx
PHASEx
to PGND 15 V
Boot Vol tage 15 V
15 V
LGA TEx, PHASEx, to PGNDx
-0.3 to VCC + 0.3
VID0 to V ID 5 -0.3 to 5 V
All other Pins to PGNDx -0.3 to 7 V
V
PHASEx
Positive Peak Voltage; T<20ns @ 600kHz 26 V
Negative Peak Voltage; TBD V
3.2 Thermal data
Table 3. Thermal data
Symbol Parameter Value Unit
R
R
T
T
P
THJA
THJC
MAX
STG
T
TOT
Thermal Resistan ce Junction to Ambient
(Device soldered on 2s2p PC Board)
30 °C/W
Thermal Resistan ce Junction to Case 1 °C/W
Maximum Junction Temperature 150 °C
Storage Temperature Range -40 to 150 °C
Junction Temperature Range 0 to 125 °C
J
Maximum Power Dissipation at 25°C
(Device soldered on 2s2p PC Board)
3.3 W
V
8/44
L6701 4 Electrical specifications
4 Electrical specifications
4.1 Electrical characteristics
Table 4. Electrical Characteristics
(V
= 12V±15%, TJ = 0°C to 70°C unless otherwise specified).
CC
Symbol Parameter Te st condi tions Min. Typ. Max. Unit
Supply Current and Power-ON
I
CC
I
BOOTx
UVLO
UVLO
VCC Supply current
BOOTx Supply Current
VCC Turn-ON VCC Rising
VCC
Turn-OFF VCC Falling
V
CC
Pre-OVP Turn-ON
OVP
Pre-OVP Turn-OFF
HGATEx and LGATEx = OPEN
BOOTx = 12V
HGA TEx = OPEN;
PHASEx to PGNDx; BOOTx = 12V
V
Rising
CC
V
Falling
CC
17 mA
0.7 mA
9.2 V
7V
3.8 V
3V
Oscillator and Inhib it
F
SW
OSC
d
MAX
∆V
OSC
Main Oscillator Accuracy
Disable Thresholds 0.5 V
IL
Maximum Duty Cycle
PWMx Ramp Amplitude 3 V
OSC = OPEN
OSC = OPEN; T
OSC = OPEN; I
OSC = OPEN; I
= 0°C to 125°C
J
= 0µA
ISENx
= 35µA
ISENx
90 100 110 kHz
80 %
40 %
FAULT Voltage at Pin OSC OVP Active 5 V
Reference and DAC
k
VID
I
VID
VID
VID
FBR = V
VR10 and VR9 DACs; V
Output Voltage Accuracy
FBR = V
K8 DAC; V
; FBG = GND
OUT
; FBG = GND
OUT
> 1V
OUT
OUT
OUT
OUT
;
> 1V
;
-0.7 0.7 %
-1 1 %
VID Pull-up Current 25 µA
IL
VR9 and VR10 Mode; Input Low
K8 Mode; Input Low
0.4
0.8
V
V
VID Input Thresholds
IH
VR9 and VR10 Mode; Input Low
K8 Mode; Input Low
0.8
2
V
V
9/44
4 Electric al specifications L6701
Table 4. Electrical Characteristics (continued)
(V
= 12V±15%, TJ = 0°C to 70°C unless otherwise specified).
CC
Symbol Parameter Te st condi tions Min. Typ. Max. Unit
Error Amplifier and Remote Buffer
A
0
EA DC Gain 80 dB
SR Slew Rate COMP = 10pF to SGND 15 V/µs
RB DC Gain 1 V/V
CMRR
Remote Buffer Common
Mode Rejection Ratio
40 dB
Differential Curr ent Sensing and Offset
I
OCTH
k
IDROOP
I
OFFSET
Over Current Threshold 35 µA
I
Droop Current Deviation
= 0 to 105µA; RD=5.1kΩ
DROOP
-3 3 µA
Offset Current 10 11.5 13 µA
Gate Drivers
t
RISE_UGA
TEx
I
UGATEx
R
UGATEx
t
RISE_LGA
TEx
I
LGATEx
R
LGATEx
HS Rise Time
HS Source Current BOOTx - PHASEx = 10V 1.5 A
HS Sink Resistance BOOTx - PHASEx = 12V 2.5 Ω
LS Rise Ti me
LS Source Current VCC = 10V 1.5 A
LS Sink Resistance VCC = 12V 1.8 Ω
BOOTx - PHASEx = 10V;
C
to PHASEx = 3.3nF
UGATEx
VCC = 10V;
C
to PGNDx = 5.6nF
LGATEx
15 ns
20 ns
Protections
OVP Over Voltage Protection
Pre-OVP
Preliminary Over vol tage
Protection
VSEN Rising, VR10 and K8 Mode
VSEN Rising, VR9 Mode
FBR Rising, VR10 and K8 Mode
FBR Rising, VR9 Mode
1.85
2.05
1.8
2.0
1.9
2.1
1.9
2.1
1.95
2.15
2.0
2.2
Hysteresis 300 mV
UVP Under Voltage Protection VSEN Falling; Below VID -475 -400 -325 mV
PGOOD PGOOD Threshold
V
SSEND/
PGOOD
SSEND / PGOOD
Voltage Low
K8 and VR9 Mode;
VSEN Falling; Below VID
I = -4mA
-280 -230 -180 mV
0.4
10/44
V
V
V
V
V
L6701 5 Typical application circuit and block diagram
5 Typi cal application ci rcuit and block diagram
5.1 Application circuit
Figure 2. Typical application cir cuit
VIN
GNDIN
2
VCC
LIN
BOOT1
to BOOT1
CIN
7
VIN
to BOOT2
to BOOT3
ISEN1
BOOT2
ISEN2
BOOT3
ISEN3
CS+
CS-
8
9
3
31
R
ISEN
10
11
12
5
30
R
ISEN
13
14
15
6
29
R
ISEN
32
33
R
D
16
HS1
LS1
HS2
LS2
HS3
LS3
VIN
VIN
RPHRPHR
L1
L2
COUT
L3
PH
C
PH
Vcc_core
LOAD
PGOOD
4
PGND
1
SGND
17
DAC_SEL
18
OSC/EN/FAULT
26
VID5
21
VID4
22
VID3
23
VID2
24
VID1
25
VID0
19
REF_IN
R
C
OS
OS
C
R
R
FB
20
REF_OUT
36
COMP
F
F
35
FB
34
VSEN
27
FBR
28
FBG
UGATE1
PHASE1
LGATE1
UGATE2
PHASE2
LGATE2
UGATE3
L6701
PHASE3
LGATE3
SSEND / PGOOD
L6701 REFERENCE SCHEMATIC
11/44
5 T ypical application circuit and block diagram L6701
Figure 3. Typical Applicat i on Circuit: Fully Differential Curr ent Sense (Pat.Pend.)
VIN
GNDIN
2
VCC
4
PGND
1
SGND
17
DAC_SEL
18
OSC/EN/FAULT
26
VID5
21
VID4
22
VID3
23
VID2
24
VID1
25
VID0
19
REF_IN
R
C
OS
OS
C
R
R
FB
20
REF_OUT
36
COMP
F
F
35
FB
34
VSEN
27
FBR
28
FBG
LIN
BOOT1
UGATE1
PHASE1
LGATE1
ISEN1
BOOT2
UGATE2
PHASE2
LGATE2
ISEN2
BOOT3
UGATE3
L6701
PHASE3
LGATE3
ISEN3
CS+
CS-
SSEND / PGOOD
to BOOT1
CIN
7
8
9
3
31
R
ISEN
10
11
12
5
30
R
ISEN
13
14
15
6
29
R
ISEN
32
33
VIN
HS1
L1
LS1
VIN
HS2
L2
LS2
VIN
HS3
L3
LS3
R
D
R
D
R
D
RPHRPHR
PH
C
PH
C
PH
C
PH
16
to BOOT2
to BOOT3
COUT
Vcc_core
LOAD
PGOOD
L6701 FULLY DIFFERENTIAL
REFERENCE SCHEMATIC
12/44
L6701 5 Typical application circuit and block diagram
5.2 Block diagram
Figure 4. Block diagram
BOOT1
UGATE1
VCC
PGND
SGND
OSC / EN / FAULT
VID0
VID1
VID2
VID3
VID4
VID5
DAC_SEL
PGND
SGND
3 PHASE
OSCILLATOR
DIGITAL
SOFT START
MULTIPLE DAC
WITH DYNAMIC
PHASE1
HS1 LS1 HS2 LS2 HS3 LS3
LOGIC PWM
ADAPTIVE ANTI
CROSS CONDUCTION
VCC
OSC/EN/FAULT
DAC_SEL
I
OS
I
VID CONTROL
DROOP
AMPLIFIER
LGATE1
VCC
CURRENT SHARING
CORRECTION
PWM1 PWM2 PWM3
OVP
UVP, PGOOD
x3
ERROR
BOOT2
UGATE2
PHASE2
PGND
CROSS CONDUCTION
PWM1 PWM2 PWM3
L6701
CONTROL LOGIC
AND PROTECTIONS
I
INFO
CURRENT READING
VCC
LOGIC PWM
ADAPTIVE ANTI
CURRENT SHARING
CORRECTION
DROOP
LGATE2
PGND
1V
BOOT3
UGATE3
ADAPTIVE ANTI
CROSS CONDUCTION
OCP1
OCP2
OCP3
REMOTE
BUFFER
PHASE3
LOGIC PWM
CURRENT SHARING
CORRECTION
PH1
LOW SIDE MOSFET
CURRENT READING
AND OVER CURRENT
SSEND / PGOOD
64k
VCC
PH2
64k
PH3
LGATE3
64k
64k
PGNDVCC
AVG
ISEN1
ISEN2
ISEN3
SSEND / PGOOD
REF_OUT
REF_IN
FB
COMP
CS-
CS+
VSEN
FBR
FBG
13/44
6 VID Tables L6701
6 VID Tables
Table 5. Vo ltage IDentification (VID) for Intel VR10 DAC.
VID4 VID3 VID2 VID1 VID0 VID5
010101 1.6000 110101 1.2000
010110 1.5875 110110 1.1875
010111 1.5750 110111 1.1750
011000 1.5625 111000 1.1625
011001 1.5500 111001 1.1500
011010 1.5375 111010 1.1375
011011 1.5250 111011 1.1250
011100 1.5125 111100 1.1175
011101 1.5000 111101 1.1000
011110 1.4875 111110 OFF
011111 1.4750 111111 OFF
100000 1.4625 000000 1.0875
100001 1.4500 000001 1.0750
100010 1.4375 000010 1.0625
100011 1.4250 000011 1.0500
100100 1.4125 000100 1.0375
Output
Voltage
VID4 VID3 VID2 VID1 VID0 VID5
(1)
Output
Voltage
(1)
100101 1.4000 000101 1.0250
100110 1.3875 000110 1.0125
100111 1.3750 000111 1.0000
101000 1.3625 001000 0.9875
101001 1.3500 001001 0.9750
101010 1.3375 001010 0.9625
101011 1.3250 001011 0.9500
101100 1.3125 001100 0.9375
101101 1.3000 001101 0.9250
101110 1.2875 001110 0.9125
101111 1.2750 001111 0.9000
110000 1.2625 010000 0.8875
110001 1.2500 010001 0.8750
110010 1.2375 010010 0.8625
14/44
L6701 6 VID Tables
Table 5. Vo ltage IDentification (VID) for Intel VR10 DAC. (continued)
VID4 VID3 VID2 VID1 VID0 VID5
Output
Voltage
VID4 VID3 VID2 VID1 VID0 VID5
(1)
Output
Voltage
110011 1.2250 010011 0.8500
110100 1.2125 010100 0.8375
1. Since the VIDx pins program the maximum output voltage, according to VR10.x specifications, the device automatically
regulates to a voltage 1 9mV lowe r avoiding the use of any external components to lower the output voltage. T his improves
the system tolerance per formance since the reference already offset is tri mmed in production within ±0.7%.
Table 6. Vo ltage IDentification (VID) for Intel VR9 DAC (VID5 doesn’t care)
VID4 VID3 VID2 VID1 VID0
Output Voltage
00000 1.850 10000 1.450
00001 1.825 10001 1.425
00010 1.800 10010 1.400
00011 1.775 10011 1.375
00100 1.750 10100 1.350
00101 1.725 10101 1.325
00110 1.700 10110 1.300
00111 1.675 10111 1.275
01000 1.650 11000 1.250
(1)
VID4 VID3 VID2 VID1 VID0
Output Voltage
(1)
(1)
01001 1.625 11001 1.225
01010 1.600 11010 1.200
01011 1.575 11011 1.175
01100 1.550 11100 1.150
01101 1.525 11101 1.125
01110 1.500 11110 1.100
01111 1.475 11111 OFF
1. Since the VIDx pins program the maximum output voltage, the device automatically regulates to a voltage 19mV lower
avoiding the use of any external components to lower the output voltage. This improves the system tolerance performance
since the reference already offs et is trimmed in production within ±0.7 %.
15/44
6 VID Tables L6701
Table 7. Vo ltage IDentification (VID) for AMD Hammer DAC
VID5 VID4 VID3 VID2 VID1 VID0
00000 1.550
00001 1.525 00001 1.550
00010 1.500 00010 1.525
00011 1.475 00011 1.500
00100 1.450 00100 1.475
00101 1.425 00101 1.450
00110 1.400 00110 1.425
00111 1.375 00111 1.400
01000 1.350 01000 1.375
01001 1.325 01001 1.350
01010 1.300 01010 1.325
01011 1.275 01011 1.300
01100 1.250 01100 1.275
01101 1.225 01101 1.250
01110 1.200 01110 1.225
01111 1.175 01111 1.200
1
10000 1.150 10000 1.175
Output
Voltage
VID5 VID4 VID3 VID2 VID1 VID0
00000 1.575
0
Output
Voltage
10001 1.125 10001 1.150
10010 1.100 10010 1.125
10011 1.075 10011 1.100
10100 1.050 10100 1.075
10101 1.025 10101 1.050
10110 1.000 10110 1.025
10111 0.975 10111 1.000
11000 0.950 11000 0.975
11001 0.925 11001 0.950
11010 0.900 11010 0.925
11011 0.875 11011 0.900
11100 0.850 11100 0.875
11101 0.825 11101 0.850
11110 0.800 11110 0.825
11111 OFF 11111 OFF
16/44
L6701 7 Configuring the Device: DAC Selection
7 Configuring the Device: DAC Selection
Multiple DACs need to be configured before the system start-up by programming the apposite
pin DAC_SEL. The embedded DAC allows to regulate the output voltage with a tolerance of
±0.7% recovering from offsets and manufacturing variations. In case of selecting VR9 and
VR10 Mode, the device automatically introduc es a -19mV offset to the regulated voltage (see
Table 5 and Table 6) in order to avoid any external offset circuitry to worsen the guaranteed
accuracy and, as a consequence, the calculated system TOB. In case of selecting the K8 DAC,
VID5 gives the option to introduce +25mV offset to the regulation (See Table 7).
Output voltage is programmed through the VID pins: they are inputs of an internal DAC that is
realized by means of a series of resistors providing a partition of the internal voltage reference.
The VID code drives a multiplexer that selects a voltage on a precise point of the divider. The
DAC output is delivered to an amplifier obtaining the voltage reference available on REF_OUT.
According to the selected DAC, the device also changes the protection thresholds as a
consequence of different CPU specifications, see Table 8 for details.
Table 8. L6701 Configuration
DAC_SEL OPERATIVE MODE
OPEN AMD K8 +25mV (Driven by VID5) 1.9V Fixed -400mV -230mV
82kΩ to GND Intel VR10 -19mV 1.9V Fixed -400mV SSEND
GND Intel VR9 -19mV 2.1V Fixed -400mV -230mV
7.1 Single-Wire CPU Automatic Detection
L6701 has been designed to automatically detect the Intel CPU connected by monitoring the
DAC_SEL pin status at the start-up so modifying the DAC table accordingly (see Table 8). In
fact, by directly connecting the DAC_SEL pin with #BOOTSEL pin of the CPU, the controller
automatically recognize the different technology steps of the CPU so modifying the DAC table
accordingly.
See CPU related documentation for further details about compatibility.
OVP & Pre-
OVP
UVP PGOOD
17/44
8 Driver Section L6701
P
V
3I
3I
++
=
P
3FSWQ
Q
+
=
8 Driver Section
The integrated high-current drivers allow using different types of power MOS (also multiple
MOS to reduce the equivalent R
The drivers for the high-side MOSFETs us e BOOT x pins for supply and PHASEx pins for
return. The drivers for the low-side MOSFETs use the VCC pin for supply and PGND pin for
return.
The controller embodies a anti-shoot-through and adaptive dead-time control to minimize low
side body diode conduction time maintaining good efficiency saving the use of Schottky diodes:
when the high-side MOSFET turns off, the voltage on its source begins to fall; when the voltage
reaches 2V, the low-side MOSFET gate drive is suddenly applied. When the low-side MOSFET
turns off, the voltage at LGATEx pin is sensed. When it drops below 1V, the high-side MOSFET
gate drive is suddenly applied. If the current flowing in the inductor is negative, the source of
high-side MOSFET will never drop. To allow the low-side MOSFET to turn-on even in this case,
a watchdog controller is enabled: if the source of the high-side MOSFET does not drop, the low
side MOSFET is switched on so allowing the negative current of the inductor to recirculate. This
mechanism allows the system to regulate even if the current is negative.
Power conversion input is flexible: 5V, 12V bus or any bus that allows the conversion (See
maximum duty cycle limitations) can be chosen freely.
), maintaining fast switching transition.
DS(on)
8.1 Power Dissipation
L6701 embeds high current MOSFET drivers for both high side and low side MOSFETs: it is
then important to consider the power that the device is going to dissipate in driving them in
order to avoid overcoming the maximum junction operative tempera ture. In addition, since the
device has an exposed pad to better dissipate the power, the thermal resistance between
junction and ambient consequent to the layout is also important: thermal pad need to be
soldered to the PCB ground plane through several VIAs in order to facilitate the heat
dissipation.
Two main terms contribute in the device power dissipation: bias power and drivers' power.
● Device Power (P
pins and it is simply quantifiable as follow (assuming to supply HS and LS drivers with the
same VCC of the device):
● Drivers' power is the power needed by the driver to continuously switch on and off the
external MOSFETs; it is a function of the switching frequency and total gate charge of the
selected MOSFETs. It can be quantified considering that the total power P
switch the MOSFETs (easy calculable) is dissipated by three main factors: external gate
resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance.
This last term is the important one to be determined to calculate the device power
dissipation. The total power dissipated to switch the MOSFETs results:
) depends on the static consumption of the device through the supply
DC
DC
()⋅
CCICC
⋅
CCDRx
⋅
BOOTx
dissipated to
SW
SW
()⋅⋅
⋅
GHSVBOOT
⋅
GLSVCCDRx
External gate resistors helps the device to dissipate the switching power since the same power
P
will be shared between the internal driver impedance and the external resistor resulting in
SW
a general cooling of the device.
18/44
L6701 8 Driver Section
Figure 5. Dissipated Power
19/44
9 Current Sharing Loop and Current Reading L6701
I
R
x
x
I
9 Current Sharing Loop an d Cur re nt Reading
9.1 Current Sharing Loop
L6701 embeds two separate Current Reading circuitries used to perform Current Sharing and
OCP through ISENx pins and Voltage Positioning (Droop Function) through CS+ and CS- pins
(See Section 10).
Current sharing control loop and connections are reported in Figure 6: the current read through
the I
phase and the information about the average current I
device. The error between the read current I
a voltage that with a proper gain is used to adjust the duty cycle whose dominant value is set by
the voltage error amplifier in order to equalize the current carried by each phase.
9.2 Current Reading for Current Sharing
The current flowing trough each phase is read using the voltage drop across the low side
MOSFETs R
current. The trans-conductance ratio is issued by the external resistor R
chip between I
The current sense circuit tracks the current information for a time T
middle of the LS conduction time and holds the tracked information during the rest of the
period. The current that flows from the I
perform current sharing and OCP and it is given by:
where R
conductance resistor connected between the ISENx pins and the LS Drain; I
current carried by the relative phase and I
internally. R
details.
pins is converted into a current I
SENx
or across a sense resistor in its series and it is internally converted into a
DS(on)
and the reading point (usually the LS MOSFET Drain).
SENx
ISENx
is the ON resistance of the low side MOSFET and R
DS(on)
is designed according to the Over Current Protection: see Section 13.6 for
ISENx
proportional to the current delivered by each
INFOx
and the reference I
INFOx
pin is the current information used by the device to
SENx
dsON
----------------- I
==
R
⋅ I
ISEN
PHASEx
is the current information signal reproduced
INFOx
AVG
= ΣI
INFO
/ 3 is internally built into the
INFOx
is then converted into
AVG
ISEN
centered in the
TRACK
is the tra ns-
ISEN
placed outside the
PHASEx
is the
Figure 6. Curre nt Sharing Lo op and Cur rent Rea ding Connections
I
INFO1
PWM1 Out
I
PHASE
I
AVG
20/44
AVG
I
INFO2
From EA
I
INFO3
PWM2 Out
PWM3 Out
ISENx
LGATEx
ISENx
R
ISEN
L6701 10 Output Voltage Positioning
V
VID ROSI
RFBI
P
–+=
I
I
R
---
RPHCPH3
10 Output Voltage Positioning
Output voltage positioning is performed by selecting the reference DAC and by programming
the Droop Function and Offset to the reference (See Figure 7). The current (I
from the FB pin, directly proportional to the read current, causes the output voltage to vary
according to the external R
current (I
to the resistance R
) sourced from the REF_IN pin causes the reference voltage to be offset according
OS
connected.
FB
resistor so implementing the desired load-line resistance. The
FB
The output voltage is then driven by the following relationship:
DROOP
) sourced
OUT
⋅
OS
Both DROOP and OFFSET func tion can be disabled: see Section 10.1 and Section 1 0.3 for
details.
Figure 7. Vo ltage Positioning
OS
VID
I
REF_INREF_OUT
R
OS
C
OS
DROOP
I
FB COMP
R
F
R
FB
C
F
10.1 Load-Line (Droop Function - Optional)
This method "recovers" part of the drop due to the output capacitor ESR in the load transient,
introducing a dependence of the output voltage on the load current: a static error proportional to
the output current causes the output voltage to vary according to the sensed current.
⋅
VSEN
DROO
64k
64k
64k
64k
FBR FBG
T o Vcore
(Remote Sense)
Figure 8 shows the typical Current-Sense Circuit used to implement the Droop-Function in low-
cost application (saves component count). The current flowing across the three inductors is
read through the R
gain and generates a current I
phases. The current I
(I
). RFB gives the final gain to program the desired load-line slope.
DROOP
- CPH filter across CS+ and CS- pins. RD programs a trans-conductance
PH
is then mirrored and, multiplied by three, sourced by the FB pin
CS
proportional to the average of the currents of the three
CS
Considering the scheme reported on Figure 8, it is possible to observe that:
CS
OUT
------------
3
1sL⋅ DCR⁄+
⋅⋅=
--------------------------------------------------- -
1sR⋅
PH
C⋅
PH
DC
----------
3⁄+
R
D
Time constant matching between the inductor (L / DCR) and the current reading filter
( ) is required to implement a real equivalent output impedance of the system so
⁄⋅
avoiding over and/or under shoot of the output voltage as a consequence of a load transient. It
results:
21/44
10 Output V oltage Positio ning L6701
D
-
RPHC
---
I
I
R
---
V
DCR
T
R
R
R
---
L
------------
=
CR
The device forces I
R
implementing the load regulation dependence. The output characteristic vs. load current is
FB
= ICSx3, proportional to the read current, into the feedback resistor
DROOP
⋅
------------------------
3
PH
=>
CS
OUT
------------
3
⋅=
DC
----------
R
D
then given by (Offset disabled):
Where R
OUT
is the resulting load-line resistance implemented by the system.
LL
VID RFBI
⋅– VID R
DROOP
------------- I
⋅⋅– VID RLLI
FB
OUT
R
D
⋅–== =
OU
The whole power supply can be then represented by a "real" voltage generator with an
equivalent output resistance R
resistor can be then designed according to the RLL specifications as follow:
R
FB
where R
Caution: Droop function is optional, in case it is not desired, the Current Sense circuit can be modified so
is typically designed to have I
D
and a voltage value of VID.
LL
LL
⋅=
----------
DC
D
R
FB
= 35µA at the maximum output current (OCP).
CS
that the device always read a null current (See Figure 8). To do this, it is enough to connect
CS+ directly to the outpu t voltage lea ving CS- unconnected. The reaction will keep CS+ and
CS- at the same voltage, always reading a null current and also assuring the FB disconnection
protection to be effective.
Figure 8. Droop Function Current Reading Network
PHASE1
PHASE2
PHASE3
DCR1
L1
DCR2
L2
DCR3
L3
PH
RPHRPHR
C
PH
R
CS+ CS- FB
D
PHASE1
PHASE2
V
OUT
R
FB
C
F
R
F
COMP
PHASE3
CS+ CS- FB
DCR1
L1
DCR2
L2
DCR3
L3
V
OUT
R
FB
C
F
R
F
COMP
I
I
DROOP
CS
x 3
I
I
DROOP
CS
x 3
Droop Function Enabled Droop Function Disabled
10.2 Fully-Differential Load-Line (Droop Function - Optional)
Fully-Differential current-reading for voltage-positioning allows the designer to save time in the
application fine-tuning since the BOM so obtained becomes layout-independent. The patentpending topology offered by L6701 allow implementing fully-differential current-sense still using
only two current-sense pins (CS+ and CS-). Figure 9 shows the typical Current-Sense Circuit
used to implement the Fully-Differential Droop-Function. The current flowing across the three
inductors is read through an R
each phase to program the trans-conductance-gain. As previously mentioned, a current I
proportional to the average of the currents of the three phases is internally generated, mirrored
22/44
- CPH filter for each phase as well as an RD is required for
PH
CS
L6701 10 Output Voltage Positioning
I
1sL⋅DCR
+
DCR
---
L
D
-
H
I
DCR
---
V
DCR
T
R
R
R
R
---
g
and, multiplied by three, sourced by the FB pin (I
). RFB gives the final gain to program
DROOP
the desired load-line slope.
As before, the voltage positioning equations results (See Figure 9):
CSIOUT
⋅⋅=
--------------------------------------------
1sR⋅
+
⁄
PH
----------
C⋅
PH
R
D
As a consequence:
------------ RPHC⋅
=
CR
The device forces I
R
implementing the load regulation dependence. The output characteristic vs. load current is
FB
= ICSx3, proportional to the read current, into the feedback resistor
DROOP
=>
P
CSIOUT
⋅=
----------
R
D
then given by (Offset disabled):
OUT
Where R
VID RFBI
is the resulting differential load-line resistance implemented by the system. The
LLDIFF
⋅– VID 3 R⋅
DROOP
------------- I
⋅⋅– VID R
FB
OUT
R
D
LLDIFFIOU
⋅–== =
whole power supply can be then represented by a "real" voltage generator with an equivalent
output resistance R
resistor can be then designed according to the Load-Line (R
R
FB
and a voltage value of VID.
LLDIFF
) specifications as
LLDIFF
follow:
FB
LLDIFF
--------------------- -
3
⋅=
----------
DC
D
.
where R
is typically designed to have I
D
= 35µA at the maximum output current (OCP).
CS
Table 9 contains a quick-reference guide to design applications with typical and/or differential
current sense.
Figure 9. Fully Differential Load-Line Current-Reading (pat. pend.)
PHASE1
PHASE2
PHASE3
L1
L2
L3
PH
RPHRPHR
CS+ CS- FB
DCR1
DCR2
DCR3
V
OUT
Fully Differential Current Readin
for Load-Line
C
PH
C
PH
C
PH
R
D
R
D
R
D
I
I
DROOP
CS
x 3
R
FB
C
R
F
F
COMP
23/44
10 Output V oltage Positio ning L6701
L
D
-
H
D
-
RPHC
---
R
DCR
---
R
OCP
DCR
---
R
R
R
R
---
R
R
R
---
R
DCR
B
R
DCR
B
V
R
S
=
Table 9. Comparison between different load-line implementations.
Fully-Differential LL Non-Fully-Differ enti al LL
Layout-insen sitive BOM Y N
Time-C onstant Matching
Design (given OCP th.)
R
D
R
Design (given RLL)
FB
(given RD and RFB)
R
LL
10.3 Offset (Optional)
Positive offset can be added to the programmed reference by connecting a ROS resistor
between the REF_OUT and REF_IN pins. Referring to Figure 7, a constant current
(I
=11.5µA) is sourced from the REF_IN pin as soon as the device is enabled, so
OS
programming a fixed voltage drop across R
reference giving the desired offset to the output voltage as follow:
Offset current is suddenly sourced from REF_IN pin as soon as the device implements SoftStart: to avoid having steps during soft-start, the introduction of C
required. The resulting time constant need to be negligible with respect to the soft-start time as
well as long enough to smooth the initial step. Typical values are in the range of few hundreds
of nF.
------------ RPHC⋅
=
CR
OCP
D
LL
--------- -
FB
LL
3
3
------------- R
⋅⋅=
R
D
: this voltage is directly added to the programmed
OS
OS
OSIO
⋅=
⋅=
----------
35µ
----------
DC
⋅
L
------------
P
D
F
(in parallel to ROS) is
OS
CR
D
FB
LL
=
-------------
⋅
------------------------
3
⋅=
----------
3
R
----------
⋅=
LL
DC
------------- R
⋅=
R
D
PH
35µ
D
F
Offset function can be easily disabled simply setting R
Caution: Offset automatically given by the DAC selection differs from the offset implemented through the
OS
= 0.
OFFSET pin: the built-in feature is trimmed in production and assures ±0.7% accuracy over
load and line variations.
10.4 Remote Voltage Sense
L6701 embeds a Remote Sense Buffer to sense remotely the regulated voltage without any
additional external components. In this way, the output voltage programmed is regulated
between the remote buffer inputs compensating motherboard or connector losses. The device
senses the output voltage remotely through the pins FBR and FBG (FBR is for the regulated
voltage sense while FBG is for the ground sense) and reports this voltage internally at VSEN
pin with unity gain eliminating the errors. Keeping the FBR and FBG traces parallel and
guarded by a power plane results in common mode coupling for any picked-up noise.
24/44
L6701 10 Output Voltage Positioning
T
A
0
0
T
10.5 Maximu m Duty Cycle limitation
To provide proper time for current-reading in order to equalize the current carried by each
phase, the device implements a duty-cycle limitation. This limitation is not fixed but it is linearly
variable with the current delivered to the load as follow:
0.80 T
ON max()
=
⎧
⎨
0.40 T
⎩
SWIISENx
SWIISENx
Duty Cycle limitation is variable with the delivered current to provide fast load transient
response at light load as well as assuring robust over-current protection.
Figure 10 shows the maximum output voltage that the device is able to regulate considering the
T
limitation imposed by the previous relationship. If the desired output characteristic crosses
ON
the limited-T
maximum output voltage, the output resulting voltage will start to drop after the
ON
cross-point. In this case, the output voltage starts to decrease following the resulting
characteristic (dotted in Figure 10) until UVP is detected or anyway until I
Figure 10. Maximum Duty Cycle limitation
=⋅
0µA=⋅
35µ
ISENx
= 35µA.
V
OUT
.80 V
.40 V
IN
IN
Maximum Output Voltage
Limted-T
Output Char.
ON
I
= 3 x I
OCP
(I
= 35µA)
ISENx
OCPx
0.80 V
0.40 V
I
OUT
V
OUT
IN
IN
Limted-T
Desired output Char.
Resulting Output Char.
UVP Threshold
Limited TON
Output Char.
ON
I
= 3 x I
OCP
(I
= 35µA)
ISENx
OCPx
I
OU
25/44
1 1 Dynamic VID Transitions L6701
I
C
=
d
d
d
1)
4)
I
d
1)
1)
1)
d
d
d
d
d
d
1)
d
d
d
d
d
11 Dynamic VID Transitions
L6701 is able to manage Dynamic VID Code changes in all its operative modes (VR10, K8 and
also VR9) so allowing Output Voltage modification during normal device operation. PGOOD
(when applicable), OVP and UVP signals are masked during every VID transition and they are
re-activated after the transition finishes with a 32 clock cycles delay to prevent from false
triggering.
When changing dynamically the regulated voltage (D-VID), the system needs to charge or
discharge the output capacitor accordingly. This means that an extra-current
DVID–
OUTdVOUTdTVID
⁄⋅
needs to be delivered, especially when increasing the output regulated voltage and it must be
considered when setting the over current threshold. In the previous relationship, dV
selected DAC LSB (12.5mV for VR10 DAC or 25mV for both VR9 and K8 DACs) and T
OUT
is the
is
VID
the time interval between each LSB transition (typically externally driven). Overcoming the OC
threshold during the dynamic VID causes the device to enter the constant current limitation
slowing down the output voltage dV/dt also causing the failure in the D-VID test.
Figure 11. Dynamic VID Transitions
VID Sample
VID Clock
VID [0,5]
nt. Reference
VID Sample
T
DVID
Ref Moved (2)Ref Moved (3)Ref Moved (
VID Stable
VID Sample
Ref Moved (
VID Sample
VID Sample
VID SampledRef Moved (
VID Sample
VID SampledVID Sample
VID Stable
Ref Moved (
VID Sample
VID Sample
VID Stable
Ref Moved (
VID Sample
VID Stable
VID Sample
Ref Moved (
VID Sample
VID Stable
VID Sample
VID Sample
VID Sample
t
t
T
V
out
sw
x 4 Step VID Transition
Vout Slope Controlled by internal
DVID-Clock Oscillator
T
VID
4 x 1 Step VID Transition
Vout Slope Controlled by external
driving circuit (T
VID
)
t
t
L6701 checks for VID code modifications (See Figure 11) on the rising edge of an internal
additional DVID-clock and waits for a confirmation on the following falling edge. Once the new
code is stable, on the next rising edge, the reference starts stepping up or down in LSB
increments every VID-clock cycle until the new VID code is reached. During the transition, VID
code changes are ignored; the device re-starts monitoring VID after the transition has finished
on the next rising edge available. VID-clock frequency (F
) depends on the operative mode
DVID
selected: for VR10 Mode it is equal to three times the system switching frequency programmed
for each phase (F
and K8, this frequency is lowered to F
26/44
= 3 x FSW) to assure compatibility with the specifications while, for VR9
DVID
DVID
= FSW.
L6701 11 Dynamic VID Transitions
Caution: If the new VID code is more than 1 LSB different from the previous, the device will execute the
transition stepping the reference with the DVID-clock frequency F
reached: for this reason it is recommended to carefully control the VID change rate in order to
carefully control the slope of the output voltage variation especially in VR10 mode.
until the new code has
DVID
Warning: DVID sample and hold clock depends on the switching frequency F
DVID transition so following the VID change rate, it is required to have at least 2 complete
cycles of the F
5µsec., the minimum operating frequency results to be F
clock between every VID transition. If the VID update-rate is, for example,
DVID
> 133kHz in VR10 mode.
SW
. To correctly perform
SW
27/44
12 Soft Start L6701
12 Soft Start
L6701 implements a soft-start to smoothly charge the output filter avoiding high in-rush currents
to be required to the input power supply. The device increases the reference from zero up to
the programmed value in 2048 clock periods and the output voltage increases accordingly with
closed loop regulation. At the end of the digital Soft-Start, SSEND/PGOOD signal is set free.
Protections are active during this phase; Under Voltage is enabled when the reference voltage
reaches 0.6V while Over Voltage is always enabled with a threshold dependent on the selected
Operative Mode. DAC table information is frozen just before initializing the Soft-Start.
The device implements Soft-Start only when all the power supplies are above their own turn-on
thresholds and the EN pin is set free.
12.1 Low-Side-Less Startup (LSLess)
In order to avoid any kind of negative undershoot and dangerous return from the load during
start-up, L6701 performs a special sequence in enabling LS driver to switch: during the softstart phase, the LS driver results disabled (LS = OFF) until the HS starts to switch. This avoid
the dangerous negative spike on the output voltage that can happen if starting over a prebiased output (See Figure 12).
This particular feature of the device masks the LS turn-on only from the control loop point of
view: protections by-pass this turning ON the LS MOSFET in case of need.
Figure 12. LSLess Startup (left) vs. Non-LSLess Startup (right)
28/44
L6701 13 Output volt age M onitor and Protections
I
3FSWQ
+
I
3I
3I
++
+
=
13 Output voltage Monitor and Protections
L6701 monitors through pin VSEN the regulated voltage in order to manage the OVP, UVP and
PGOOD (when applicable) conditions. Protect ions are active also during soft-start (See
Section 12 for details) while are masked during D-VID transitions with an additional 32 clock
cycle delay after the transition has finished to avoid false triggering.
In addition, preliminary over-voltage protection is also provided to protect the load from high-
side MOSFET failures before the syst em turn-ON.
13.1 Under Voltage
If the output voltage monitored by VSEN drops more than -400mV below the programmed
reference for more than one clock period, the device turns off all MOSFETs driving high the
FAULT pin and latches the condition: to recover it is required to cycle Vcc or the EN pin. This is
independent by the selected operative mode.
13.2 Preliminary Over Voltage
To provide a protection while VCC is below the UVLO
threshold is fundamental to avoid
VCC
damage to the load in case of failed HS MOSFETs. In fact, since the device is supplied from the
12V bus, it is basically “blind” for any voltage below the turn-on threshold (UVLO
). In order
VCC
to give full protection to the load, a preliminary-OVP protection is provided while VCC is within
UVLO
and UVLO
VCC
OVP
.
According to the DAC_SEL pin status, this protection turns-on the low side MOSFETs as long
as the FBR pin voltage is greater than 1.9V for VR10 and 2.1V for VR9 and K8 with a 300mV
hysteresis (See Table 10). When set, the protection drives the LS MOSFET with a gate-tosource voltage depending on the voltage applied to VCC. This protection depends also on the
EN pin status as detailed in Figure 13. Preliminary OVP is always active before UVLO
VCC
for
all operative modes with intervention thresholds dependent on the DAC_SEL pin status.
A simple way to provide protection to the output in all conditions when the system is OFF (then
avoiding the unprotected red region in Figure 13-Left) consists in supplying the controller
through the 5VSB bus with an OR-ing diode solution as shown in Figure 13-Right: 5VSB is
always present before +12V and, in case of HS short, the LS MOSFET is driven with 5V
assuring a reliable protection of the load.
When using the OR-ing diode solution, OR-ing diodes need to be sized according to the device
current consumption: the two diodes will then results to be different since the diode connected
to the 12V bus needs to carry the current for normal operations (I
to the 5V
active. Device current consumption (I
(I
SB
RMS-PREOVP
) need to carry only the current in case of Pre-OVP protection is
) in normal operations depends on the external
RMS
) and the diode connected
RMS
MOSFET configuration as follow:
RMS
⋅⋅
()
GHSQGLS
()
CC
⋅
CCDRx
⋅
BOOTx
Device current consumption when Pre-OVP is active depends on the output filter configuration
since LS MOSFETs switching frequency depends on the leakage that is charging the output
filter. Test on the bench is required but, for an over-sized solution, the same diode identified for
the +12V bus can be used.
29/44
13 Output voltage Monitor and Protections L6701
+
U
U
RDI
S
Figure 13. Output Voltage Protections and typical principle connections
V
cc
Preliminary OVP
VLO
VLO
VCC
OVP
FBR/DACSEL Monitor
13.3 Over Voltage
Once VCC crosses the turn-ON threshold and the device is enabled (EN = Free), L6701
provides an Over Voltage Protection according to the DAC_SEL status: when the voltage
sensed by VSEN overcomes the OVP threshold, the controller permanently switches on all the
low-side MOSFETs and switches off all the high-side MOSFETs in order to protect the load.
The FAULT pin is driven high (5V) and power supply or EN pin cycling is required to restart
operations.
The OVP (and Pre-OVP) Threshold varies according to the operative mode selected as
reported in Table 10.
Table 10. OVP and Prelimina ry OVP Thresholds
(EN = 0)
Preliminary OVP Enabled
FBR Monitored
No Protection
(EN = Free)
OVP Protection
VSEN Monitored
Provided
5V
SB
VCC+12V
DAC_SEL Operative Mode Pre-OVP OVP
0VR92.12.1
82kΩ to SGND VR 1 0 1.9 1.9
Open K8 1.9 1.9
13.4 Feedback Disconnection
L6701 allows to monitor the output voltage in two different points:
● Remotely, through the remote buffer, across VSEN
● Locally across the CS- pin (negligibly offset by ).
By comparing the voltage present at these two different locations, L6701 is able to understand
if the output voltage feedback is connected. When CS- is more than 1V higher than VSEN,
(See Figure 14) the device stops switching with the low side MOSFETs permanently ON and
drives high the FAULT pin. The condition is latched until VCC or EN cycled.
⋅
C
30/44
L6701 13 Output volt age M onitor and Protections
R
I
-- -
I
I
I
I
---
Figure 14. Feedback Disconnection
DCR1
PHASE1
PHASE2
PHASE3
L1
DCR2
L2
DCR3
L3
RDRDR
D
C
D
R
CS_DROOP+ CS_DROOP- FB
G
V
OUT
I
I
DROOP
INFO
x 3
VID
R
FB
R
F
C
F
COMP VSEN FBR FBG
1V
FB_DISCONNECTED
13.5 PGOOD (Only for VR9 and K8 Modes)
It is an open-drain signal set free after the soft-start sequence has finished. It is pulled low
when the output voltage drops below -230mV of the programmed voltage.
13.6 Over Current Protection
Output current in each phase is monitored by L6701 through R
value of these resistors, it is possible to set the OCP to the desired value. The Over Current
threshold has to be programmed to a safe value, in order to be sure that the device doesn't
enter OCP during normal operation of the device. This value must take into consideration also
the extra current needed during the Dynamic VID Transition I
across MOSFETs R
elements. Moreover, since also the internal threshold spreads, the Rg design has to consider
the minimum value I
where I
is the current measured by the current reading circuitry when the device enters
OCPx
Quasi-Constant-Current.
Since the device reads the current across Low Side MOSFETs, it limits the bottom of the
inductor current entering in constant current until setting UVP as below explained. I
be calculated starting from the corresponding output current value I
must also be considered when D-VID are supported) since the device holds the valley current
information:
, the process spread and temperature variations of these sensing
DS(on)
OCTH(min)
of the threshold as follow:
g
OCPx
OCPx max()RdsON max()
---------------------------------------------------------------
=
OUT OCP()
--------------------------- -
3
⋅
I
OCTH min()
∆
PP
------------
2
+–=
---------------
and so, programming the
ISEN
and, since the device reads
D-VID
OUT(OCP)
DVID–
as follo w (I
3
OCPx
must
D-VID
where I
OUT(OCP)
Current, I
PP
is still the output current value at which the device enters Quasi-Constant-
is the inductor current ripple in each phase and I
is the additional current
D-VID
required by D-VID (when applicable). In particular, since the device limits the valley of the
31/44
13 Output voltage Monitor and Protections L6701
I
VINV
–
VINV
–
I
I
–
T
I
–
F
--- -
T
I
I
inductor current, the ripple entity , when not negligible, impacts on the real OC threshold value
and must be considered.
The device detects an Over Current condition for each phase when the current information
overcomes the fixed threshold of I
I
ISENx
. When this happens, the device keeps the
OCTH
relative LS MOSFET on, also skipping clock cycles, until the threshold is crossed back and
I
results being lower than the I
ISENx
threshold (this implies that the device limits the bottom
OCTH
of each inductor current ripple). After exiting the OC condition, the LS MOSFET is turned off
and the HS is turned on with a duty cycle driven by the PWM comparator.
The device enters in Quasi-Constant-Current operation: the low-side MOSFETs stays ON until
the current read becomes lower than I
side MOSFET can be then turned ON with a T
OCPx
(I
< I
INFOx
imposed by the control loop after the LS turn-
ON
) skipping clock cycles. The high
OCTH
off and the device works in the usual way until another OCP event is detected.
This means that the average current delivered can slightly increase in Quasi-Constant-Current
operation since the current ripple increases. In fact, the ON time increases due to the OFF time
rise because of the current has to reach the I
bottom. The worst-case condition is when
OCPx
the ON time reaches its maximum value (see Section 10.5). When this happens, the device
works in Real Constant Current and the output voltage decrease as the load increase. Crossing
the UVP threshold causes the device to latch driving high the OSC pin.
It can be observed that the peak current (I
) is greater than I
PEAK
but it can be determined
OCPx
as follow:
PEAKIOCPx
Where V
------------------------------------------ - T
is the UVP threshold, (inductor saturation must be considered). When that
outMIN
OUT min()
L
⋅+ I
ON max()
OCPx
------------------------------------------ - 0.40 T⋅
OUT min()
L
⋅+==
SW
threshold is crossed, all MOSFETs are turned off, the FAULT pin is driven high and the device
stops working. Cycle the power supply or the EN pin to restart operation.
The maximum average current during the Constant-Current behavior results (see Figure 15):
MAX tot,
3I
⋅ 3I
MAX
⋅==
⎛⎞
OCPx
⎝⎠
PEAKIOCPx
-------------------------------------+
2
in this particular situation, the switching frequency for each phase results reduced. The ON time
is the maximum allowed T
OFF
ON(max)
while the OFF time depends on the application:
PEAKIOCPx
L
------------------------------------ -⋅= f
V
OUT
=
------------------------------------------
T
ON max()TOF
1
+
Figure 15. Constant Current Operation
Constant Current (Exploded)
V
0.40 V
OUT
IN
Limted-TON Char.
Resulting Out. Char.
UVP Threshold
I
OCP
(I
DROOP
= N x I
OCPx
= N x 35µA)
Droop Effect
Current
Quasi-Const.
I
MAX,tot
I
OU
PEAK
I
MAX
OCPx
T
ON(max)
T
SW
LS ON Skipping
Clock Cycles
T
ON(max)
T
SW
32/44
L6701 13 Output volt age M onitor and Protections
R
I
--- -
I
I
I
I
---
The trans-conductance resistor R
can be designed considering that the device limits the
ISENx
bottom of the inductor current ripple and also considering the additional current delivered
during the quasi-constant-current behavior as previously described in the worst case
conditions.
Moreover, when designing D-VID compatible systems, the additional current due to the output
filter charge during dynamic VID transitions must be considered.
∆
PP
------------
2
+–=
---------------
DVID–
3
ISENx
OCPx max()RdsON max()
--------------------------------------------------------------
=
⋅
I
OCTH min()
where
OCPx
OUT OCP()
--------------------------- -
3
33/44
14 Oscillator L6701
F
6
---
14 Oscillator
The internal oscillator generates the triangular waveform for the PWM charging and
discharging with a constant current an internal capacitor. The switching frequency for each
channel, F
side results in being tripled (300kHz).
The current delivered to the oscillator is typically 25µA (corresponding to the free-running
frequency F
between the OSC pin and SGND. Since the OSC pin is fixed at 1.24V, the frequency is
increased proportionally to the current sunk from the pin considering the internal gain of 4KHz/
µA.
, is internally fixed at 100kHz so that the resulting switching frequency at the load
SW
=100kHz) and it may be varied using an external resistor (R
SW
) connected
OSC
In particular connecting R
to SGND the frequency is increased according to the following
OSC
relationship:
R
vs. SGND
OSC
Caution: Maximum programmable switching frequency per phase must be limited to 500kHz to avoid
SW
100k Hz
1.240V
---------------------------- 4
R
OSC
kΩ()
kHz
---------- -⋅+ 100 kHz
µA
+==
⋅
4.96 10
-------------------------
R
OSC
kΩ()
current reading errors causing, as a consequence, current sharing errors. Anyway, device
power dissipation must be checked prior to design high switching frequency systems.
Figure 16. R
vs. Switching Frequency
OSC
250
200
150
100
Rosc [kOhms] to SGND
50
0
100 150 200 250 300 350 400 450 500 550
Fsw [kHz] Programmed
34/44
L6701 15 System Control Loop Compensation
G
PWM ZFs()R
s
+
--- -
R
DCR
B
DCR
15 System Control Loop Com pensation
The control loop is composed by the Current Sharing control loop (See Figure 17) and the
Average Current Mode control loop. Each loop gives, with a proper gain, the correction to the
PWM in order to minimize the error in its regulation: the Current Sharing control loop equalize
the currents in the inductors while the Average Current Mode control loop fixes the output
voltage equal to the reference programmed by VID. Figure 17 shows the block diagram of the
system control loop.
The system Control Loop is reported in Figure 18. The current information I
the DROOP pin flows into R
implementing the dependence of the output voltage from the
FB
DROOP
sourced by
read current.
Figure 17. Main Control Loop
L3
L2
L1
Reference
ZF(s) ZF(s)
C
OUTROUT
I
DROOP
1 / 5
1 / 5
1 / 5
CURRENT SHARING
DUTY CYCLE
CORRECTION
I
INFO1
I
INFO2
I
INFO3
PWM3
PWM2
PWM1
ERROR AMPLIFIER
4 / 5
COMP FB
The system can be modeled with an equivalent single phase converter which only difference is
the equivalent inductor L/3 (where each phase has an L inductor).The Control Loop gain results
(obtained opening the loop after the COMP pin):
()
1
----------- -+
As()
RFB⋅+⋅
LOOP
s()
()⋅⋅
----------------------------------------------------------------------------------------------------------------
–=
Z
s() ZLs()+[]
P
DROOPZP
s()
Z
F
-------------- - 1
As()
⎛⎞
⎝⎠
Where:
● is the equivalent output resistance determined by the droop function
DROOP
( for fully differential current sense);
R
DROOP
● Z
(s) is the impedance resulting by the parallel of the output capacitor (and its ESR) and
P
the applied load R
● Z
● Z
● A(s) is the er r or amplifier gain ;
(s) is the compensation network impedance;
F
(s) is the parallel of the three inductor impedance;
L
------------- R
⋅=
R
D
3
⋅⋅=
F
------------- R
R
D
;
O
FB
35/44
15 System Control Loop Compensation L6701
P
V
--- -
V
ZFs
ROR
+
1sCOR
//ROESR+
+
--- -
D
R
R
V
---
C
L
3
-- -
---
4
● is the PWM transfer function where ∆V
WM
---
5
---------------
⋅=
∆V
IN
OSC
is the oscillator ramp
OSC
amplitude and has a typical value of 3V .
Removing the dependence from the Error Amplifier gain, so assuming this gain high enough,
and with further simplifications, the control loop gain results:
G
LOOP
s()
4
-- -
⋅⋅⋅ ⋅–=
5
IN
----------------- -----
∆V
OSC
---------------
R
FB
()
DROOP
------------------- ------------------------ -
R
L
R
-------+
O
3
----------------- --------------------------------- --------------------------------- -------------------------- --------------------------
s2C
L
----⋅⋅s
O
3
()⋅⋅
DROOP
L
---------------- -- COESR⋅ C
3 R
⋅
O
R
L
-------⋅++1+⋅+
O
3
The system Control Loop gain (See Figure 18) is designed in order to obtain a high DC gain to
minimize static error and to cross the 0dB axes with a constant -20dB/dec slope with the
desired crossover frequency ω
. Neglecting the effect of ZF(s), the transfer function has one
T
zero and two poles; both the poles are fixed once the output filter is designed (LC filter
resonance ω
) and the zero (ω
LC
) is fixed by ESR and the Droop resistance.
ESR
Figure 18. E qu ivalent Contro l Loop Block Diagram (left) and Bode Diagram (right).
DROOP
I
ROOP
Reference
FB COMP
d V
L / N
PWM
V
OUT
OUT
REMOTE BUFFER
64k
64k
64k
ESR
C
O
FBG
FBR
V
OUT
R
O
RF[dB]
dB
G
(s)
LOOP
K
(s)
Z
F
R
(s)
FCF
R
FB
ZF(s)
Z
FB
To obtain the desired shape an R
implementation. A zero at ω
integrator minimizes the static error while placing the zero ω
VSEN
=
ω
ω
LC
F
ω
ESR
- CF series network is considered for the ZF(s)
F
= 1/RFCF is then introduced together with an integrator. This
F
in correspondence with the L-C
F
ω
T
resonance assures a simple -20dB/dec shape of the gain.
In fact, considering the usual value for the output filter, the LC resonance results to be at
frequency lower than the above reported zero.
Compensation network can be simply designed placing ω
frequency ω
of the switching frequency F
as desired obtaining (always considering that ωT might be not higher than 1/10th
T
FB
----------------------------------
F
):
SW
∆
⋅
V
IN
OSC
5
-- - ω
⋅⋅ ⋅=
4
----------------------------------------------------
T
3R
L
DROOP
and imposing the cross-over
F=ωLC
C
⋅
=
O
-----------------
R
F
ESR+()⋅
F
ω
36/44
L6701 15 System Control Loop Compensation
s)
R
15.1 Compensation Network Guidelines
The Compensation Network desig n ass ur es to havin g system response according to the cro ssover frequency selected and to the output filter considered: it is anyway possible to further finetune the compensation network modifying the bandwidth in order to get the best response of
the system as follow (See Figure 19):
● Increase R
● Decrease R
● Increase C
phase margin.
Having the fastest compensation network gives not the confidence to satisfy the requirements
of the load: the inductor still l i mits the maximum dI/dt that the system can afford. In f a ct, when a
load transient is applied, the best that the controller can do is to “saturate” the duty cycle to its
maximum ( d
charge / discharge time and by the output capacitance. In particular, the most limiting transition
corresponds to the load removal since the inductor results being discharged only by V
(while it is charged by d
Referring to Figure 19-left, further tuning the Compensation network cannot give any
improvements unless the output filter changes: only modifying the main inductors or the output
capacitance improves the system response.
to increase the system bandwidth accordingly;
F
to decrease the system bandwidth accordingly;
F
to move ωF to low frequencies increasing as a consequence the system
F
) or minimum (0) value. The output voltage dV/dt is then limited by the inductor
MAX
MAXVIN-VOUT
during a load appliance).
OUT
Figure 19. B est Load Transient achievable (d=0) and R
dB
K
[dB]
F
impact on Bandwidth.
F-CF
C
F
G
(s)
LOOP
ω
= ω
LC
F
ω
ESR
ω
T
Z
(
F
R
F
ω
37/44
16 Layout Guideline s L6701
16 Layout Guidelines
Since the device manages control functions and high-current drivers, layout is one of the most
important things to consider when designing such high current applications. A good layout
solution can generate a benefit in lowering power-dissipation on the power paths, reducing
radiation and a proper connection between signal and power ground can optimize the
performance of the control loops.
Two kind of critical components and connections have to be considered when layouting a VRM
based on L6701: power components and connections and small signal components
connections.
16.1 Power Compone n ts and Connections
These are the components and connections where switching and high continuous current flows
from the input to the load. The first priority when placing components has to be reserved to this
power section, minimizing the length of each connection and loop as much as possible. To
minimize noise and voltage spikes (EMI and losses) these interconnections must be a part of a
power plane and anyway realized by wide and thick copper traces: loop must be anyway
minimized. The critical components, i.e. the power transistors, must be close one to the other.
The use of multi-layer printed circuit board is recommended.
Figure 20 shows the details of the power connections involved and the current loops. The input
capacitance (C
to the power section in order to eliminate the stray inductance generated by the copper traces.
Low ESR and ESL capacitors are preferred, MLCC are suggested to be connected near the HS
drain.
Use proper VIAs number when power traces have to move between different planes on the
PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the
same high-current trace on more than one PCB layer will reduce the parasitic resistance
associated to that connection.
Connect output bulk capacitor as near as possible to the load, minimizing parasitic inductance
and resistance associated to the copper trace also adding extra decoupling capacitors along
the way to the load when this results in being far from the bulk capacitor bank.
Gate traces must be sized according to the driver RMS current delivered to the power
MOSFET. The device robustness allows managing applications with the power section far from
the controller without losing performances. Anyway, when possible, it is suggested to minimize
the distance between controller and power section.
), or at least a portion of the total capacitance needed, has to be placed close
IN
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L6701 16 Layout Guidelines
U
P
16.2 Small Signal Components and Connections
These are small signal components and connections to critical nodes of the application as well
as bypass capacitors for the device supply (See Figure 20). Locate the bypass capacitor (VCC
and Bootstrap capacitor) close to the device and refer sensible components such as frequency
set-up resistor R
a single point to avoid that drops due to the high current delivered causes errors in the device
behavior.
VSEN pin filtered vs. SGND helps in reducing noise injection into device: take care in routing
driving net for this pin in order to minimize coupled noise.
Remote Buffer Connection must be routed as parallel nets from the FBG/FBR pins to the load
in order to avoid the pick-up of any common mode noise. Connecting these pins in points far
from the load will cause a non-optimum load regulation, increasing output tolerance.
Locate current reading components close to the device. It's also important to minimize any
offset in the measurement and, to get a better precision, to connect the traces as close as
possible to the sensing elements.
Caution: B oot Capacitor Extra Charge. Systems that do not use Schottky diodes might show big
negative spikes on the phase pin. This spike can be limited as well as the positive spike but has
an additional consequence: it causes the bootstrap capacitor to be over-charged. This extracharge can cause, in the worst case condition of maximum input voltage and during particular
transients, that boot-to-phase voltage overcomes the abs. max. ratings also causing device
failures. It is then suggested in this cases to limit this extra-charge by:
– adding a small resistor in series to the boot diode (one resistor can be enough for all
the three diodes if placed upstream the boot diode anode, see Figure 20)
– using non-capacitive boot diodes (such as standard diodes).
to SGND. Star grounding is suggested: connect SGND to PGND plane in
OSC
Figure 20. Power connections and related connections layout (same for all phases).
GATEx
HASEx
LGATEx
PGNDx
V
IN
C
IN
L
LOAD
To limit C
BOOTx
PHASEx
VCC
SGND
Extra-Charge
BOOT
BOOT
C
+Vcc
V
IN
C
IN
L
LOAD
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16 Layout Guideline s L6701
16.3 Embedding L6701-based VRs
When embedding the VR into the application, additional care must be taken since the whole VR
is a switching DC/DC regulator and the most common systems in which it has to work are
digital systems such as MB or similar. In fact, latest MB has become faster and powerful: high
speed data bus are more and more common and switching-induced noise produced by the VR’
MOSFETs can affect data integrity if not following additional layout guidelines. Few easy points
must be considered mainly when routing traces and planes in which high switching currents
flow (high switching currents cause voltage spikes across the stray inductance of the trace
causing noise that can affect the near traces):
Keep safe guarding distance between high current switching VRD traces and data buses,
especially if high-speed data bus to minimize noise coupling.
Keep safe guard distance or filter properly when routing bias traces for I/O sub-systems that
must walk near the VRD.
Possible causes of noise can be located in the PHASE connections, MOSFET gate drive and
Input voltage path (from input bulk capacitors and HS drain). Also PGND connections must be
considered if not insisting on a power ground plane. These connections must be carefully kept
far away from noise-sensitive data bus.
Since the generated noise is mainly due to the switching activity of the VR, noise emissions
depend on how fast the current switches. To reduce noise emission levels, it is also possible, in
addition to the previous guidelines, to reduce the current slope by properly tuning the HS gate
resistor and the PHASE snubber network.
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L6701 17 Package Mechanical Data
17 Package M echanical Data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second Level Interconnect is marked on the package and on the inner box label, in compliance
with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label. ECOP ACK is an ST trademark. ECOPACK specifications are
available at: www.st.com.
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17 Package Mechanical Data L6701
PowerSSO-36 Mecha nical Data
Dim.
Min. Typ. Max. Min. Typ. Max.
A 2.15 2.47 0.084 0.097
A2 2.15 2.40 0.084 0.094
a1 0 0.075 0 0.003
b 0.18 0.36 0.007 0.014
c 0.23 0.32 0.009 0.012
D
(1)
(2)
E
10.10 10.50 0.398 0.413
7.4 7.6 0.291 0.299
e 0.50 0.020
e3 8.50 0.035
F 2.3 0.090
G 0.10 0.004
G1 0.06 0.002
H 10.10 10.50 0.398 0.413
h 0.40 0.016
L 0.55 0.85 0.022 0.033
M 4.3 0.169
N 10° (max)
O 1.2 0.047
Q 0.8 0.031
S 2.9 0.114
T 3.65 0.144
U 1.0 0.039
X 4.10 4.70 0.161 0.185
Y 6.50 7.10 0.256 0.279
mm inch
1. “D and E” do not i nclude mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006”)
2. No intrusion allowed inwards the leads.
3. Flash or bleeds on exposed die pad shall not exceed 0.4 mm per side
Figure 21. Package Dimensions
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L6701 18 Revision history
18 Revision history
Date Revision Description of Changes
13-Dec-2005 1 First draft
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18 Revision history L6701
I
s
o
d
b
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t
ot
a
nformation furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequence
f use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is grante
y implic ation or oth erwise unde r any patent or patent rights of S T M i croelectronics. Spec i fications me ntioned in this publication are s ubje
o change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are n
uthoriz ed for use as crit ical component s i n l i fe support devices or systems wi th out express wr i tt en approval of STM i croelectronics.
The ST logo is a registered trademark of STM i croelectroni cs.
All other nam es are the property of their respective ow ners
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