ST L6701 User Manual

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3 Phase Controller for VR10, VR9 and K8 CPUs

Features

■ MULTI-DAC: VR9, VR10 AND K8 DAC

SELECTABLE THROU GH SING L E PIN

■ 0.7% OUTPUT VOLTAGE ACCURACY

■ ADJUSTABLE REFEREN CE OFFSET

■ HIGH CURRENT INTEGRATED DRIVERS

■ DYNAMIC VID MANAGEMENT

■ ACCURATE FULLY-DIFFERENTIAL LOAD-

LINE CURRENT-SENSE ACROSS MAIN INDUCTORS MAKES BOM INDEPENDENT ON THE LAYOUT

■ PRECISE CURRENT-SHARING AND OCP

ACROSS LS M OSFET S

■ CONSTANT OVER-CURRENT PROTECTION

■ FEEDBACK DISCONNECTION

PROTECTION

■ PRELIMINARY OV PROTE CTIO N

■ OSCILLATOR INTERNALLY FIXED AT

100kHz (300kHz RIPPLE) EXT ADJUSTABLE

■ SS_END / PGOOD SIGNAL

■ INTEGRATED REMOTE-SENSE BUFFER

■ PWSSO36 PACKAGE WITH EXPOSED PAD

Applications

■ HIGH CURRENT VRM / VRD FOR DESKTOP

/ SERVER/ WORKSTATION CPUs

■ HIGH DENSITY DC / DC CONVERTERS

L6701

PowerSSO-36

Description

L6701 is an extremely simple, low-cost solution to implement a three phase step-down controller with integrated high-current drivers in a com pact PowerSSO-36 package with exposed pad.

The device embeds three selectable DACs: with a single pin it is possible to pro gram the device to work in compatibility with VR9, VR10 or K8 applications managing D-VID with ±0.7% output voltage accuracy over line and temperature variations. Additional programmable offset can be added to the reference voltage with a single external resistor.

Fast protection against load over current let the system works in Constant Current mode until UVP. Preliminary OVP allows full load protection in case of startup with failed HS. Furthermore, feedback disconnection prevents from damaging the load in case o f misconnections in the system board.

Combined use of DCR and R sensing assures precision in voltage positioning and safe current sharing and OCP per each phase.

DS(on)

current

Order co des

Part number Package Packing

L6701 PowerSSO-36 Tube

L6701TR PowerSSO-36 Tape & Reel

Rev 1

December 2005 1/44

www.st.com

L6701

Contents

1 Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . . 11

5.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

5.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6 VID Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7 Configuring the Device: DAC Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.1 Single-Wire CPU Automatic Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8 Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8.1 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

9 Current Sharing Loop and Current Reading . . . . . . . . . . . . . . . . . . . . . . . 20

9.1 Current Sharing Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

9.2 Current Reading for Current Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

10 Output Voltage Positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

10.1 Load-Line (Droop Function - Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

10.2 Fully-Differential Load-Line (Droop Function - Optional) . . . . . . . . . . . . . . . 22

10.3 Offset (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

10.4 Remote Voltage Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

10.5 Maximum Duty Cycle limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2/44

L6701

11 Dynamic VID Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

12 Soft Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

12.1 Low-Side-Less Startup (LSLess) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

13 Output voltage Monitor and Protections . . . . . . . . . . . . . . . . . . . . . . . . . . 29

13.1 Under Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

13.2 Preliminary Over Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

13.3 Over Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

13.4 Feedback Disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

13.5 PGOOD (Only for VR9 and K8 Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

13.6 Over Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

14 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

15 System Control Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

15.1 Compensation Network Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

16 Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

16.1 Power Components and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

16.2 Small Signal Components and Connections . . . . . . . . . . . . . . . . . . . . . . . . . 39

16.3 Embedding L6701-based VRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

17 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3/44

1 Device Descr iption L6701

1 Device Description

L6701 is multi-phase PWM controller with embedded high-current drivers that provides complete control logic and protections for a high-performance step-down DC-DC voltage regulator, optimized for advanced microprocessor power supply. Multi-phase buck is the simplest and most cost-effective topology employable to satisfy the increasing current demand of newer microprocessors and the modern high-current DC/DC converters and POLs requirements. It allows distributing equally load and power between the phases using smaller, cheaper and most common external power MOSF ETs and inductors. Moreover, thanks to the equal phase-shift between each phase, the input and output capacitor count results in being reduced. Phase-interleaving causes in fact input rms current and output ripple voltage reduction and shows an effective output switching frequency increase: the 100kHz free-running frequency per phase, externally adjustable through a resistor, results multiplied on the output by the number of phases so reaching 300kHz in free-running.

L6701 includes multiple DACs, selectable through an apposite pin, allowing compatibility with both Intel VR9, VR10 and AMD Hammer specifications, also performing D-VID transitions accordingly. In particular for Intel CPUs, it allows to automatically recognize the CPU with a single-wire connection, without any additional external component, by proper connecting the selector pin to the proper CPU pin.

Precise voltage positioning (LL) is possible thanks to an accurate fully-differential current-sense across the main inductors still using only two pins for current-reading (pat. pend.): this makes any BOM insensitive to the board layout saving time in the design stage.

The device internally balance the current driven by each phase by sensing the voltage drop across the LS MOSFET R causing the device to work in constant-current mode.

The controller provides output voltage protections to avoid any load damage due to failed components and/or feedback misconnec tions. Over-Voltage protects the load from dangerous over stress latching immediately the device by turning-on the lower driver and driving high the FAULT pin. Furthermore, preliminary-OVP protection also allows the device to protect the load from dangerous OVP when V causes the device to stop switching when set while Over-Current protection, with a threshold for each phase, causes the device to enter in constant current mode until the latched UVP.

L6701 implements soft-start increasing the reference up to the final value in 2048 clock cycles in closed loop regulation. Low-Side-Less feature allows the device to perform soft-start over pre-biased output avoiding dangerous current return through the main inductors as well as negative spike at the load side.

The compact PowerSSO-36 package with exposed thermal pad allows dissipating the power to drive the external MOSFET through the system board.

. OC protection is effective with a threshold for each phase

DS(on)

is not above the UVLO threshold. Under-Voltage protection

4/44

L6701 2 Pins descrip tion and connection diagrams

2 Pins description a nd connection diagram s

Figure 1. Pins connection (Top view)

SSEND / PGOOD

OSC / EN / FAULT

2.1 Pin description

Table 1. Pins description

Pin n°

1SGND

2VCC

Name Function

SGND

VCC

LGATE1

PGND LGATE2 LGATE3

BOOT1 UGATE1 PHASE1

BOOT2 UGATE2 PHASE2

BOOT3 UGATE3 PHASE3

DAC_SEL

COMP FB VSEN CSCS+ ISEN1 ISEN2 ISEN3 FBG FBR VID5 VID0 VID1 VID2 VID3 VID4 REF_OUT REF_IN

All the internal references are referred to this pin. Co nnect to the PCB Signal Ground.

Device Power Supply and LS driver supply. Operative voltage is 12V ±15%. Filter with at least 1µF MLCC vs. ground.

3LGATE1

Channel 1 LS Driver Output. A small series resist or hel ps in reducing device-dissipat ed power.

4 PGND LS Drivers return path. Connect to Power ground Plane.

5LGATE2

6LGATE3

Channel 2 LS Driver Output. A small series resist or hel ps in reducing device-dissipat ed power.

Channel 3 LS Driver Output. A small series resist or hel ps in reducing device-dissipat ed power.

Channel 1 HS driver supply. Connect through a capacitor (100nF typ.) to PHASE1 and provide necessary

7 BOOT1

Bootstrap dio de. A small series resistor upstream the boot diode helps i n reducing Boot cap acitor

overcharge.

8UGATE1

Channel 1 HS driver output. A small series resistors helps in reducing device-dissipated power.

Channel 1 HS driver return path.

9 PHASE1

It must be connected to the HS1 MOSFET sour ce and provides return path for the HS driver of channel 1.

5/44

2 Pins description and connection diagrams L6701

Table 1. Pins description (continued)

Pin n°

Name Function

10 BOOT2

11 UGATE2

12 PHASE2

13 BOOT3

14 UGATE3

15 PHASE3

Channel 2 HS driver supply. Connect through a capacitor (100nF typ.) to PHASE2 and provide necessary

Bootstrap dio de. A small series resistor upstream the boot diode helps i n reducing Boot cap acitor

overcharge. Channel 2 HS driver output.

A small series resistors helps in reducing device-dissipated power. Channel 2 HS driver return path.

It must be connected to the HS2 MOSFET sour ce and provides return path for the HS driver of channel 2.

Channel 3 HS driver supply. Connect through a capacitor (100nF typ.) to PHASE3 and provide necessary

Bootstrap dio de. A small series resistor upstream the boot diode helps i n reducing Boot cap acitor

overcharge. Channel 3 HS driver output.

A small series resistors helps in reducing device-dissipated power. Channel 3 HS driver return path.

It must be connected to the HS3 MOSFET sour ce and provides return path for the HS driver of channel 3.

SSEND /

PGOOD

17 DAC_SEL

OSC / EN /

FAULT

SSEND - Intel VR10 Mode. Soft Start END Signal. Open Drain Output set free af ter SS has finished and pulled low when triggering

any protection. Pull up to 5V (typ) or lower , if not used it can be left floating. PGOOD - Intel VR9 & AMD Hammer Mode. Open Drain Output set free after SS has finished and pulled low when VSEN is

lower than t he relative threshold. Pull up to 5V (typ) or lower, if n ot used it can be left floati ng.

DAC SELection pin.

It allows progr ammin g the DAC tabl e for th e regul atio n. Int ernal ly pull ed- up to 5V. Short to GND to program VR9 DAC, leave floating to progr am K8 DAC while connect to GND t hrough 82kΩ to program VR10 DAC.

Information about the selected DAC is latched bef ore the system start-up. See

Section 7.1 for connections to enab le CPU auto-detection.

OSC: It allows programming t he swit ching frequency F

of each channel.

Switching frequency can be increased according to the resistor connected from the pin vs. SGND with a gain of 4kHz/µA (see Section 14). Leaving the pin floating it program s a switching frequency of 100kHz per phase (300kHz on the load).

EN: Forced low, the device stops operations with all MOSFETs OFF: all the protections are disabled except for Preliminary Over Voltage. When set low it resets the devi ce from any latching condition.

FAULT: The pin is forc ed high (5V) to signal an OVP / UVP FAULT: to recover from this conditio n, cycle VCC or the OSC pin. See Section13 for details.

6/44

L6701 2 Pins descrip tion and connection diagrams

Table 1. Pins description (continued)

Pin n°

Name Function

19 REF_IN

20 REF_OUT

VID4

21 to 26

VID0, VID5

27 FBR

28 FBG

ISEN3

29 to 31

ISEN1

Reference Input for the regul ation. Connect directly or through a resistor to the REF_OUT pin. See Section 10.3 for

details. This pi n is used as input for the protections. Reference Output.

Connect directly or through a resistor to the REF_IN pin. See Section 10.3 for details.

Voltage IDentific ati on Pins. Internally pulled up by 12.5µA to 5V , connect to SGND to program a '0' or leave

floating to progra m a '1' . They allow programming outp ut vol tage as specified in

Table 5, Table 6 and Table 7 according to DAC_SEL status.

Remote Buffer Non Inverting Input. Connect to the positiv e side of the load to perform remote sense. See Section 16 for proper layout of this connection.

Remote Buffer Inverting Input. Connect to the negative si de of the load to perform remot e sense. See Section 16 for proper layout of this connection.

LS Current Sense Pins. These pins are used for current balance phase-to-phase as well as for the

system OCP. Connect through a resi stor R

to the relative PHASEx pin. See

ISEN

Section 9 and Section 13.6 for details.

32 CS+

33 CS-

34 VSEN

35 FB

36 COMP

PAD

THERMAL

PAD

Droop Current Sense non-inverting input. Connect through R

network to the main inductors. Directly connect to

PH-CPH

output voltage wh en Droop function is not required. See Section 10.1 and

Section 10.2 for details.

Droop Current Sense inverting input. Connect through resistor R

to the main inductors common node. Le ave floating

when Droop Function is not required. See Section 10.1 and Section 10.2 for details.

This pin also monitors t he output for any feedback di sconnection. See

Section 13.4 for details.

Remote Buffer Out put. It manages OVP and UVP protections and PGOOD (when applicable). See Section 13 for details.

Error Amplifier Inver ting I nput. Conn ect with a resi stor R R

- CF toward COMP.

Error Amplifier Output . Connect with an R

- CF vs. FB.

vs. VSEN and with an

The device cannot be disabled by pulling down this pin. Thermal pad connects the Silicon substrate and makes good thermal contact

with the PCB to dissipate the power necessary to drive the ext ernal MOSFETs. Connect to the PGND plane with sever al VI As to i mprove thermal conductivity.

7/44

3 Maximum Ratings L6701

3 Maximum Ratings

3.1 Absolute maxi mum ratings

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

BOOTx

UGATEx

- V

PHASEx

to PGND 15 V Boot Vol tage 15 V

15 V

LGA TEx, PHASEx, to PGNDx

-0.3 to VCC + 0.3

VID0 to V ID 5 -0.3 to 5 V All other Pins to PGNDx -0.3 to 7 V

PHASEx

Positive Peak Voltage; T<20ns @ 600kHz 26 V Negative Peak Voltage; TBD V

3.2 Thermal data

Table 3. Thermal data

Symbol Parameter Value Unit

T T

THJA

THJC

MAX

STG

TOT

Thermal Resistan ce Junction to Ambient (Device soldered on 2s2p PC Board)

30 °C/W

Thermal Resistan ce Junction to Case 1 °C/W Maximum Junction Temperature 150 °C Storage Temperature Range -40 to 150 °C Junction Temperature Range 0 to 125 °C

Maximum Power Dissipation at 25°C (Device soldered on 2s2p PC Board)

3.3 W

8/44

L6701 4 Electrical specifications

4 Electrical specifications

4.1 Electrical characteristics

Table 4. Electrical Characteristics

= 12V±15%, TJ = 0°C to 70°C unless otherwise specified).

Symbol Parameter Te st condi tions Min. Typ. Max. Unit

Supply Current and Power-ON

BOOTx

UVLO

VCC Supply current

BOOTx Supply Current

VCC Turn-ON VCC Rising

VCC

Turn-OFF VCC Falling

Pre-OVP Turn-ON

OVP

Pre-OVP Turn-OFF

HGATEx and LGATEx = OPEN BOOTx = 12V

HGA TEx = OPEN; PHASEx to PGNDx; BOOTx = 12V

Rising

Falling

17 mA

0.7 mA

9.2 V

3.8 V

Oscillator and Inhib it

OSC

MAX

∆V

OSC

Main Oscillator Accuracy

Disable Thresholds 0.5 V

Maximum Duty Cycle

PWMx Ramp Amplitude 3 V

OSC = OPEN OSC = OPEN; T

OSC = OPEN; I OSC = OPEN; I

= 0°C to 125°C

= 0µA

ISENx

= 35µA

ISENx

90 100 110 kHz

80 % 40 %

FAULT Voltage at Pin OSC OVP Active 5 V

Reference and DAC

VID

FBR = V VR10 and VR9 DACs; V

Output Voltage Accuracy

FBR = V K8 DAC; V

; FBG = GND

OUT

; FBG = GND

OUT

> 1V

OUT

;

> 1V

;

-0.7 0.7 %

-1 1 %

VID Pull-up Current 25 µA

VR9 and VR10 Mode; Input Low K8 Mode; Input Low

0.4

0.8

V V

VID Input Thresholds

VR9 and VR10 Mode; Input Low K8 Mode; Input Low

0.8 2

V V

9/44

4 Electric al specifications L6701

Table 4. Electrical Characteristics (continued)

= 12V±15%, TJ = 0°C to 70°C unless otherwise specified).

Symbol Parameter Te st condi tions Min. Typ. Max. Unit

Error Amplifier and Remote Buffer

EA DC Gain 80 dB

SR Slew Rate COMP = 10pF to SGND 15 V/µs

RB DC Gain 1 V/V

CMRR

Remote Buffer Common Mode Rejection Ratio

40 dB

Differential Curr ent Sensing and Offset

OCTH

IDROOP

OFFSET

Over Current Threshold 35 µA

Droop Current Deviation

= 0 to 105µA; RD=5.1kΩ

DROOP

-3 3 µA

Offset Current 10 11.5 13 µA

Gate Drivers

RISE_UGA

TEx

UGATEx

RISE_LGA

TEx

LGATEx

HS Rise Time

HS Source Current BOOTx - PHASEx = 10V 1.5 A HS Sink Resistance BOOTx - PHASEx = 12V 2.5 Ω

LS Rise Ti me

LS Source Current VCC = 10V 1.5 A LS Sink Resistance VCC = 12V 1.8 Ω

BOOTx - PHASEx = 10V; C

to PHASEx = 3.3nF

UGATEx

VCC = 10V; C

to PGNDx = 5.6nF

LGATEx

15 ns

20 ns

Protections

OVP Over Voltage Protection

Pre-OVP

Preliminary Over vol tage Protection

VSEN Rising, VR10 and K8 Mode VSEN Rising, VR9 Mode

FBR Rising, VR10 and K8 Mode FBR Rising, VR9 Mode

1.85

2.05

1.8

2.0

1.9

2.1

1.9

2.1

1.95

2.15

2.0

2.2

Hysteresis 300 mV

UVP Under Voltage Protection VSEN Falling; Below VID -475 -400 -325 mV

PGOOD PGOOD Threshold

SSEND/

PGOOD

SSEND / PGOOD Voltage Low

K8 and VR9 Mode; VSEN Falling; Below VID

I = -4mA

-280 -230 -180 mV

0.4

10/44

V V

L6701 5 Typical application circuit and block diagram

5 Typi cal application ci rcuit and block diagram

5.1 Application circuit

Figure 2. Typical application cir cuit

VIN

GNDIN

VCC

LIN

BOOT1

to BOOT1

CIN

VIN

to BOOT2

to BOOT3

ISEN1

BOOT2

ISEN2

BOOT3

ISEN3

CS+

CS-

ISEN

HS1

LS1

HS2

LS2

HS3

LS3

VIN

RPHRPHR

COUT

Vcc_core

LOAD

PGOOD

PGND

SGND

DAC_SEL

OSC/EN/FAULT

VID5

VID4

VID3

VID2

VID1

VID0

REF_IN

REF_OUT

COMP

VSEN

FBR

FBG

UGATE1

PHASE1

LGATE1

UGATE2

PHASE2

LGATE2

UGATE3

L6701

PHASE3

LGATE3

SSEND / PGOOD

L6701 REFERENCE SCHEMATIC

11/44

5 T ypical application circuit and block diagram L6701

Figure 3. Typical Applicat i on Circuit: Fully Differential Curr ent Sense (Pat.Pend.)

VIN

GNDIN

VCC

PGND

SGND

DAC_SEL

OSC/EN/FAULT

VID5

VID4

VID3

VID2

VID1

VID0

REF_IN

REF_OUT

COMP

VSEN

FBR

FBG

LIN

BOOT1

UGATE1

PHASE1

LGATE1

ISEN1

BOOT2

UGATE2

PHASE2

LGATE2

ISEN2

BOOT3

UGATE3

L6701

PHASE3

LGATE3

ISEN3

CS+

CS-

SSEND / PGOOD

to BOOT1

CIN

ISEN

VIN

HS1

LS1

VIN

HS2

LS2

VIN

HS3

LS3

RPHRPHR

to BOOT2

to BOOT3

COUT

Vcc_core

LOAD

PGOOD

L6701 FULLY DIFFERENTIAL REFERENCE SCHEMATIC

12/44

L6701 5 Typical application circuit and block diagram

5.2 Block diagram

Figure 4. Block diagram

BOOT1

UGATE1

VCC

PGND

SGND

OSC / EN / FAULT

VID0 VID1 VID2 VID3 VID4 VID5

DAC_SEL

PGND

SGND

3 PHASE

OSCILLATOR

DIGITAL

SOFT START

MULTIPLE DAC

WITH DYNAMIC

PHASE1

HS1 LS1 HS2 LS2 HS3 LS3

LOGIC PWM

ADAPTIVE ANTI

CROSS CONDUCTION

VCC

OSC/EN/FAULT

DAC_SEL

VID CONTROL

DROOP

AMPLIFIER

LGATE1

VCC

CURRENT SHARING CORRECTION

PWM1 PWM2 PWM3

OVP UVP, PGOOD

ERROR

BOOT2

UGATE2

PHASE2

PGND

CROSS CONDUCTION

PWM1 PWM2 PWM3

L6701

CONTROL LOGIC

AND PROTECTIONS

INFO

CURRENT READING

VCC

LOGIC PWM

ADAPTIVE ANTI

CURRENT SHARING CORRECTION

DROOP

LGATE2

PGND

BOOT3

UGATE3

ADAPTIVE ANTI

CROSS CONDUCTION

OCP1

OCP2

OCP3

REMOTE BUFFER

PHASE3

LOGIC PWM

CURRENT SHARING CORRECTION

PH1

LOW SIDE MOSFET

CURRENT READING

AND OVER CURRENT

SSEND / PGOOD

64k

VCC

PH2

64k

PH3

LGATE3

64k

PGNDVCC

AVG

ISEN1 ISEN2 ISEN3

SSEND / PGOOD

REF_OUT

REF_IN

COMP

CS-

CS+

VSEN

FBR

FBG

13/44

6 VID Tables L6701

6 VID Tables

Table 5. Vo ltage IDentification (VID) for Intel VR10 DAC.

VID4 VID3 VID2 VID1 VID0 VID5

010101 1.6000 110101 1.2000 010110 1.5875 110110 1.1875 010111 1.5750 110111 1.1750 011000 1.5625 111000 1.1625 011001 1.5500 111001 1.1500 011010 1.5375 111010 1.1375 011011 1.5250 111011 1.1250 011100 1.5125 111100 1.1175 011101 1.5000 111101 1.1000 011110 1.4875 111110 OFF 011111 1.4750 111111 OFF 100000 1.4625 000000 1.0875 100001 1.4500 000001 1.0750 100010 1.4375 000010 1.0625 100011 1.4250 000011 1.0500 100100 1.4125 000100 1.0375

Output

Voltage

VID4 VID3 VID2 VID1 VID0 VID5

(1)

Output

Voltage

(1)

100101 1.4000 000101 1.0250 100110 1.3875 000110 1.0125 100111 1.3750 000111 1.0000 101000 1.3625 001000 0.9875 101001 1.3500 001001 0.9750 101010 1.3375 001010 0.9625 101011 1.3250 001011 0.9500 101100 1.3125 001100 0.9375 101101 1.3000 001101 0.9250 101110 1.2875 001110 0.9125 101111 1.2750 001111 0.9000 110000 1.2625 010000 0.8875 110001 1.2500 010001 0.8750 110010 1.2375 010010 0.8625

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