ST L6699 User Manual
Enhanced high voltage resonant controller
3/.
Features
■ Symmetrical duty cycle, variable frequency
control of resonant half bridge
■ Self-adjusting adaptive deadtime
■ High-accuracy oscillator
■ 2-level OCP: frequency-shift and immediate
shutdown
■ Interface with PFC controller
■ Anti-capacitive-mode protection
■ Burst-mode operation at light load
■ Input for brownout protection or power-on/off
sequencing
■ “Safe-start” procedure prevents hard switching
at startup
■ 600 V rail compatible high-side gate driver with
integrated bootstrap diode and high dv/dt
immunity
■ -300/800 mA high-side and low-side gate
drivers with UVLO pull-down
■ SO16N package
L6699
Datasheet − production data
Applications
■ SMPS for LCD TVs, desktop and AIO PCs,
servers, Telecom power
■ AC-DC adapter, open frame SMPS
Table 1. Device summary
Order codes Package Packing
L6699D
SO16N
L6699DTR Tape and reel
Tube
Figure 1. Block diagram
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Contents L6699
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.2 Adaptive deadtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.3 Safe-start procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7 Operation at no load or very light load . . . . . . . . . . . . . . . . . . . . . . . . . 21
8 Current sensing, OCP and OLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9 Capacitive-mode detection function . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10 Line sensing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
11 Latched shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
12 Bootstrap section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
13 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2/38 Doc ID 022835 Rev 1
L6699 List of figures
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Typical system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Multimode operation of the L6699 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Oscillator's internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Oscillator waveforms and their relationship with gate-driving signals. . . . . . . . . . . . . . . . . 14
Figure 7. Adaptive deadtime: principle schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Relevant timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. Detailed view of deadtime during low-to-high transition of half bridge midpoint . . . . . . . . . 16
Figure 10. Comparison startup behavior: traditional controller (left), with L6699 (right) . . . . . . . . . . . 18
Figure 11. Comparison of initial cycles after startup: traditional controller (left), with L6699 (right). . . 19
Figure 12. Soft-start circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. Input impedance vs. frequency curve in an LLC resonant half bridge . . . . . . . . . . . . . . . . 20
Figure 14. Narrow input voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15. Wide input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 16. Load-dependent operating modes: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 17. How the L6699 can switch off a PFC controller at light load . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 18. Current sensing techniques with sense resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 19. Current sensing techniques “lossless”, with capacitive shunt. . . . . . . . . . . . . . . . . . . . . . . 24
Figure 20. Soft-start and delayed shutdown upon overcurrent timing diagram
(safe-start details are not shown) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 21. Details of hard-switching transition during capacitive-mode operation. . . . . . . . . . . . . . . . 28
Figure 22. Line sensing function: internal block diagram and timing diagram . . . . . . . . . . . . . . . . . . . 31
Figure 23. Bootstrap supply: standard circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 24. Bootstrap supply: internal bootstrap synchronous diode . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 25. SO16N dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 26. Package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 27. Recommended footprint (dimensions are in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Doc ID 022835 Rev 1 3/38
Description L6699
1 Description
The L6699 is a double-ended controller specific to series-resonant half bridge topology.
Both LLC and LCC configurations are supported. It provides symmetrical complementary
duty cycle: the high-side switch and the low-side switch are driven ON/OFF 180° out-of-
phase for exactly the same time. Output voltage regulation is obtained by modulating the
operating frequency. The deadtime inserted between the turn-off of one switch and the turn-
on of the other one is automatically adjusted to best fit the transition times of the half bridge
midpoint. To drive the high-side switch with the bootstrap approach, the IC incorporates a
high voltage floating structure able to withstand more than 600 V with a synchronous-driven
high voltage DMOS that replaces the external fast-recovery bootstrap diode.
The IC enables the user to set the operating frequency range of the converter by means of a
high-accuracy externally programmable oscillator.
At startup, in addition to the traditional frequency-shift soft-start (the switching frequency
starts from a preset maximum value and then decays as far as the steady-state value
determined by the control loop), a proprietary circuit controls the half bridge to prevent hard-
switching from occurring in the initial cycles because of the unbalance in the V·s applied to
the transformer.
At light load the IC can be forced to enter a controlled burst-mode operation that keeps the
converter input consumption as low as possible.
IC protection functions include a current sense input for OCP with frequency shift and
delayed shutdown with automatic restart. Fast shutdown with automatic restart occurs if this
first-level protection cannot control the primary current. Additionally, the IC prevents the
converter from working in or too close to the capacitive mode, to guarantee soft-switching. A
latched disable input (DIS) can be used to implement OTP and/or OVP. The combination of
these protection features offers the highest degree of safety.
Other functions include a not-latched active-low disable input with current hysteresis, useful
for power sequencing or for brownout protection, and an interface with the PFC controller
that enables the switching-off of the pre-regulator during fault conditions or during burst-
mode operation.
4/38 Doc ID 022835 Rev 1
L6699 Electrical ratings
2 Electrical ratings
Table 2. Absolute maximum ratings
Symbol Pin Parameter Value Unit
V
BOOT
V
OUT
dV
OUT
V
CC
V
PFC_STOP
I
PFC_STOP
V
LINEmax
I
RFmin
V
ISEN
/dt 14 Floating ground max. slew rate 50 V/ns
16 Floating supply voltage (I
14 Floating ground voltage -3 to V
12 IC supply voltage (Icc ≤ 25 mA) Self-limited V
9 Maximum voltage (pin open) -0.3 to V
9 Maximum sink current (pin low) Self-limited A
7 Maximum pin voltage (Ipin ≤ 1 mA) Self-limited V
4 Maximum source current 2 mA
6 Current sense voltage -3 to 5 V
--- 1 to 5, 8 Analog inputs & outputs voltage -0.3 to 5 V
T
j
T
stg
--- Junction temperature operating range -40 to 150 °C
--- Storage temperature -55 to 150 °C
3 Thermal data
Table 3. Thermal data
≤ 5µA) -1 to 618 V
leak
BOOT
CC
V
V
Symbol Parameter Value Unit
R
th j-amb
P
tot
Max. thermal resistance, junction-to-ambient (SO16N) 120 °C/W
Power dissipation @tamb = 50 °C (SO16N) 0.83 W
Doc ID 022835 Rev 1 5/38
Pin connections L6699
4 Pin connections
Figure 2. Pin connections (top view)
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Table 4. Pin functions
N. Name Function
Soft-start. This pin connects an external capacitor to GND and a resistor to
(pin 4) that set both the initial oscillator frequency and the time constant
RF
min
for the frequency shift that occurs as the chip starts up (soft-start). An internal
1
2DELAY
C
SS
switch discharges this capacitor every time the chip turns off (VCC < UVLO,
LINE < 1.25 V, DIS > 1.85 V, ISEN > 1.5 V, DELAY > 2 V) to make sure it is softstarted next. Additionally the switch is activated when the voltage on the current
sense pin (ISEN) exceeds 0.8 V or when the converter is working too close to,
or in, the capacitive-mode operation.
Delayed shutdown upon overcurrent. A capacitor and a resistor are connected
from this pin to GND to set both the maximum duration of an overcurrent
condition before the IC stops switching and the delay after which the IC restarts
switching. Every time the voltage on the ISEN pin exceeds 0.8 V the capacitor
is charged by 350 µA current pulses and is slowly discharged by the external
resistor. If the voltage on the DELAY pin reaches 2 V, the soft-start capacitor is
completely discharged so that the switching frequency is pushed to its
maximum value and the 350 µA current source is kept always on. As the
voltage on the DELAY pin exceeds 3.5 V the IC stops switching and the internal
generator is turned off, so that the voltage on the pin decays because of the
external resistor. The IC is soft-restarted as the voltage drops below 0.3 V. In
this way, under short-circuit conditions, the converter works intermittently with
very low input average power.
If the voltage on the ISEN pin exceeds 1.5 V, the L6699 is immediately stopped
and the 350 µA current source is kept on until the voltage on the DELAY pin
reaches 3.5 V. Then, the generator is turned off and the voltage on the pin
decays because of the external resistor. Also in this case the IC is soft-restarted
as the voltage drops below 0.3 V.
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Timing capacitor. A capacitor connected from this pin to GND is charged and
3CF
6/38 Doc ID 022835 Rev 1
discharged by internal current generators programmed by the external network
connected to pin 4 (RF
converter.
) and determines the switching frequency of the
min
L6699 Pin connections
Table 4. Pin functions (continued)
N. Name Function
Minimum oscillator frequency setting. This pin provides an accurate 2 V
reference, and a resistor connected from this pin to GND defines a current that
is used to set the minimum oscillator frequency. To close the feedback loop that
regulates the converter output voltage by modulating the oscillator frequency,
4RF
min
5STBY
6 ISEN
the phototransistor of an optocoupler is connected to this pin through a resistor.
The value of this resistor sets the maximum operating frequency. Initial
operating frequency should be set below 300 kHz; it is recommended not to
exceed such limit. An R-C series connected from this pin to GND sets
frequency shift at startup to prevent excessive energy inrush (soft-start).
Burst-mode operation threshold. The pin senses some voltage related to the
feedback control, which is compared to an internal reference (1.26 V). If the
voltage on the pin is lower than the reference, the IC enters an idle state and its
quiescent current is reduced. The chip restarts switching as the voltage
exceeds the reference by 30 mV. Soft-start is not invoked. This function realizes
burst-mode operation when the load falls below a level that can be programmed
by properly choosing the resistor connecting the optocoupler to the RF
Figure 1: Block diagram
(see
). Tie the pin to RF
if burst-mode is not used.
min
min
pin
Current sense input. The pin senses the instantaneous primary current though
a sense resistor or a capacitive divider for lossless sensing. If the voltage
exceeds a 0.8 V threshold the soft-start capacitor connected to pin 1 is
internally discharged: the frequency increases and so limits the power
throughput. Under output short-circuit, this normally results in a nearly constant
peak primary current. This condition is allowed for a maximum time set at pin 2.
If the current keeps on building up despite this frequency increase, a second
comparator referenced to 1.5 V disables switching immediately and activates a
restart delay procedure (see DELAY pin description for more information).
This pin is used also for capacitive-mode operation detection and for hardswitching prevention at startup. Do not short the pin to ground; this would
prevent the device from operating correctly.
Line sensing input. The pin is to be connected to the high voltage input bus with
a resistor divider to perform either AC or DC (in systems with PFC) brownout
protection. A voltage below 1.25 V shuts down the IC, lowers its consumption
and discharges the soft-start capacitor. IC operation is enabled as the voltage
7LINE
exceeds 1.25 V. The comparator is provided with current hysteresis: an internal
13 µA current generator is ON as long as the voltage applied at the pin is below
1.25 V, and is OFF if this value is exceeded. Bypass the pin with a capacitor to
GND to reduce noise pick-up. The voltage on the pin is top-limited by an
internal Zener. Tie the pin to V
Latched device shutdown. Internally, the pin connects a comparator that, when
the voltage on the pin exceeds 1.85 V, shuts the IC down and brings its
8DIS
consumption almost to a “before startup” level. The information is latched and it
is necessary to recycle the supply voltage of the IC to enable it to restart: the
latch is removed as the voltage on the V
Tie the pin to GND if the function is not used.
Open-drain ON/OFF control of PFC controller. This pin, normally open, is
intended for stopping the PFC controller, for protection purposes or during
burst-mode operation. It goes low when the IC is shut down by DIS > 1.85 V,
9PFC_STOP
ISEN > 1.5 V and STBY < 1.25 V. The pin is pulled low also when capacitive
mode operation is detected and when the voltage on the DELAY pin exceeds 2
V. In this latter case it goes back open as the voltage falls below 0.3 V. During
UVLO, it is open. Leave the pin unconnected if not used.
with a =100 kΩ resistor if not used.
CC
pin goes below the UVLO threshold.
CC
Doc ID 022835 Rev 1 7/38
Pin connections L6699
Table 4. Pin functions (continued)
N. Name Function
Chip ground. Current return for both the low-side gate-drive current and the
10 GND
11 LVG
12 V
CC
13 N.C.
14 OUT
15 HVG
16 V
BOOT
bias current of the IC. All of the ground connections of the bias components
should be tied to a track going to this pin and kept separate from any pulsed
current return.
Low-side gate-drive output. The driver is capable of 0.3 A min. source and 0.8 A
min. sink peak current to drive the lower MOSFET of the half bridge leg. The pin
is actively pulled to GND during UVLO.
Supply voltage of both the signal part of the IC and the low-side gate driver.
Sometimes a small bypass capacitor (0.1 µF typ.) to GND may be useful to
obtain a clean bias voltage for the signal part of the IC.
High voltage spacer. The pin is not internally connected to isolate the high
voltage pin and ease compliance with safety regulations (creepage distance) on
the PCB.
High-side gate-drive floating ground. Current return for the high-side gate-drive
current. Lay out the connection of this pin carefully to avoid too large spikes
below ground.
High-side floating gate-drive output. The driver is capable of 0.3 A min. source
and 0.8 A min. sink peak current to drive the upper MOSFET of the half bridge
leg. A resistor internally connected to pin 14 (OUT) ensures that the pin is not
floating during UVLO.
High-side gate-drive floating supply voltage. The bootstrap capacitor connected
between this pin and pin 14 (OUT) is fed by an internal synchronous bootstrap
diode driven in-phase with the low-side gate-drive. This patented structure
replaces the normally used external diode.
Figure 3. Typical system block diagram
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8/38 Doc ID 022835 Rev 1
L6699 Electrical data
5 Electrical data
Tj = -25 to +125 °C, VCC = 15 V, V
= 12 KΩ; unless otherwise specified.
RF
min
BOOT
= 15 V, C
HVG
= C
= 1 nF; CF = 470 pF;
LVG
Table 5. Electrical characteristics
Symbol Parameter Test condition Min. Typ. Max. Unit
Ic supply voltage
V
CC
V
CCOn
V
CCOff
Hys Hysteresis 2.55 V
V
Supply current
I
start-up
I
q
I
op
I
q
High-side floating gate-drive supply
R
DS(on)
Operating range After device turn-on 8.85 16 V
Turn-on threshold Voltage rising 10 10.7 11.4 V
Turn-off threshold Voltage falling 7.45 8.15 8.85 V
VCC clamp voltage Iclamp = 15 mA 16 17 17.9 V
Z
Startup current
Quiescent current Device on, V
Operating current Device on, V
Residual consumption
Synchronous bootstrap diode
ON-resistance
Before device turn-on
VCC = V
>1.92 V or V
V
DIS
<1.2 V
V
LINE
= high 150
V
LVG
CCOn
- 0.2 V
= 1 V 1 1.3 mA
STBY
= V
STBY
DELAY
RFmin
>3.65 V or
250 300 µA
34.1mA
400 500 µA
Overcurrent comparator
I
ISEN
V
ISENx
V
ISENdis
Input bias current V
Frequency shift threshold Voltage rising
Immediate stop threshold Voltage rising
Line sensing
V
V
LINE
I
Hys
clamp
Threshold voltage Voltage rising or falling
Current hysteresis V
Clamp level I
Latched disable function
V
I
DIS
DIS
Input bias current V
Disable threshold Voltage rising
Oscillator
f
osc
Oscillation frequency
= 0 to V
ISEN
= 1.2 V 101316µA
LINE
= 1 mA 6 V
LINE
= 0 to 1.92 V -1 µA
DIS
ISENdis
(1)
(1)
(1)
(1)
0.76 0.80 0.84 V
1.43 1.5 1.55 V
1.18 1.22 1.26 V
1.78 1.85 1.92 V
-1 µA
58.2 60 61.8
kHz
R
= 2.7 kΩ 225 235 245
RFmin
Doc ID 022835 Rev 1 9/38
Electrical data L6699
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
T
V
V
V
RF
D
CFp
CFv
REF
K
Deadtime self-adjustment
(2)
range
Peak value 3.9 V
Valley value 0.9 V
Voltage reference on pin 4
Current mirroring ratio 1 A/A
M
Timing resistor range 1 100 kΩ
min
Minimum value 0.23
Maximum
(1)
I
REF
value 0.7
= -2 mA
(1)
1.93 2 2.07
1.8 2 2.07
Zero-current comparator
V
ZCD neg
V
ZCD pos
Threshold voltage (-) -10 mV
Threshold voltage (+) +10 mV
Pfc_stop function
I
leak
R
PFC_STOP
High level leakage current V
ON-state resistance I
PFC_STOP
PFC_STOP
= VCC, V
= 1 mA, V
= 0 V 1 µA
DIS
> 1.92 V 130 200 Ω
DIS
Soft-start function
I
leak
Open-state current V(CSS) = 2 V 0.5 µA
R Discharge resistance 120 Ω
V
T
DISCH
CSS discharge duration
> V
ISEN
capacitive-mode
or approaching
ISENx
5
Capacitive-mode detected 50
Standby function
µs
V
µs
I
STBY
V
STBY
Input bias current V
Disable threshold Voltage falling
= 0 to 1.3 V -1 µA
STBY
(1)
1.22 1.26 1.3 V
Hys Hysteresis Voltage rising 30 mV
Delayed shutdown function
V
= 1 V 1
I
leak
I
CHARGE
Vth
1
Vth
2
Vth
3
Open-state current
Charge current V
Threshold for forced operation
at max. frequency
Shutdown threshold Voltage rising
Restart threshold Voltage falling
DELAY
= 1 V, after shutdown -0.1 -0.5
V
DELAY
= 2.5 V, V
DELAY
Voltage rising
(1)
(1)
(1)
= 0.85 V 250 350 450 µA
ISEN
1.92 2.0 2.08 V
3.35 3.5 3.65 V
0.27 0.3 0.33 V
Low-side gate driver (voltages referred to GND)
V
V
LVG L
LVG H
Output low voltage I
Output high voltage I
= 200 mA 1.5 V
sink
= 5 mA 12.8 13.3 V
source
10/38 Doc ID 022835 Rev 1
µA
L6699 Electrical data
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
I
sourcepk
I
sinkpk
t
t
Peak source current -0.3 A
Peak sink current 0.8 A
Fall time 30 ns
f
Rise time 60 ns
r
UVLO saturation V
High-side gate driver (voltages referred to out)
V
LVG L
V
LVG H
I
sourcepk
I
sinkpk
t
t
Output low voltage I
Output high voltage I
Peak source current -0.3 A
Peak sink current 0.8 A
Fall time 30 ns
f
Rise time 60 ns
r
HVG-OUT pull-down 22 kΩ
1. Values tracking each other.
Figure 9
2. Refer to adaptive deadtime section,
.
= 0 to V
CC
= 200 mA 1.5 V
sink
= 5 mA 12.8 13.3 V
source
CCOn
, I
= 2 mA 1.1 V
sink
Doc ID 022835 Rev 1 11/38
Application information L6699
6 Application information
The L6699 is an advanced double-ended controller specific to resonant half bridge topology.
In these converters the MOSFETs of the half bridge leg are alternately switched on and off
(180° out-of-phase) for exactly the same time. This is commonly referred to as symmetrical
operation at “50% duty cycle”, although the real duty cycle, i.e. the ratio of the ON-time of
either switch to the switching period, is actually less than 50%. The reason is that there is a
deadtime T
one, where both MOSFETs are off. This deadtime is essential in order for the converter to
work correctly: it enables soft-switching and, then, high-frequency operation with high
efficiency and low EMI emissions.
inserted between the turn-off of either MOSFET and the turn-on of the other
D
A special feature of this IC is that it is able to automatically adjust T
within a range so that it
D
best fits the transition times of the half bridge midpoint (adaptive deadtime). This allows the
user to optimize the design of the resonant tank so that soft-switching can be achieved with
a lower level of reactive energy (i.e. magnetizing current), therefore optimizing efficiency
under a broader load range, from full to light load.
To perform converter output voltage regulation the device is able to operate in different
modes (
Figure 1
), depending on the load conditions:
1. Variable frequency at heavy and medium/light load. A relaxation oscillator (see
Section 6.1: Oscillator
for more details) generates a symmetrical triangular waveform,
which MOSFET switching is locked to. The frequency of this waveform is related to a
current that is modulated by the feedback circuitry. As a result, the tank circuit driven by
the half bridge is stimulated at a frequency dictated by the feedback loop to keep the
output voltage regulated, therefore exploiting its frequency-dependent transfer
characteristics.
2. Burst-mode control with no or very light load. When the load falls below a value, the
converter enters a controlled intermittent operation, where a series of a few switching
cycles at a nearly fixed frequency are spaced out by long idle periods where both
MOSFETs are in the OFF-state. A further load decrease is translated into longer idle
periods and then in a reduction of the average switching frequency. When the converter
is completely unloaded, the average switching frequency can go down even to few
hundred hertz, therefore minimizing magnetizing current losses as well as all
frequency-related losses and making it easier to comply with energy saving
specifications.
Figure 4. Multimode operation of the L6699
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