ST L6668 User Manual

L6668

SMART PRIMARY CONTROLLER

1 General Features

■ MULTIPOWER BCD TECHNOLOGY

■ LOAD-DEPENDENT CURRENT-MODE CON-

TROL: FIXED-FREQUENCY (HEAVY LOAD), FREQUENCY FOLDBACK (LIGHT LOAD), BURST-MODE (NO-LOAD)

■ ON-BOARD HIGH-VOLTAGE START-UP

■ IMPROVED STANDBY FUNCTION

■ LOW QUIESCENT CURRENT (< 2 mA)

■ SLOPE COMPENSATION

■ PULSE-BY-PULSE & HICCUP-MODE OCP

■ INTERFACE WITH PFC CONTROLLER

■ DISABLE FUNCTION (ON/OFF CONTROL)

■ LATCHED DISABLE FOR OVP/OTP FUNC-

TION

■ PROGRAMMABLE SOFT-START

■ 2% PRECISION REFERENCE VOLTAGE EX-

TERNALLY AVAILABLE

■ ±800 mA TOTEM POLE GATE DRIVER WITH

INTERNAL CLAMP AND UVLO PULL-DOWN

■ BLUE ANGEL, ENERGY STAR, EU CODE OF

CONDUCT COMPLIANT

Figure 2. Block Diagram

S-COMP V

RCT

DIS

N.C.

ISEN

PFC_STOP

S-COMP V

SLOPE

SLOPE COMP.

COMP.

TIMING

2.2V

HICCUP

1.5V

DIS

DIS OCP

OCP

CLK

2.2/2.7V

BLANKING

and UVLO management

PWM

OCP

0.8V 4R

SKIPADJ

gure 1. Package

SO-16 (Narrow)

Table 1. Order Codes

Part Number Package

L6668 SO-16

L6668TR SO-16 in Tape & Reel

■ SO16 PACKAGE ECOPACK

1.1 APPLICATIONS

■ HI-END AC-DC ADAPTERS/CHARGERS FOR

NOTEBOOKS.

■ LCD/CRT MONITORS, LCD/CRT TV

■ DIGITAL CONSUMER

515

VREG

0.4mA

VREG

COMPSS

Vref

STANDBY

15V

HV generator ON/OFF

Vcc_OK

HYST. CTRL

11R

25V

Vcc_OK

DIS

SOFT-START

11 10

VREF

OUT

GND

ST-BY

January 2006

Rev. 4

1/23

L6668

2 Description

L6668 is a current-mode primary controller IC, designed to build single-ended converters.

The IC drives the system at fixed frequency at heavy load and an improved Standby function causes a smooth frequency reduction as the load is progressively reduced. At very light load the device enters a special operating mode (burst-mode with fixed, externally programmed peak current) that, in addition to the on-board high-voltage start-up and the very low quiescent current, helps keep low the consumption from the mains and be compliant with energy saving regulations. To allow meeting compliance with these standards in power-factor-corrected systems too, an interface with the PFC controller is provided that enables to turn off the pre-regulator when the load level falls below a threshold.

The IC includes also a programmable soft-start, slope compensation for stable operation at duty cycles greater then 50%, a disable function, a leading edge blanking on current sense to improve noise immunity, latched disable for OVP or OTP shutdown and an effective two-level OCP able to protect the system even in case the secondary diode fails short.

Table 2. Absolute Maximum Ratings

Symbol Pin Parameter Value Unit

--- Analog Inputs & Outputs, except pin 14 -0.3 to 8 V

PFC_STOP

tot

stg

Note: 1. ESD immunity for pin 1 is guaranteed up to 900V (Human Body Model).

5 IC Supply voltage (Icc = 20 mA) Self-limited V

1 High-voltage start-up generator voltage range -0.3 to 700 V

1 High-voltage start-up generator current Self-limited A

14 Max. sink current (low state) 2 mA

14 Max. voltage (open state) 16 V

Power Dissipation @Tamb = 50°C 0.75 W

Junction Temperature Operating range -25 to 150 °C

Storage Temperature -55 to 150 °C

Table 3. Thermal Data

Symbol Parameter Value Unit

th j-amb

Thermal Resistance Junction to AmbientMax 120 °C/W

Figure 3. Pin Connection (Top view)

2/23

HVS

GND

OUT

Vcc

N.C.

DIS

VREF

RCT

S-COMP

PFC_STOP

STBY

ISEN

COMP

SKIPADJ

Table 4. Pin Description

L6668

Number

1 HV High-voltage start-up. The pin is to be connected directly to the rectified mains voltage. A

2 HVS High-voltage spacer. The pin is not connected internally to isolate the high-voltage pin and

3 GND Chip ground. Current return for both the gate-drive current and the bias current of the IC. All

4 OUT Gate-drive output. The driver is capable of 0.8A min. source/sink peak current to drive

5 Vcc Supply Voltage of both the signal part of the IC and the gate driver. The internal high volt-

6 N.C. Connect the pin to GND.

7 DIS Latched device shutdown. Internally the pin connects a comparator that, when the voltage

8 VREF Voltage reference. An internal generator furnishes an accurate voltage reference (5V±4%,

9 SKIPADJ Burst-mode control threshold. A voltage is applied to this pin, derived from the reference

10 COMP Control input for PWM regulation. The pin is to be driven by the phototransistor (emitter-

11 SS Soft start. An internal 20µA generator charges an external capacitor connected between

12 ISEN Current sense (PWM comparator) input. The voltage on this pin is internally compared with

Pin Name Function

0.8 mA internal current source charges the capacitor connected between pin Vcc and GND to start up the IC. When the voltage on the Vcc pin reaches the start-up threshold the generator is shut down. Normally it is re-enabled when the voltage on the Vcc pin falls below 5V, except under latched shutdown conditions, when it is re-enabled as the Vcc voltage falls

0.5V below the start-up threshold.

comply with safety regulations (creepage distance) on the PCB.

of the ground connections of the bias components should be tied to a track going to this pin and kept separate from any pulsed current return.

MOSFET’s. The voltage delivered to the gate is clamped at about 15V so as to prevent too high values when the IC is supplied with a voltage close to or exceeding 20V.

age generator charges an electrolytic capacitor connected between this pin and GND as long as the voltage on the pin is below the start-up threshold of the IC, after that it is disabled. Sometimes a small bypass capacitor (0.1µF typ.) to GND might be useful to get a clean bias voltage for the signal part of the IC.

on the pin exceeds 2.2V, shuts the IC down and brings its consumption to a value barely higher than before start-up. The information is latched and it is necessary to recycle the input power to restart the IC: the latch is removed as the voltage on the Vcc pin goes below the UVLO threshold. Connect the pin to GND if the function is not used.

all inclusive) that can be used to supply up to 5 mA to an external circuit. A small film capacitor (0.1µF typ.), connected between this pin and GND is recommended to ensure the stability of the generator and to prevent noise from affecting the reference.

voltage VREF via a resistor divider. When the control voltage at pin COMP falls 50 mV below the voltage on this pin the IC is shutdown and the consumption is reduced. The chip is re-enabled as the voltage on pin COMP exceeds the voltage on the pin. The high-voltage start-up generator is not invoked. The function is disabled during the soft-start ramp. The pin must always be biased between 0.8 and 2.5V. A voltage between 0.8 and 1.4V disables the function, if the pin is pulled below 0.8V the IC is shut down.

grounded) of an optocoupler to modulate the voltage by modulating the current sunk from (sourced by) the pin (0.4 mA typ.). It is recommended to place a small filter capacitor between the pin and GND, as close to the IC as possible to reduce switching noise pick up, to set a pole in the output-to-control transfer function. A voltage 50 mV lower than that on pin SKIPADJ shuts down the IC and reduces its current consumption.

the pin and GND generating a voltage ramp across it. This ramp clamps the voltage at pin COMP during start-up, thus the duty cycle of the power switch starts from zero. During the ramp all functions monitoring the voltage at pin COMP are disabled. The SS capacitor is quickly discharged as the chip goes into UVLO.

an internal reference derived from the voltage on pin COMP and when they are equal the gate drive output (previously asserted high by the clock signal generated by the oscillator) is driven low to turn off the power MOSFET. The pin is equipped with 200 ns. min. blanking time for improved noise immunity. A second comparison level located at 1.5V shuts the device down and brings its consumption almost to a “before start-up” level.

3/23

L6668

Table 4. Pin Description (continued)

Number

Pin Name Function

13 STBY Standby function. This pin is a high-impedance one as long as the voltage on pin COMP is

higher than 3V. When the voltage on pin COMP falls below 3V, the voltage on the pin tracks that on pin COMP and is capable of sinking current. A resistor connected from the pin to the oscillator allows programming frequency foldback at light load.

14 PFC_STOP Open-drain ON/OFF control of PFC controller. This pin is intended for driving the base of a

PNP transistor in systems comprising a PFC pre-regulator, to stop the PFC controller at light load by cutting its supply. The pin, normally low, opens if the voltage on COMP is lower than 2.2V and goes back low when the voltage on pin COMP exceeds 2.7V. Whenever the IC is shutdown, either latched (DIS >2.2V, ISEN >1.5V) or not (UVLO, SKIPADJ<0.8), the pin is open as well.

15 S-COMP Voltage ramp for slope compensation. When the gate-drive output is high the pin delivers a

voltage tracking the oscillator ramp (shifted down by one V

); when the gate-drive output

is low the voltage delivered is zero. The pin is to be connected to pin ISEN via a resistor to make slope compensation and allow stable operation at duty cycles close to and greater than 50%.

16 RCT Oscillator pin. A resistor to VREF and a capacitor to GND define the oscillator frequency (at

full load). A resistor connect to STBY modifies the oscillator frequency when the voltage on pin COMP is lower than 3V.

Table 5. Electrical Characteristcs

= 0 to 105°C, Vcc=15V, Co=1nF; RT =13.3k , CT =1nF; unless otherwise specified)

Symbol Parameter Test Condition Min. Typ. Max. Unit

SUPPLY VOLTAGE

Vcc Operating range After turn-on 9.4 22 V

CCOn

CCOff

Turn-on threshold

Turn-off threshold

Hys Hysteresis 4.0 V

Zener Voltage Icc = 20 mA 22 24 28 V

SUPPLY CURRENT

start-up

qdis

Start-up Current Before turn-on,

Quiescent Current After turn-on 2 2.5 mA

Operating Supply Current 4 mA

Shutdown quiescent current

HIGH-VOLTAGE START-UP GENERATOR

HVstart

charge

HV, ON

HV, OFF

CCrestart

Breakdown voltage I

Start voltage I

Vcc charge current VHV > V

ON-state current VHV > V

Leakage current (OFF state) VHV = 400 V 40 µA

HV generator restart voltage 4.4 5 5.6 V

(1)

After turn-on

12.5 13.5 14.5 V

8.0 8.7 9.4 V

150 µA

Vcc=Vcc

DIS

SKIPADJ

0.8 <V

< 100 µA 700 V

< 100 µA 60 80 105 V

Vcc

(1)

After DIS tripping

-0.5

> 2.2, or V

> 1.5 180 µA

ISEN

<0.8 1 1.8 mA

> V

< V

COMP

Hvstart

SKIPADJ

, Vcc > 3V 0.55 0.85 1 mA

, Vcc > 3V 1.6 mA

, Vcc = 0 0.8

1.3 mA

12 13 14 V

4/23

Table 5. Electrical Characteristcs (continued) (T

= 0 to 105°C, Vcc=15V, Co=1nF; RT =13.3k , CT =1nF; unless otherwise specified)

Symbol Parameter Test Condition Min. Typ. Max. Unit

REFERENCE VOLTAGE

REF

Output voltage

Total variation Vcc= 9.4 to 22 V,

Short circuit current V

Sink capability in UVLO Vcc = 6V; Isink = 0.5 mA 0.2 0.5 V

PWM CONTROL

COMP

max

min

Maximum level I

Max. source current V

Dynamic resistance V

Maximum duty cycle V

Minimum duty cycle V

CURRENT SENSE COMPARATOR

ISEN

LEB

d(H-L)

Input Bias Current V

Leading Edge Blanking After gate drive low-to-high

Delay to Output 100 ns

Gain 3.56 3.75 3.94 V/V

ISENx

ISENdis

Maximum signal V

Hiccup-mode OCP level

STANDBY FUNCTION

drop

- V

COMP

STBY

Threshold on V

COMP

Hysteresis 50 mV

LATCHED DISABLE FUNCTION

DIS

Input Bias Current V

Vth Disable threshold

OSCILLATOR

fsw Oscillation Frequency Tj = 25°C, V

Vpk Oscillator peak voltage

Vvy Oscillator valley voltage

SLOPE COMPENSATION

S-COMP

Ramp peak R

Ramp starting value R

Ramp voltage OUT pin low 0

Source capability V

SOFT-START

SSC

Charge current Tj = 25 °C 14 20 26 µA

(2)

Tj = 25 °C; I

REF

= 1 mA

4.925 5 5.075 V

4.8 5.13 V

= 1 to 5 mA

REF

= 0 10 30 mA

REF

=0 5.5 V

COMP

= 1 V 320 400 480 µA

COMP

= 2 to 4 V 22 kΩ

COMP

= 5 V 70 75 %

COMP

= 1 V 0 %

COMP

= 0 -1 µA

ISEN

160 225 290 ns

transition

= 5 V 0.725 0.8 0.875 V

COMP

(2)

= 0.8 mA, V

STBY

(2)

Voltage falling

= 0 to Vth -1 µA

DIS

(2)

voltage rising

COMP

Vcc = 9.4 to 22V, V

(2)

= 3 kΩ to GND,

S-COMP

OUT pin high, V

= 3 kΩ to GND,

S-COMP

<3V 35 mV

COMP

= 5 V 95 100 105 kHz

= 5 V 93 100 107 kHz

COMP

= 5V

COMP

1.35 1.5 1.65 V

2.1 2.2 2.3 V

2.85 3 3.15 V

0.8 0.95 1.1 V

1.6 1.75 1.9 V

0.15 0.35 0.55 V

OUT pin high

S-COMP = VS-COMPpk

0.8 mA

L6668

5/23

L6668

Table 5. Electrical Characteristcs (continued)

= 0 to 105°C, Vcc=15V, Co=1nF; RT =13.3k , CT =1nF; unless otherwise specified)

Symbol Parameter Test Condition Min. Typ. Max. Unit

SSsat

SSclamp

SKIPADJ FUNCTION

bias

SKIP

Hys Hysteresis Below V

OFF

PFC_STOP FUNCTION

leak

Vth Threshold for high level

GATE DRIVER

sourcepk

sinkpk

Oclamp

(1), (2)

Parameters in tracking each other

Low saturation voltage Duty cycle = 0 0.6 V

High saturation voltage 7 V

Input Bias Current V

= 0 to 4.5 V -1 µA

SKIP

Operating range 1.4 2.5 V

SKIP

25 85 mV

Shutdown threshold Voltage falling 0.8 V

High level leakage current V

Low saturation level I

Output Low Voltage I

Output High voltage I

PFC_STOP

COMP

= 200 mA 1.0 V

sink

source

= 1mA, V

falling

rising

< 16V, V

(2)

= 2V 1 µA

COMP

= 4V 0.1 V

COMP

2.1 2.2 2.3 V

2.55 2.7 2.85 V

= 5 mA, Vcc = 12V 9.8 10.3 V

Peak source current -0.8 A

Peak sink current 0.8 A

Current Fall Time 30 ns

Current Rise Time 55 ns

Output clamp voltage I

UVLO saturation Vcc= 0 to Vccon, I

= 5mA; Vcc = 20V 10 12 15 V

source

= 2mA 1.1 V

sink

Figure 4. Typical System Block Diagram

PFC PRE-REGULATOR DC-DC CONVERTER

inac

PWM is turned off in case of PFC's

anomalous operation, for safety

L6561/2

L6563

PFC can be turned off at light

PFC can be turned off at light load to ease compliance with

load to ease compliance with

energy saving regulations.

6/23

L6668

outdc

3 Typical Electrical Performance

L6668

Figure 5. High-voltage generator ON-state sink current vs. Tj

(pin 1)

1.2

[mA]

0.8

VHV = 100 V

0.6

0.4

0.2

-50 0 50 100 150

Vcc≥3V

Vcc = 0

Tj (°C)

Figure 6. High-voltage generator output (Vcc charge current) vs. Tj

Icc (pin 5)

120%

VHV = 100 V

110%

Figure 8. High-voltage generator start voltage vs. Tj

120%

110%

100%

90%

Values normalized to VHV@ 25°C

80%

-50 0 50 100 150

Tj (°C)

Figure 9. High-voltage generator Vcc restart voltage vs. Tj

Vcc (pin 5)

[V]

while

latched off

100%

90%

Values normalized to Icc @ 25°C

80%

-50 0 50 100 150

Tj (°C)

Figure 7. High-voltage pin leakage vs. Tj

(pin 1)

[µA]

VHV = 400 V

Vcc = 15V

-50 0 50 100 150

Tj (°C)

VHV = 100 V

-50 0 50 100 150

normal

operation

Tj (°C)

Figure 10. IC consumption vs. Tj

Icc (pin 5)

[mA]

Vcc = 15 V

Co = 1 nF

0.5

0.3

0.2

0.1

f = 100 kHz

Latched off

Before start-up (Vcc=12V)

-50 0 50 100 150

during burst-mode

Tj (°C)

Operating

Quiescent

Disa bled or

7/23

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