ST L6615 User Manual

L6615

HIGH/LOW SIDE LOAD SHARE CONTROLLER

■ SSI SPECS COMPLIANT

■ HIGH/LOW SIDE CURRENT SENSING

■ FULLY COMPAT IBL E W ITH REMOTE

OUTPUT VOL TAGE SENSING

■ FULL DIFFERENTIAL LOW OFFSET

CURRENT SENSE

■ 2.7V TO 22V V

■ 32kΩ SHARE SENSE AMPLIFI ER INP U T

OPERATING RANGE

CC

IMPEDANCE

■ HYSTERETIC U VL O

APPLICATION

■ DISTRIBU TED PO WE R SYSTEMS

■ HIGH DENSITY DC-DC CONVERTERS

■ (N+1) REDUNDANT SYSTEMS, N UP TO 20

■ SMPS FOR (WEB) SERVERS

DESCRIPTION

This controller IC is specifically designed to

TYPICAL APPLICATION DIAGRAM

R

SENSE

+OUT

+OUT_S

-OUT_S

-OUT

PS #1

+OUT

+OUT_S

-OUT_S

-OUT

PS #N

SENSE

R

G1RG2

R

SENSE

R

G1

(*)

R

ADJ

1

GND

VCC

CS-

2

CGA

CS+

3

SHARE

ADJ

4

COMP

L6615

(*)

R

ADJ

R

G2

1

GND

VCC

CS-

2

CGA

CS+

3

SHARE

ADJ

4

COMP

L6615

BCD TECHNOLOGY

DIP8 SO8

ORDERING NUM BERS :

L6615N L6615D

L6615DTR(T & Reel)

achieve load sharing of paralleled and independent power supply m odules in distributed power systems, by adding only few external components. Current sharing is achieved through a single wire connection (share bus) common to all of the paralleled modules.

8

8 7

7

6

6 5

5

C

R

CGA

R

C

+OUT

LOAD

GND

SHARE BU S

8

8 7

7

7 6

6

6 5

5

C

R

CGA

C

CGA

(*) OR-ing FET can

(*) OR-ing FET can be used to reduce

be used to reduce power dissipation

power dissipation

July 2003

1/20

L6615

DESCRIPTION (continued)

Load sharing is a technique used in all the systems in which the load requires low vol tage, high current and/or redundancy; for this reason a modular power syst em is necessary in which t wo or more power supplies or DC-DC converters are paralleled.

The device is able to perform both high side and low side current sensing, that is the sense current resistor can be placed either in series to the power supplies output or on the ground return.

The L6615 then drives the share bus to a voltage proportional to the output current of the master that is to the highest amongst the output currents delivered by the paralleled power supplies.

The share bus dynamics is independent of the power supply output voltage and is clamped only by the device supply voltage (V

The output voltage of the other paralleled power supplies (slaves) is then trimmed by the ADJ pin so that they can support their amount of load current. The slave power supplies work as current-controlled current sources.

Sharing the output currents is useful for equalizing also the thermal stress of the different modules and providing an advantage in term of reliability.

Moreover the paralleled supplies architecture allows achieving redundancy; the failure of one of the modules can be tolerated until the capability of the remaining power supplies is enough to provide the required load current.

PIN DESCRIPTION

N° Pin Function

1 GND Ground.

CC

).

2 CS- Input of current sense amplifier; it is connected to the negative side of the sense resistor through

a resistor (R

3 CS+ Input of current sense amplifier. A resistor (RG1, of the same value as RG2) is placed between

this pin and the positive side of the sense resistor: its value defines the transconductance gain between I

4 ADJ Output of Adjust amplifier; it is connected to both the load (through a resistor R

positive remote sense pin of the power system. This pin is an open collector diverting (from the feedback path) a current proportional to the difference between the current supplied to the load by the relevant power supply and the current supplied by the master.

5 COMP Output of the current sharing (transconductance) error amplifier and input of ADJ amplifier.

Typically , a compensation network is placed between this pin and ground. The maximum voltage is internally clamped to 1.5V (typ.)

6 SH Share bus pin. During the power supply

share bus. During power supply proportional to the load current.

share

The and GND could be useful to reduce the noise present on the share bus.

7 CGA Current Gain Adjust pin; current sense amplifier output. A resistor connected between this pin

8V

and ground defines the maximum voltage on the share bus and sets the gain of the current sharing system.

Supply voltage of the IC.

CC

).

G2

and V

CGA

bus connects the SH pins of all the paralleled modules. A capacitor between this pin

SENSE

.

) and to the

ADJ

slave

operation, this pin acts as positive input from

master

operation, it drives the share bus to a voltage

2/20

ABSOLUTE MAXIMUM RATINGS

Symbol Pin Parameter Value Unit

L6615

V

CC

ICS+, ICS- Sense pin current 10 mA

VCS-, V

V

(V

All voltages are with re spect to pin 1. C urrents are positive into, negative out of t he specified t erminal. (*) Maximum package power dissipation limits must be observed

, VSH,

CS+

, V

ADJ

CGA

V

COMP

) - (V

CS+

Ptot Total power dissipation @ Tamb = 70°C

Tstg Storage temperature -55 to +150 °C

) Differential input voltage (VCS+ from 0V to 22V) -0.7 to 0.7 V

CS-

Tj Junction temperature range -40 to +125 °C

8 Supply Voltage (*) (ICC<50mA) selflimit V

2, 3, 6, 4, 7 -0.3 to V

5 Error amplifier output -0.3 to 1.5 V

SO8

DIP8

CC

0.45

0.6

PIN CONNECTION

8

VCC

7

VCC CGA

CGA

GND

CS-

1

1 2

2

V

W

6

CS+

ADJ

3

3 4

4

6 5

5

SH

SH COMP

COMP

THERMA L D ATA

Symbol Parameter MINIDIP SO8 Unit

R

th j-amb

Thermal Resistance junction to ambient 90 120 °C/W

3/20

L6615

ELECTRICAL CHARACTERISTCS

(Tj = -40 to 85°C, Vcc=12V, V V

SENSE

= IL * R

, RG1 = RG2 = 200Ω)

SENS E

Symbol Parameter Test Condition Min. Typ. Max. Unit

Vcc

V

CC, ON

V

CC,OFF

V Vz I

Operating range 2.7 22 V

cc

Quiescent current VSH= 1V, V

I

cc

Turn-on voltage VSH= 0.2V, V Turn-off voltage 2.35 2.5 2.65 V Hysteresis 100 mV

H

CURRENT SENSE AMPLIFIER

V V I

CGAS

I

B(CS-)

I

B(CS+)

CMR Common mode dynamics range V

VTH

SW

Input offset voltage 0.1V ≤ VSH ≤ 10.0V -1.5 0.0 1.5 mV

OS

Out high voltage V

CGA

Short circuit current V Input bias current (high side

sensing) Input bias current (low side

sensing)

Switchover threshold low side to

CS+

high side sensing Switchover hysteresis 0.16 V

H

SHARE DRIVE AMPLIFIER

HV

LV

α

V

SH, load

I SR Slew rate V

SH high output voltage V

SH

SH low output voltage

SH

High side sensing mirror accuracy

(+)

(*) Low side sensing mirror accuracy

(-)

(*) Load regulation -1.0mA ≤ I Short circuit current VSH= 0V, V

SC

= 12V, C

ADJ

= 5nF to GND, R

COMP

= 0V 5 6 mA

SENSE

= 0V 2.45 2.60 2.75 V

SENSE

= 20mA 24 26 V

CC

= 0.25V Vcc-2.2 V

SENSE

= 0V, V

CGA

V

= 0V, V

SENSE

= 0V, V

SENSE

CS-, VCS+ CS+

= 250mV, ISH= -1mA Vcc-2.2 V

SENSE

= 0mV, RSH= 200Ω

CGA

= 0.45V -1.5 -2.0 mA

SENSE

=+12V 1.0 µA

CS+

=0V -1.0 µA

CS+

= 16kΩ, unless otherwise specified;

CGA

0V

CC

1.6 V

45 mV

±1 ±5 %

SDA(OUT)

SENSE

= -10mV to 90mV step,

SENSE

≤ -4mA 20 mV

= 25mV -20 -13.5 -8 mA

0.8 1.5 2.2 V/µs

RSH= 200Ω to GND V

= 90mV to –10mV step,

SENSE

234V/µs

RSH= 200Ω to GND

V

SHARE SENSE AMPLIFIER

R

Input impedance 22.4 32 41.6

i

ERROR AMPLIFIER

G V

4/20

Transconductance 3 4 5 mS

m

Input offset voltage V

os

=1V 30 50 70 mV

CGA

Ω

k

L6615

ELECTRICAL CHARACTERISTCS

(Tj = -40 to 85°C, Vcc=12V, V V

SENSE

= IL * R

, RG1 = RG2 = 200Ω)

SENS E

= 12V, C

ADJ

(continued)

COMP

= 5nF to GND, R

= 16kΩ, unless otherwise specified;

CGA

Symbol Parameter Test Condition Min. Typ. Max. Unit

I

Source current V

OH

Sink current V

OL

COMP

V

SENSE COMP

=1.5V, V

=-10mV

= 1.5V, V

≥ 300mV,

SH

SENSE

=-10mV

-150 -350 -400 µA

100 200 300 µA

200Ω resistor SH to GND

V

COMP(L

V

Low voltage 0.05 0.15 0.25

)

Clamp Zener voltage IZ = 1mA 1.5 V

Z

ADJ AMPLIFIER

I

ADJ

V R

V

ADJ(MIN)

(*) Mirror accuracy is defined as :

Max. ADJ output current VSH= 1V, V Threshold voltage I

T

Emitter resistor Guaranteed by design 60 100 140 Ω

A

Low saturation voltage I

  

----------------------------------------- 1–

 

V

SENSE



=10µA 0.7 V

ADJ

=5mA 1 V

ADJ

I

=1mA 0.4 V

ADJ

V

SH

R

CGA

---------------

⋅

R

G

= 0V 6.5 10 13 mA

SENSE

  

100⋅

  

and it represents the accuracy of the transfer between the voltage sensed and the voltage imposed on the share bus.

BLOCK DIAGRAM

CGA

7

ADJ

4

I

CGA

CS+

CURRENT SENSE

AMPLIFIER (CSA)

+

_

SHARE SENSE

AMPLIFIER (SSA)

R

A

CS-

23

R

40 mV

ADJ OUTPUT

AMPLIFIER (AOA)

R

UVLO

+

_

+

+ _

_

BIAS

R

+

+ _

_

AMPLIFIER (E/A)

0.7V

R

Gm ERROR

24V

R

_

_ +

+

SHARE DRIVE

AMPLIFIER (SDA)

1

GND

1.5V

8

6

5

V

CC

SH

COMP

5/20

L6615

Figure 1. Turn- o n and turn-off voltage

V

, V

CC(OFF)

[V]

CC(ON)

3

2.6

2.2

-50 0 50 100

TJ [OC]

Figure 2. Supply current vs. supply voltage

ICC [mA]

100

10

Figure 4. Max CGA current

I

[mA]

CGA(max)

2.8

2.6

2.4

2.2

2

1.8

-50 0 50 100

TJ [

O

C]

Figure 5. High side/low side sensing

switchover thresh old

VTH [V]

1.9

1.7

1

0.1

0.01

0.1 1 10 100

V

[V]

CC

Figure 3. Supply current

ICC [mA]

4.7

4.3

3.9

3.5

3.1

2.7

-50 0 50 100

TJ [

O

C]

1.5

1.3

-50 0 50 100

O

TJ [

C]

Figure 6. Max. share bus voltage at no load

V

[mV]

SH(LOW)

50

45

40

35

30

25

20

15

10

-50 0 50 100

TJ [OC]

6/20