ST L6615 User Manual
1/20
L6615
July 2003
■ SSI SPECS COMPLIANT
■ HIGH/LOW SIDE CURRENT SENSING
■ FULLY COMPAT IBL E W ITH REMOTE
OUTPUT VOL TAGE SENSING
■ FULL DIFFERENTIAL LOW OFFSET
CURRENT SENSE
■ 2.7V TO 22V V
CC
OPERATING RANGE
■ 32kΩ SHARE SENSE AMPLIFI ER INP U T
IMPEDANCE
■ HYSTERETIC U VL O
APPLICATION
■ DISTRIBU TED PO WE R SYSTEMS
■ HIGH DENSITY DC-DC CONVERTERS
■ (N+1) REDUNDANT SYSTEMS, N UP TO 20
■ SMPS FOR (WEB) SERVERS
DESCRIPTION
This controller IC is specifically designed to
achieve load sharing of paralleled and indepen-
dent power supply m odules in distributed power
systems, by adding only few external components.
Current sharing is achieved through a single wire
connection (share bus) common to all of the paral-
leled modules.
DIP8 SO8
ORDERING NUM BERS :
L6615N L6615D
L6615DTR(T & Reel)
HIGH/LOW SIDE LOAD SHARE CONTROLLER
TYPICAL APPLICATION DIAGRAM
CS-
CGA
CS+
VCC
ADJ
SHARE
GND
COMP
3
2
4
1
5
6
7
8
L6615
+OUT
GND
PS #1
C
C
R
C
R
CGA
R
ADJ
R
SENSE
CS-
CGA
CS+
VCC
ADJ
SHARE
GND
COMP
3
2
4
1
5
6
7
8
L6615
+OUT
+OUT_S
-OUT_S
-OUT
PS #N
C
C
R
C
R
CGA
R
ADJ
R
SENSE
+OUT
+OUT_S
-OUT_S
-OUT
R
G1
R
G2
R
G1
R
G2
SHARE BU S
LOAD
(
*
) OR-ing FET can
be used to reduce
power dissipation
(
*
)
(
*
)
CS-
CGA
CS+
VCC
ADJ
SHARE
GND
COMP
3
2
4
1
5
6
7
8
L6615
+OUT
GND
PS #1
C
C
R
C
R
CGA
R
ADJ
R
SENSE
CS-
CGA
CS+
VCC
ADJ
SHARE
GND
COMP
3
2
4
1
5
6
7
8
L6615
+OUT
+OUT_S
-OUT_S
-OUT
PS #N
C
C
R
C
R
CGA
R
ADJ
R
SENSE
+OUT
+OUT_S
-OUT_S
-OUT
R
G1
R
G2
R
G1
R
G2
SHARE BU S
LOAD
CS-
CGA
CS+
VCC
ADJ
SHARE
GND
COMP
3
2
4
1
5
6
7
8
L6615
+OUT
GND
PS #1
C
C
R
C
R
CGA
R
ADJ
R
SENSE
CS-
CGA
CS+
VCC
ADJ
SHARE
GND
COMP
3
2
4
1
5
6
7
8
L6615
+OUT
+OUT_S
-OUT_S
-OUT
PS #N
C
C
R
C
R
CGA
R
ADJ
R
SENSE
+OUT
+OUT_S
-OUT_S
-OUT
R
G1
R
G2
R
G1
R
G2
SHARE BU S
LOAD
(
*
) OR-ing FET can
be used to reduce
power dissipation
(
*
)
(
*
)
BCD TECHNOLOGY
L6615
2/20
DESCRIPTION (continued)
Load sharing is a technique used in all the systems in which the load requires low vol tage, high current
and/or redundancy; for this reason a modular power syst em is necessary in which t wo or more power sup-
plies or DC-DC converters are paralleled.
The device is able to perform both high side and low side current sensing, that is the sense current resistor
can be placed either in series to the power supplies output or on the ground return.
The L6615 then drives the share bus to a voltage proportional to the output current of the master that is
to the highest amongst the output currents delivered by the paralleled power supplies.
The share bus dynamics is independent of the power supply output voltage and is clamped only by the
device supply voltage (V
CC
).
The output voltage of the other paralleled power supplies (slaves) is then trimmed by the ADJ pin so that
they can support their amount of load current. The slave power supplies work as current-controlled current
sources.
Sharing the output currents is useful for equalizing also the thermal stress of the different modules and
providing an advantage in term of reliability.
Moreover the paralleled supplies architecture allows achieving redundancy; the failure of one of the mod-
ules can be tolerated until the capability of the remaining power supplies is enough to provide the required
load current.
PIN DESCRIPTION
N° Pin Function
1 GND Ground.
2 CS- Input of current sense amplifier; it is connected to the negative side of the sense resistor through
a resistor (R
G2
).
3 CS+ Input of current sense amplifier. A resistor (R
G1
, of the same value as R
G2
) is placed between
this pin and the positive side of the sense resistor: its value defines the transconductance gain
between I
CGA
and V
SENSE
.
4 ADJ Output of Adjust amplifier; it is connected to both the load (through a resistor R
ADJ
) and to the
positive remote sense pin of the power system. This pin is an open collector diverting (from the
feedback path) a current proportional to the difference between the current supplied to the load
by the relevant power supply and the current supplied by the master.
5 COMP Output of the current sharing (transconductance) error amplifier and input of ADJ amplifier.
Typically , a compensation network is placed between this pin and ground. The maximum voltage
is internally clamped to 1.5V (typ.)
6 SH Share bus pin. During the power supply
slave
operation, this pin acts as positive input from
share bus. During power supply
master
operation, it drives the share bus to a voltage
proportional to the load current.
The
share
bus connects the SH pins of all the paralleled modules. A capacitor between this pin
and GND could be useful to reduce the noise present on the share bus.
7 CGA Current Gain Adjust pin; current sense amplifier output. A resistor connected between this pin
and ground defines the maximum voltage on the share bus and sets the gain of the current
sharing system.
8V
CC
Supply voltage of the IC.
3/20
L6615
ABSOLUTE MAXIMUM RATINGS
All voltages are with re spect to pin 1. C urrents are positive into, negative out of t he specified t erminal.
(*) Maximum package power dissipation limits must be observed
PIN CONNECTION
THERMA L D ATA
Symbol Pin Parameter Value Unit
V
CC
8 Supply Voltage (*) (I
CC
<50mA) selflimit V
I
CS
+, I
CS
- Sense pin current 10 mA
V
CS
-, V
CS+
, V
SH
,
V
ADJ
, V
CGA
2, 3, 6, 4, 7 -0.3 to V
CC
V
V
COMP
5 Error amplifier output -0.3 to 1.5 V
(V
CS+
) - (V
CS-
) Differential input voltage (V
CS
+ from 0V to 22V) -0.7 to 0.7 V
Ptot Total power dissipation @ Tamb = 70°C
SO8
DIP8
0.45
0.6
W
Tj Junction temperature range -40 to +125 °C
Tstg Storage temperature -55 to +150 °C
Symbol Parameter MINIDIP SO8 Unit
R
th j-amb
Thermal Resistance junction to ambient 90 120 °C/W
1
2
4
3
GND
VCC
CS-
5
6
8
7
CGA
SH
ADJ
COMP
CS+
1
2
4
3
GND
VCC
CS-
5
6
8
7
CGA
SH
ADJ
COMP
CS+
L6615
4/20
ELECTRICAL CHARACTERISTCS
(Tj = -40 to 85°C, Vcc=12V, V
ADJ
= 12V, C
COMP
= 5nF to GND, R
CGA
= 16k
Ω
, unless otherwise specified;
V
SENSE
= I
L
* R
SENS E
, R
G1
= R
G2
= 200
Ω
)
Symbol Parameter Test Condition Min. Typ. Max. Unit
Vcc
V
cc
Operating range 2.7 22 V
I
cc
Quiescent current V
SH
= 1V, V
SENSE
= 0V 5 6 mA
V
CC, ON
Turn-on voltage V
SH
= 0.2V, V
SENSE
= 0V 2.45 2.60 2.75 V
V
CC,OFF
Turn-off voltage 2.35 2.5 2.65 V
V
H
Hysteresis 100 mV
Vz I
CC
= 20mA 24 26 V
CURRENT SENSE AMPLIFIER
V
OS
Input offset voltage 0.1V ≤ V
SH
≤ 10.0V -1.5 0.0 1.5 mV
V
CGA
Out high voltage V
SENSE
= 0.25V V
cc
-2.2 V
I
CGAS
Short circuit current V
CGA
= 0V, V
SENSE
= 0.45V -1.5 -2.0 mA
I
B(CS-)
Input bias current (high side
sensing)
V
SENSE
= 0V, V
CS+
=+12V 1.0 µA
I
B(CS+)
Input bias current (low side
sensing)
V
SENSE
= 0V, V
CS+
=0V -1.0 µA
CMR Common mode dynamics range V
CS-,
V
CS+
0V
CC
V
VTH
CS+
Switchover threshold low side to
high side sensing
V
CS+
1.6 V
SW
H
Switchover hysteresis 0.16 V
SHARE DRIVE AMPLIFIER
HV
SH
SH high output voltage V
SENSE
= 250mV, I
SH
= -1mA V
cc
-2.2 V
LV
SH
SH low output voltage
V
CGA
= 0mV, R
SH
= 200Ω
45 mV
α
(+)
High side sensing mirror accuracy
(*)
±1 ±5 %
α
(-)
Low side sensing mirror accuracy
(*)
±1 ±5 %
V
SH, load
Load regulation -1.0mA ≤ I
SDA(OUT)
≤ -4mA 20 mV
I
SC
Short circuit current V
SH
= 0V, V
SENSE
= 25mV -20 -13.5 -8 mA
SR Slew rate V
SENSE
= -10mV to 90mV step,
R
SH
= 200Ω to GND
0.8 1.5 2.2 V/µs
V
SENSE
= 90mV to –10mV step,
R
SH
= 200Ω to GND
234V/µs
SHARE SENSE AMPLIFIER
R
i
Input impedance 22.4 32 41.6
k
Ω
ERROR AMPLIFIER
G
m
Transconductance 3 4 5 mS
V
os
Input offset voltage V
CGA
=1V 30 50 70 mV
5/20
L6615
(*) Mirror accuracy is defined as :
and it represents the accuracy of the transfer between the voltage sensed and the voltage imposed on the
share bus.
BLOCK DIAGRAM
I
OH
Source current V
COMP
=1.5V, V
SH
≥ 300mV,
V
SENSE
=-10mV
-150 -350 -400 µA
I
OL
Sink current V
COMP
= 1.5V, V
SENSE
=-10mV
200Ω resistor SH to GND
100 200 300 µA
V
COMP(L
)
Low voltage 0.05 0.15 0.25
V
Z
Clamp Zener voltage I
Z
= 1mA 1.5 V
ADJ AMPLIFIER
I
ADJ
Max. ADJ output current V
SH
= 1V, V
SENSE
= 0V 6.5 10 13 mA
V
T
Threshold voltage I
ADJ
=10µA 0.7 V
R
A
Emitter resistor Guaranteed by design 60 100 140 Ω
V
ADJ(MIN)
Low saturation voltage I
ADJ
=5mA 1 V
I
ADJ
=1mA 0.4 V
ELECTRICAL CHARACTERISTCS
(continued)
(Tj = -40 to 85°C, Vcc=12V, V
ADJ
= 12V, C
COMP
= 5nF to GND, R
CGA
= 16k
Ω
, unless otherwise specified;
V
SENSE
= I
L
* R
SENS E
, R
G1
= R
G2
= 200
Ω
)
Symbol Parameter Test Condition Min. Typ. Max. Unit
V
SH
V
SENSE
R
CGA
R
G
---------------
⋅
----------------------------------------- 1–
100⋅
_
ADJ OUTPUT
AMPLIFIER (AOA)
COMP
V
CC
40 mV
SH
+
+
_
CGA
_
+
7
I
CGA
UVLO
BIAS
8
6
CS-
CS+
23
4
ADJ
R
A
0.7V
Gm ERROR
AMPLIFIER (E/A)
1.5V
5
SHARE SENSE
AMPLIFIER (SSA)
SHARE DRIVE
AMPLIFIER (SDA)
+
_
1
GND
_
+
CURRENT SENSE
AMPLIFIER (CSA)
R
R
R
R
R
R
R
R
24V
_
ADJ OUTPUT
AMPLIFIER (AOA)
COMP
V
CC
40 mV
SH
+
+
_
CGA
_
+
7
I
CGA
UVLO
BIAS
8
6
CS-
CS+
23
4
ADJ
R
A
0.7V
Gm ERROR
AMPLIFIER (E/A)
1.5V
5
SHARE SENSE
AMPLIFIER (SSA)
SHARE DRIVE
AMPLIFIER (SDA)
+
_
1
GND
_
+
CURRENT SENSE
AMPLIFIER (CSA)
R
R
R
R
R
R
R
R
24V
L6615
6/20
Figure 1. Turn- o n and turn-off voltage
Figure 2. Supply current vs. supply voltage
Figure 3. Supply current
Figure 4. Max CGA current
Figure 5. High side/low side sensing
switchover thresh old
Figure 6. Max. share bus voltage at no load
V
CC(ON)
, V
CC(OFF)
[V]
2.2
2.6
3
-50 0 50 100
T
J
[
O
C]
I
CC
[mA]
0.01
0.1
1
10
100
0.1 1 10 100
V
CC
[V]
I
CC
[mA]
2.7
3.1
3.5
3.9
4.3
4.7
-50 0 50 100
T
J
[
O
C]
I
CGA(max)
[mA]
1.8
2
2.2
2.4
2.6
2.8
-50 0 50 100
T
J
[
O
C]
V
TH
[V]
1.3
1.5
1.7
1.9
-50 0 50 100
T
J
[
O
C]
V
SH(LOW)
[mV]
10
15
20
25
30
35
40
45
50
-50 0 50 100
T
J
[
O
C]
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