Features
■ PFC section
– transition mode PFC with over-current
protection
– over-voltage protection
– feedback disconnection
– under-voltage lockout
– PFC choke saturation detection
– THD optimizer
■ Half-bridge section
– preheating and ignition phases
independently programmable
– 3 % oscillator precision
– 1.2 µs dead time
L6585DE
Combo IC for PFC and ballast control
SO-20
– programmable and precise end-of-life
protection compliant with all ballast
configurations
– smart hard switching detection
– fast ignition voltage control with choke
saturation detection
– half-bridge over-current control
Figure 1. Block diagram
April 2009 Rev 2 1/33
www.st.com
33
Contents L6585DE
Contents
1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 VCC section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 PFC section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2.1 TM PFC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2.2 Leading edge blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2.3 THD optimizer feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2.4 Over-voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2.5 Disabling the L6585DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2.6 Feedback disconnection protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2.7 PFC over-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 Ballast section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 Half-bridge drivers and integrated bootstrap diode . . . . . . . . . . . . . . . . . 18
6.2 Normal start-up description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 Startup sequence with old or damaged lamps . . . . . . . . . . . . . . . . . . . . . 21
6.4 Old lamp management during run mode . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.5 Rectifying effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6 Over-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.7 Hard switching protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/33
L6585DE Contents
6.8 Choke saturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3/33
Pin settings L6585DE
1 Pin settings
1.1 Connection
Figure 2. Pin connection (top view)
1.2 Functions
Table 1. Pin functions
Pin n. Name Function
1OSC
2RF
3EOI
An external capacitor to ground fixes the half-bridge switching frequency with a
± 3 % precision.
Voltage reference capable of sourcing up to 240 µA. The current sunk from this
pin fixes the switching frequency of the half-bridge for each operating state.
R
A resistor (
combined with the capacitor connected to the pin OSC.
A resistor connected to EOI (R
frequency during preheating combined with R
Connected to ground by a capacitor that, combined with R
ignition time.
Preheating
Ignition and run mode
HBCS threshold triggering.
) connected to ground sets the half-bridge operating frequency
RUN
) sets the maximum half-bridge switching
PRE
: low impedance to set high switching frequency
: high impedance with controlled current sink in case of
RUN
and C
.
OSC
, determines the
PRE
4/33
L6585DE Pin settings
Table 1. Pin functions (continued)
Pin n. Name Function
Pin for setting the preheating time and protection intervention.
Connect an RC parallel network (Rd and Cd) to ground.
Preheating
voltage reaches 4.63 V the generator is disabled and the capacitor discharges
because of R
4Tch
ignition phase starts and the RdCd is pulled to ground.
Ignition and Run mode:
impedance. During a fault (either over-current or EOL) the internal generator
charges the Cd to 4.63 V and then another current generator discharges the
same capacitor. In this way, C
time).
Pin to program the EOL comparator.
5EOLP
It is possible to select both the EOL sensing method (fixed reference or
reference in tracking with CTR) and the window comparator amplitude by
connecting a resistor (R
Input for the window comparator.
6EOL
It can be used to detect lamp ageing for either “lamp to ground” or “block
capacitor to ground” configurations.
This function is blanked during the ignition phase.
Input pin for:
- PFC over-voltage detection: the PFC driver is stopped until the voltage returns
7CTR
in the proper operating range
- Feedback disconnection detection
- Reference for EOL comparator (in case tracking reference)
- The pin can be used also for shutdown
8MULT
Multiplier external input. This pin is connected to the rectified mains voltage via a
voltage divider and provides the sinusoidal reference to the PFC current loop.
Output of the error amplifier. A compensation network is placed between this pin
9COMP
and INV to achieve stability of the PFC voltage control loop and ensure high
power factor and low THD.
10 INV
Inverting input of the error amplifier. Output voltage of the PFC pre-regulator is
fed to the pin through a voltage divider.
Boost inductor demagnetization sensing input for PFC transition-mode
11 ZCD
operation. A negative-going edge triggers PFC MOSFET turn-on.
During startup or when the voltage is not high enough to arm the internal
comparator, the PFC driver is triggered by means of an internal starter.
Input to the PFC PWM comparator. The current flowing through the PFC
MOSFET is sensed through a resistor. The resulting voltage is applied to this pin
and compared with an internal sinusoidal-shaped reference, generated by the
12 PFCCS
multiplier, to determine the PFC MOSFET’ s turnoff.
A second comparison level detects abnormal currents (due to boost inductor
saturation, for example) and, on this occurrence, shuts down the PFC gate.
An internal LEB prevents undesired function triggering.
: the Cd is charged by an internal current generator. When the pin
. Once the voltage drops below 1.5 V, the preheating finishes, the
d
During proper behavior of the IC, this pin is low
sets the fault timing (shorter than preheating
d
) to ground.
EOLP
5/33
Pin settings L6585DE
Table 1. Pin functions (continued)
Pin n. Name Function
13 PFG
14 HBCS
15 GND Ground.
16 LSD
17 VCC
18 OUT
19 HSD
20 BOOT
PFC gate driver output. The totem pole output stage is able to drive power
MOSFETs with a peak current of 300 mA source and 600 mA sink (typ. values).
3-level half-bridge current monitor for current control.
The current flowing through the HB MOSFET is sensed through a resistor. The
resulting voltage is applied to this pin.
First level threshold (1.05 V, active during run mode): in case of threshold
crossing the IC reacts with frequency increase in order to limit the half-bridge
(and lamp) current.
Second level threshold (1.6 V, active during ignition and run mode):
- Ignition
with frequency increase in order to limit the lamp voltage and preventing
operation below resonance.
- Run mode
example, to capacitive mode / cross-conduction) longer than 200 ns the
L6585DE is latched in low consumption mode to avoid damage to the
MOSFETs.
Third level threshold (2.75 V, active during ignition and run mode):
- Ignition
choke saturation), the IC latches to avoid damage to the MOSFETs.
- Run mode
duration equal to around 40 ns) an internal counter is increased. After around
350 (typ.) subsequent hard switching events the IC is latched in low consumption
mode.
Low side driver output: the output stage can deliver 290 mA source and 480 mA
sink (typ. values).
Supply voltage of both the signal part of the IC and the gate driver.
Clamped with a Zener inside.
High-side driver floating reference. This pin must be connected close to the
source of the high side power MOSFET.
High-side driver output: the output stage can deliver 290 mA source and 480 mA
sink (typ. values).
Bootstrapped supply voltage. Bootstrap capacitor must be connected between
this pin and OUT pin.
Patented, integrated circuitry replaces the external bootstrap diode by means of
a high voltage DMOS, synchronously driven with the low side power MOSFET.
: in case of threshold crossing during the frequency shift, the IC reacts
: in case of threshold crossing because of current spikes (due, for
: in case of threshold crossing during frequency shift (e.g. caused by
: in case of threshold crossing by a hard switching event (spike
6/33
L6585DE Electrical data
2 Electrical data
2.1 Maximum ratings
Table 2. Absolute maximum ratings
Symbol Pin Parameter Value Unit
V
BOOT
V
OUT
/dt 18 Floating ground max. slew rate 50 V/ns
dV
OUT
V
CC
20 Floating supply voltage -1 to 618 V
18 Floating ground voltage -3 to V
17 IC supply voltage (ICC = 20 mA)
(1)
Self-limited V
BOOT –
18 V
1, 3, 4,
8, 10, 12Analog input and outputs -0.3 to 5 V
2, 5 -0.3 to 2.7 V
V
V
V
EOL
CTR
HBCS
6 Maximum EOL voltage -0.3 to V
CC
7 Maximum CTR voltage -0.3 to 7 V
14 Maximum half-bridge current sense voltage -5 to 5 V
9, 11 Self-limited
I
RF
I
EOLP
F
OSC(MAX)
P
TOT
1. The device has an internal clamping Zener between GND and the VCC pin. It must not be supplied by a
low impedance voltage source.
2 Current capability 240 μA
5 Current capability 100 μA
Maximum operating frequency 250 kHz
Power dissipation @TA = 70 °C 0.83 W
Note: ESD immunity for pins 18, 19 and 20 is guaranteed up to 900 V (human body model)
V
2.2 Thermal data
Table 3. Thermal data
Symbol Description Value Unit
R
T
thJA
T
STG
Max. thermal resistance junction to ambient 120 °C/W
Junction operating temperature range -40 to 150 °C
J
Storage temperature -55 to 150 °C
7/33
Electrical characteristics L6585DE
3 Electrical characteristics
VCC = 15 V, TA = 25 °C, CL = 1 nF, C
= 470 pF, R
OSC
= 47 kΩ, unless otherwise specified
RUN
Table 4. Electrical characteristics
Symbol Pin Parameter Test condition Min. Typ. Max. Unit
Supply voltage
Vcc V
V
CC(on)
V
CC(OFF)
V
Z
V
V
V
Supply current
I
ST-UP
I
CC
V
V
Iq V
PFC section – multiplier input
I
V
ΔV
ΔV
MULT
MULT
CS
MULT
K
M
MULT Input bias current V
MULT Linear operation range V
MULT Output max. slope
MULT Gain V
PFC section – error amplifier
Operating range After turn-on 11 16 V
CC
Turn-on threshold
CC
Turn-off threshold
CC
(1)
(1)
13.6 14.3 15 V
9.6 10.3 11 V
Icc = 20 mA, TA = 25 °C 16.7 17.1 17.5 V
Zener voltage
CC
Start-up current Before turn-on @ 13 V 250 370 µA
CC
Operating supply current Fpfc = 50 kHz 7 mA
CC
Residual current IC latched 350 µA
CC
Icc = 20 mA, full
temperature range
= 0 V -1 µA
MULT
= 3 V 0 to 3 V
COMP
V
= 0 to 1 V,
MULT
= Upper clamp
V
COMP
MULT
= 1 V, V
= 3 V 0.52 1/V
COMP
16 17.1 18 V
0.75 V/V
V
I
INV
INV
INV
INV Line regulation V
INV Input bias current -1 µA
Voltage feedback input
threshold
CC
Gv INV Voltage gain Open loop
GB INV Gain-bandwidth product
I
COMP
COMP
Source current V
Sink current V
Upper clamp voltage I
V
COMP
V
DIS
COMP
INV
Lower clamp voltage I
Open loop detection
threshold
(2)
COMP
COMP
SOURCE
SINK
CTR > 3.4 V 1.2 V
COMP Static OVP threshold 2.1 2.25 2.4 V
8/33
2.47 2.52 2.57 V
= 10.3 V to 16 V 50 mV
(2)
60 80 dB
1MHz
= 4V, V
= 4V, V
= 2.4 V -2.6 mA
INV
= 2.6 V 4 mA
INV
= 0.5 mA 4.2 V
= 0.5 mA 2.25 V
L6585DE Electrical characteristics
Table 4. Electrical characteristics (continued)
Symbol Pin Parameter Test condition Min. Typ. Max. Unit
CTR pin
DIS CTR
Hysteresis 120 mV
Dynamic PFC over-
Shutdown threshold Falling edge 0.75 V
PFOV CTR
voltage
Hysteresis 140 mV
CTR
Available range as
tracking reference
PFC section – current sense comparator
I
CS
t
LEB
V
CSstop
t
d(H-L)
V
CSclamp
PFCS Input bias current V
PFCS Leading edge blanking
PFCS PFC stop threshold V
PFCS Delay to output 120 ns
PFCS
Current sense reference
clamp
PFC section – zero current detector
V
ZCDH
V
ZCDL
V
ZCDA
V
ZCDT
I
ZCDb
I
ZCDsrc
I
ZCDsnk
ZCD Upper clamp voltage I
ZCD Lower clamp voltage I
ZCD
ZCD
Arming voltage
(positive-going edge)
Triggering voltage
(negative-going edge)
ZCD Input bias current V
ZCD Source current capability -4 mA
ZCD Sink current capability 4 mA
PFC section – gate driver
Rising edge 3.4 V
Lower threshold (falling) 1.7 V
Hysteresis 120 mV
Higher threshold (rising) 3.4 V
Hysteresis 140 mV
= 0 V -1 µA
CS
(2)
CTR
= Upper clamp 1 1.08 1.16 V
V
COMP
= 2.5 mA 5 V
ZCD
= -2.5 mA -0.3 0 0.3 V
ZCD
(2)
(2)
= 1 to 4.5 V 1 µA
ZCD
100 200 300 ns
1.65 1.75 1.85 V
1.4 V
0.7 V
I
= 10 mA 0.2 V
PFG Output high/low
SINK
I
SOURCE
= 10 mA 14.5 V
tf PFG Fall time 40 90 ns
tr PFG Rise time 90 140 ns
I
SINK
I
SOURCE
PFG Peak sink current 475 600 mA
PFG Peak source current 200 300 mA
PFG Pull-down resistor 10 kΩ
9/33
Electrical characteristics L6585DE
Table 4. Electrical characteristics (continued)
Symbol Pin Parameter Test condition Min. Typ. Max. Unit
Half bridge section – timing and oscillator
V
V
I
CH
CHP
CHN
T
T
T
T
Charge current V
CH
Charge threshold
CH
(positive going-edge)
Discharge threshold
CH
(negative going edge)
Leakage current
CH
= 2.2 V 31 µA
TCH
(1)
(1)
1.5 V < V
TCH
< 4.5 V,
4.53 4.63 4.73 V
1.50 V
falling
0.1 µA
During protection:
I
CHsnk
R
TCH
R
EOI
I
EOI
V
EOI
V
REF
I
RF
I
OSCratio
T
T
Discharge current
CH
Internal impedance Run mode 100 200 Ω
CH
EOI Open state current V
EOI EOI impedance During preheating 150 Ω
EOI current generator
EOI
during ignition and run
mode
EOI EOI threshold
RF Reference voltage
RF Max current capability 240 µA
OSC I
OSC/IRF
OSC Rising threshold
OSC Falling threshold
reduced timing
= 3 V
V
TCH
= 2 V 0.15 µA
EOI
Tspike = 200 ns
Tspike = 400 ns
Tspike = 600 ns
Tspike = 1 µs
(1)
(1)
V
= 3 V 4
OSC
(1)
(1)
(3)
(3)
(3)
(3)
1.83 1.9 1.98 V
1.92 2 2.08 V
26 µA
20
100
200
270
3.7 V
0.9 V
D OSC Output duty cycle 48 50 52 %
T
DEAD
F
F
RUN
PRE
OSC Dead time 0.96 1.2 1.44 µs
OSC
OSC
Half-bridge oscillation
frequency (run mode)
Half-bridge oscillation
frequency (preheating)
58.4 60.2 62 KHz
R
= 50 kΩ 113.2 116.7 120.2 KHz
PRE
µA
Half bridge section – end-of-life function
I
EOLP
V
EOLP
EOLP Current capability 100 µA
EOLP Reference voltage 1.92 2 2.08 V
EOL Operating range EOLP = 27 kΩ 0.95 4.15 V
220 kΩ < R
kΩ or 22 kΩ < R
V
S
EOL
Window comparator
reference
27 kΩ
R
EOLP
75 kΩ < R
10/33
< 270
EOLP
EOLP
> 620KΩ or
< 91 kΩ
EOLP
<
tracking with CTR
V
2.5
L6585DE Electrical characteristics
Table 4. Electrical characteristics (continued)
Symbol Pin Parameter Test condition Min. Typ. Max. Unit
V
W
EOL Half window amplitude
EOL Sink/source capability 5.5 µA
Half bridge section – Half-bridge current sense
HBCS
HBCS
HBCS
HBCS
HBCS
t
LEB,HBCS
HBCS
HBCS
H
L
H,test
L,test
AS
CM
HS
HBCS Frequency increase V
HBCS Threshold V
HBCS Shut down threshold
HBCS V
during first low side on
time after Tch cycle
HBCS Anti saturation threshold Ignition 2.75 V
HBCS Leading edge blanking Ignition 270 ns
HBCS
Capacitive mode
threshold
HBCS Hard switching detector
Hysteresis 450 mV
N
HS
Hard switching events
before shutdown
220 kΩ < R
270 kΩ
EOLP
<
+250
-240
+160
22 kΩ < R
> 620 kΩ 720
R
EOLP
75 kΩ < R
< 1.9 V (ignition) 1.53 1.6 1.66 V
EOI
> 1.9 V (run mode) 0.98 1.05 1.12 V
EOI
V
< 1.9 V (ignition) 1.05 V
EOI
> 1.9 V (run mode)0.82 V
EOI
Run mode,
Tpulse > 200 ns
Run mode,
Tpulse > 40 ns
< 27 kΩ
EOLP
< 91 kΩ 240
EOLP
1.53 1.6 1.66 V
-150
2.75 V
mV
Run mode 350
Half bridge section – Low side gate driver
LSD Output low voltage I
LSD Output high voltage I
= 10 mA 0.3 V
SINK
SOURCE
= 10 mA 14.5 V
LSD Peak source current 200 290 mA
LSD Peak sink current 400 480 mA
T
T
RISE
FAL L
LSD Rise time 120 ns
LSD Fall time 80 ns
LSD Pull-down resistor 45 kΩ
Half bridge section – High side gate driver (voltages referred to OUT)
HSD Output low voltage I
HSD Output high voltage I
= 10 mA
SINK
SOURCE
= 10 mA
HSD Peak source current 200 290 mA
HSD Peak sink current 400 480 mA
11/33
V
BOOT
0.5
–
V
OUT
0.3
+
V
V
Electrical characteristics L6585DE
Table 4. Electrical characteristics (continued)
Symbol Pin Parameter Test condition Min. Typ. Max. Unit
T
T
RISE
FAL L
HSD Rise time 120 ns
HSD Fall time 80 ns
HSD HSD-OUT pull-down 50 kΩ
High-side floating gate-drive supply
(2)
(2)
5µA
5µA
BOOT Leakage current V
OUT Leakage current V
Synchronous bootstrap
diode on-resistance
1. Parameter in tracking
2. Specification over the -40 °C to 125 °C junction temperature range are ensured by design, characterization and statistical
correlation
3. A pulse train has been sent to the HBCS pin with f = 6 kHz; the pulse duration is the one indicated in the notes as "TON"
= 600 V
BOOT
= 600 V
OUT
V
= HIGH 250 Ω
LSD
12/33
L6585DE Device description
4 Device description
The L6585DE embeds a high performance PFC controller, a ballast controller and all the
relevant drivers necessary to build an electronic ballast.
The PFC section achieves current mode control operating in transition mode, offering a
highly linear multiplier including a THD optimizer that allows for an extremely low THD, even
over a large range of input voltages and loading conditions.
The PFC output voltage is controlled by means of a voltage-mode error amplifier and a
precise internal voltage reference.
The ballast controller offers the designer a very precise oscillator, a logic that manages all
the operating steps and a full set of protection features:
● Programmable end-of-life detection, compliant with both lamp-to-ground and capacitor-
to-ground configurations
● Over-current protection with either current limiting or choke saturation protection
● Hard switching events detection
High current capability drivers for both the PFC (300 mA source and 600 mA sink) and the
half-bridge (290 mA source and 480 mA sink) also allow ballast designs for very high output
power (up to 160 W).
13/33
Application information L6585DE
5 Application information
Figure 3. Typical application
5.1 VCC section
The L6585DE is supplied by applying voltage between the VCC pin and GND pin. An undervoltage lockout (UVLO) prevents the IC from operating with supply voltages too low to
guarantee the correct behavior of the internal structures.
An internal voltage clamp limits the voltage to around 17 V and can deliver up to 20 mA. For
this reason it cannot be used directly as a clamp for the charge pump (current peaks usually
reach several hundreds of mA), but can be easily used during startup in order to charge the
V
capacitor or during save mode in order to keep the IC alive, for example, connecting
CC
V
to input voltage through a resistor.
CC
In addition to the bulk capacitor (>1 µF)it is suggested to place a 100 nF ceramic capacitor
close to V
CC
pin.
14/33
L6585DE Application information
5.2 PFC section
5.2.1 TM PFC operation
The PFC stage contains all the features needed to implement a transition mode PFC
controller.
Figure 4. PFC section
The control loop can be implemented thanks to the high performance error amplifier and the
very precise internal voltage reference that fixes the non-inverting input of the E/A to 2.52 V
± 2 %.
The control loop reacts in order to bring the inverting input to the same voltage. Connecting
the high voltage rail to INV pin, by means of a voltage divider, the output voltage will be
easily set.
The output of the E/A can be used in order to compensate the control loop with an RC
network or, more often, with a simple capacitor connected between INV and COMP pin.
The output voltage of the E/A is also fed to the multiplier. This block multiplies the waveform
present at the MULT pin by the output of the E/A. The resulting voltage will be used as the
threshold for the current sense input. An internal clamp limits the threshold to a maximum
value equal to 1 V.
In Figure 5 the characteristic curves of the multiplier are reported.
Figure 5. Multiplier
15/33
Application information L6585DE
The ZCD input can be connected directly to an auxiliary winding of the PFC choke in order
to turn on the MOSFET when the choke current reaches zero. This pin has internal clamps
and high current capability that makes it compliant with a very wide range of input voltage.
At startup, when PFC choke is not yet energized, an internal starter gives ZCD pulses to the
PFC gate driver with a repetition rate of approximately 15 kHz.
By turning off the MOSFET when the current reaches the threshold and turning on the
MOSFET when the choke current reaches zero, a triangular input current whose peaks are
modulated by the MULT voltage is obtained. By feeding the MULT pin with the mains
waveform, a power factor correction and THD reduction is achieved.
5.2.2 Leading edge blanking
Usually current sense voltage is filtered by means of an RC network in order to avoid false
turning off of the MOSFET because of the discharge current related to parasitic drain
capacitance present at the beginning of the on time of the MOSFET. This filtering generates
a delay between the actual threshold crossing and the input triggering. During this time the
PFC inductor current increases and the choke may saturate. A leading edge blanking
structure makes the PFCCS input active only after 200 ns (typ.) after the PFG turn on. This
allows the use of inductors with lower saturation current. However, if saturation occurs, a
choke saturation protection turns off the PFC gate as soon as the voltage at pin PFCCS is
above 1.7 V.
Figure 6. PFCCS waveforms
5.2.3 THD optimizer feature
When the input voltage passes through zero, the PFC choke cannot store energy because
of the very low voltage across it. This may cause heavy crossover distortion and subsequent
THD degradation. A small offset voltage superimposed over the MULT voltage can reduce
this issue.
The internal THD optimizer increases the performance when the mains voltage reaches
zero; this reduces crossover distortion and avoids offset introduction.
16/33
L6585DE Application information
5.2.4 Over-voltage protection
Two different over-voltage protections can be detected: dynamic over-voltage, usually due to
fast load transition and static over-voltage, due to an excessive input voltage.
● Dynamic OVP
The CTR pin is connected to high voltage rail through a voltage divider. If the voltage at
this pin is above 3.4 V, the PFC gate driver is stopped until the voltage returns below
the threshold. This limits the risk of choke saturation and MOSFET's damage.
● Static OVP
A steady over-voltage may cause abnormal behavior in both the PFC (e.g. because
input voltage is higher than PFC output voltage) and the ballast (e.g. overheating, lamp
over-current, capacitive mode operating point). A steady over-voltage causes a slow
transition of the COMP pin towards the low saturation (around 2.25 V). This fact is
considered by the L6585DE as a static over-voltage event and a Tch cycle is started.
After this cycle, if the COMP pin is saturated low the IC is latched in low consumption
mode.
5.2.5 Disabling the L6585DE
the CTR pin can be used to shut down the IC without mains disconnection. When CTR is
pulled below 0.75 V, the IC is stopped and the internal logic is reset. When CTR is released,
the IC starts with a new preheating sequence. This function is available only if the IC is not
latched due to a fault protection intervention.
5.2.6 Feedback disconnection protection
Very fast output voltage surges may damage the upper resistors of the voltage divider
feeding the INV pin, causing a feedback disconnection. In this case, the E/A saturates high
and the PFC gate drive turns on the MOSFET for a long time (the current sense threshold
assumes its maximum value equal to 1 V) and the choke may saturate, destroying the
MOSFET.
The output voltage increases very fast and may reach very high value even if OVP is
triggered.
Feedback disconnection protection is then activated if V
voltage protection is triggered.
5.2.7 PFC over-current protection
The PFC MOSFET over-current can occur in cases of PFC choke saturation or in cases of
surge from the input, due to the breakdown of the MOSFET body diode. The latter case is
observed together with an over-voltage of the PFC output.
In both cases, the PFC stage is stopped, whereas the HB stage continues switching. The
protection is not latched: once the PFCCS falls below 1.7 V, the PFC driver restarts.
< 1.2 V and dynamic over-
INV
17/33
Ballast section L6585DE
6 Ballast section
6.1 Half-bridge drivers and integrated bootstrap diode
The half-bridge drivers are capable of 290 mA source and 480 mA sink current. This makes
them able to effectively drive also big MOSFETs Cg up to 2.2 nF. The high-side MOSFET is
driven by means of a bootstrapped structure reducing the number of external components.
6.2 Normal start-up description
Referring to Figure 7, normal startup proceeds as follows:
Figure 7. Normal start-up procedure
1. Startup: As soon as Vcc reaches the startup threshold voltage references are built up,
the RF and EOLP pin are biased, the EOI pin is pulled down and the TCH pin starts
sourcing 31 µA. The frequency of the half-bridge is generated by an internal CCO,
connected to
pulled down, the startup frequency will be due to the current flowing in parallel with
R
and R
PRE
2. Preheating: the TCH pin continues to source 31 µA until its voltage reaches 4.63 V,
therefore it is left in a high impedance status. As this pin loaded with an RC parallel
network, the voltage across this pin decreases exponentially. When it reaches 1.5 V the
TCH pin is pulled down and the preheating time ends. During this sequence the EOI
pin is pulled down and the half-bridge frequency is the startup frequency. A leading
18/33
C
and using the RF current as the control signal. With the EOI pin
OSC
(see typical application diagram).
RUN
L6585DE Ballast section
edge blanking is active during this time in order to avoid any detection of hard switching
events, very common during this phase.
3. Ignition: At the end of the TCH cycle, the EOI pin is left free in high impedance mode.
Therefore, the capacitor connected between EOI and ground is charged by RF through
R
. The current sunk from the RF pin decreases exponentially, and the frequency
PRE
along with it. An exponential decrease in switching frequency causes a linear increase
of the lamp voltage. When the lamp voltage reaches the strike value, the lamp ignites.
Ignition time is set by the value of
R
PRE
and C
IGN
.
During ignition current control protection, anti-ballast choke saturation protection and
leading edge blanking are all active.
Figure 8. Half-bridge protection thresholds during ignition
4. Run mode: When the EOI voltage reaches 1.9 V, the IC enters run mode and the
switching frequency is set only by R
. Current control protection and anti-ballast
RUN
choke saturation are now active with a lower threshold, leading edge blanking is not
active and a fast hard switching detector is activated.
Figure 9. Half-bridge protection thresholds during run mode
19/33
Ballast section L6585DE
The oscillator characteristic curves represent the half bridge frequency versus the
resistance R placed between RF pin and ground. During preheating R is equal to R
parallel with
value of the
The value of
R
whereas during Run mode R is equal to R
PRE
C
capacitor and are depicted in Figure 10.
OSC
C
is measured between pin 1 (OSC) and 15 (GND); for other capacitor
OSC
. Each curve is related to a
RUN
RUN
in
values please refer to AN2870.
The right value of R during preheating and run mode can be found graphically considering
the curve related with the chosen capacitor and respectively
F
PRE
and F
RUN
“
Figure 10. Oscillator characteristics
Some useful equations are given:
TT
TchPRE
20/33
63.4
I
CH
CR3T
⋅⋅≅
IGNPREIGN
ddd
63.4
⎞
⎛
lnCRC
⋅+==
⎟
⎜
5.1
⎠
⎝
L6585DE Ballast section
6.3 Startup sequence with old or damaged lamps
When an old lamp is connected to the ballast the strike voltage is higher than the nominal
voltage and may also be higher than the safety threshold. In this case the lamp can ignite in
a time longer than ignition time or may not ignite. In both cases, during ignition time,
because of the frequency decrease, the voltage at the output of the ballast can easily reach
dangerous values.
The same occurs if the lamp tube is broken: the lamp cannot ignite and the lamp voltage
must be limited.
During ignition time, the L6585DE senses the current flowing into the lamp through a sense
resistor connected to the HBCS pin. If the HBCS pin voltage reaches 1.6 V, a small amount
of current is sunk from the EOI pin causing a small frequency increase. This frequency
modification results, macroscopically, in a frequency regulation and therefore a current
regulation and a lamp voltage limiting.
As soon as the HBCS pin voltage reaches 1.6 V, the TCH pin starts to charge Cd: when the
TCH voltage reaches 4.63 V, the TCH pin is no longer left free (as during preheating), but it
sinks 26 uA, causing a faster discharge of Cd. When the TCH voltage reaches 1.5 V, the pin
is pulled down and HBCS voltage is checked. If it is above 1.05 V the IC is stopped.
If the lamp ignites during this reduced TCH cycle, the EOI pin stops sinking current and if it
reaches 1.9 V, the IC enters run mode and TCH pin is immediately pulled down.
Figure 11. Startup procedures with old or damaged lamps
It can be noted that the reduced TCH cycle time depends only on the value of Cd. It is
suggested to start from the choice of Cd in order to obtain the protection time, and then can
proceed to the choice of Rd to obtain the desired T
⎛
63.4
⎜
CT ⋅⋅≅
dreduced,Tch
⎜
I
⎝
+=
I
−
snk,Tchsource,Tch
PRE
.
⎞
5.163.4
⎟
d
⎟
⎠
6
1026974.0C
21/33
Ballast section L6585DE
6.4 Old lamp management during run mode
During run mode, an old lamp can exhibit three different abnormal behaviors:
● Rectifying effect
● Over-current
● Hard switching event
6.5 Rectifying effect
The rectifying effect is related to a differential increase of the ohmic resistance of the two
cathodes. The lamp equivalent resistance is therefore higher when the lamp current flows in
one direction than in the other. The current waveform is distorted and the mean value of the
lamp current is no longer zero. The EOL pin is the input of an internal window comparator
that can be triggered by a voltage variation due to rectifying effect.
The reference of this comparator and the amplitude of the window can be set by connecting
a suitable resistor to EOLP pin as indicated in following table:
Table 5. EOL window comparator configuration table
EOLP resistor range Reference Window amplitude (Wv)
22 k ÷ 27 k V
75 k ÷ 91 k 2.5 V 240 mV
220 k ÷ 270 k V
> 680 k 2.5 V 720 mV
CTR
CTR
+160 mV / -150 mV
+ 250 mV / -240 mV
The reference of this comparator can be set at a fixed voltage or at the same voltage as the
CTR pin.
The fixed reference configuration (see
Figure 12) can be used when the lamp is connected
to ground, and requires two Zener diodes in order to shift the mean value of the lamp
voltage to 2.5 V. The values of the two Zeners affect the symmetry of the intervention of the
protection: the best symmetry is obtained choosing two values whose difference is equal to
twice the reference voltage:
● V
● V
● V
●
Where VUP and V
UP
DOWN
UP
2 V
= V
REF
= V
= - V
= VZ1 − V
REF
+ V
REF
DOWN
+ VF1 + W/2
Z2
– (VZ1 + VF2) – W/2
Z2
are the maximum allowed values of V
DOWN
K
The tracking configuration (see Figure 13) is useful when the lamp is connected between
choke and blocking capacitor in the block capacitor-to-ground configuration. In this
configuration the voltage across the blocking capacitor is affected by the voltage ripple
superimposed on the PFC output. Using a reference affected by the same ripple helps to
reject it and avoid premature triggering of the comparator.
As soon as the comparator is triggered, a Tch cycle starts in order to improve the noise
immunity.
22/33
L6585DE Ballast section
Figure 12. End-of-life protection in lamp-to-ground configuration
23/33
Ballast section L6585DE
Figure 13. End-of-life protection in blocking capacitor-to-ground configuration
24/33
L6585DE Ballast section
p
p
6.6 Over-current protection
The appearance of over-current and hard switching events are related to a symmetrical
increase of the ohmic resistance of the two cathodes. The overall effect results in an
increased equivalent resistance of the lamp and a subsequent modification of the
resonance curve of the resonance network (see
Figure 14. Resonance curve modification due to lamp ageing
Figure 14).
Old lam
The increasing of the resonant peak causes over-current that is managed by the L6585DE
in the same way as in ignition mode, but the limiting threshold and checking threshold are
respectively 1.05 V and 0.82 V.
6.7 Hard switching protection
When F
purely resistive. In this case, zero voltage switching is no longer present and the MOSFET
experiences high current spikes at turn on. The voltage at HBCS pin shows these peaks
whose voltage value can be greater than 3 V with a duration that depends on how close the
resonant frequency and the operating frequency are. Typical values go from 40 ns to around
200 ns. These spikes may overheat the MOSFETs but, if correctly detected, can prevent the
risk of working below the resonance frequency (capacitive mode).
The L6585DE can detect these spikes by means of a 2.75 V threshold on HBCS pin, and a
counter that shuts down the IC if 350 (typ.) subsequent spikes are detected.
This protection is blanked both during preheating and ignition.
is equal to the peak of the resonance curve, the load seen by the half-bridge is
RUN
frun
New lam
6.8 Choke saturation protection
Ballast choke saturation implies that very high currents flow into resonance network and an
almost instant modification of the resonance curve occurs in a way that the operating point
lies immediately in capacitive mode. Steady operation in capacitive mode heavily damages
the ballast.
25/33
Ballast section L6585DE
Figure 15. Example of capacitive mode operation due to ballast choke saturation
HBCSOUT pin
Good
working
Saturating
slightly
Capacitive
mode
Therefore, in ignition and run mode a comparator, connected to the HBCS pin, is active with
a threshold respectively equal to 2.75 V and 1.6 V. It senses very high currents flowing in the
ballast sense resistor and immediately latches the IC in low consumption mode. The width
of the triggering spike is above 200 ns. This guarantees that, during run mode, hard
switching events (typical duration between 40 ns and 100 ns) cannot trigger the comparator.
However, hard switching protection and anti-saturation protection are not perfectly
independent. Regarding the pulse width we can indicate four different regions:
a) Spikes with a duration less than 40 ns: (noise region) no protection can be
triggered.
b) Spikes with a duration between 40 ns and 100 ns: (HSw region) only hard
switching protection will be activated after around 420 events.
c) Spikes with a duration between 100 ns and 200 ns: (uncertainty region) hard
switching protection is activated, but also anti-saturation protection can be
activated, which may result in a sort of early activation of hard switching protection
or retarded activation of anti-saturation protection (in this case the saturation of the
choke won’t be deep).
d) Spikes with a duration longer than 200 ns: (ASP region) anti-saturation protection
will certainly be activated at the first event.
26/33
L6585DE Ballast section
Figure 16. Half-bridge current sense pulse detection areas
27/33
Ballast section L6585DE
Table 6. Table of faults
Active during
Fault
PH Ign Run
Fault with immediate activation of latched operating mode
Condition IC behavior Required action
- Drivers stopped
Shutdown V
9 9 9
PFC feedback
disconnection
9 9 9
V
V
CTR
CTR
INV
< 0.75 V
> 3.4 V
and
< 1.2 V
- IC low consumption
(Vcc clamped)
- Drivers stopped
- IC low consumption
(Vcc clamped)
Ignition:
Half bridge anti-
saturation
protection
9 9
> 2.75 V
V
HBCS
Run mode:
V
> 1.6 V
HBCS
- Drivers stopped
- IC low consumption
Vcc clamped)
Fault with immediate activation of a non latched operating mode
PFC dynamic
over-voltage
PFC protection
over-current
9 9 9
9 9 9
V
> 3.4 V - PFC driver stopped
CTR
V
> 1.7 V - PFC driver stopped
PFCCS
Fault with timed activation of latched operating mode
- PFC driver stopped
PFC static OVP V
9 9 9
COMP
< 2.25 V
- Tch cycle starts
- At the end of cycle, if V
2.25 V IC is latched
- Tch cycle starts
- At the end of the cycle if V
)
is out of range the IC is latched
Lamp end-of-life
9
outside
V
EOL
allowed range
(set by R
EOLP
- Frequency control activated
and Reduced Tch Cycle (RTC)
starts
- At the end of RTC the
threshold is reduced (1.05 V
during ignition and 0.82 V
during run mode)
- If V
HBCS
Lamp over-current
9 9
Ignition:
> 1.6 V
V
HBCS
Run mode:
> 1.05 V
V
HBCS
is stopped
Lamp ageing
causing hard
switching
> 2.75 V
V
9
HBCS
- After 350 subsequent hard
switching events IC is stopped
COMP
EOL
>reduced threshold IC
> 0.75 V
V
CTR
(IC restarts with PH
sequence)
Board failure
Turn off – turn on
sequence
Wait for output
voltage reduction
Wait for next starter
event
Check the mains
<
voltage
Replace the lamp
with a new one
Replace the lamp
with a new one
Replace the lamp
with a new one
28/33
L6585DE Package mechanical data
7 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
®
packages, depending on their level of environmental compliance. ECOPACK®
29/33
Package mechanical data L6585DE
Table 7. SO-20 mechanical data
mm. inch
Dim.
Min. Typ. Max. Min. Typ. Max.
A 2.65 0.104
a1 0.1 0.2 0.004 0.008
a2 2.45 0.096
b 0.35 0.49 0.014 0.019
b1 0.23 0.32 0.009 0.012
C 0.5 0.020
c1 45° (typ.)
D 12.60 13.00 0.496 0.512
E 10.00 10.65 0.393 0.419
e 1.27 0.050
e3 11.43 0.450
F 7.40 7.60 0.291 0.300
L 0.50 1.27 0.020 0.050
M 0.75 0.029
S 8° (max.)
Figure 17. Package dimensions
30/33
L6585DE Ordering information
8 Ordering information
Table 8. Order codes
Order codes Package Packaging
L6585DE SO-20 Tube
L6585DETR SO-20 Tape and reel
31/33
Revision history L6585DE
9 Revision history
Table 9. Document revision history
Date Revision Changes
27-Nov-2008 1 Initial release
10-Apr-2009 2 Updated Ta b le 1 ,Ta bl e 2 , Tab l e 3 , Figure 4
32/33
L6585DE
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