ST L6585D User Manual

Combo IC for PFC and ballast control

Features

■ Pre-heating and ignition phases independently

programmable

■ Ignition voltage control

■ Transition mode PFC with over-current

protection

■ Programmable and precise End-of-life

protection compliant with all ballast configurations

■ Auto-adjusting half-bridge over-current control

■ Automatic re-lamp

■ 3% oscillator precision

■ 1.2µs dead time

■ PFC over-voltage protection and feedback

disconnection

■ Under voltage lock-out

L6585D

SO-20

Applications

■ Electronic ballast

Figure 1. Block diagram

COMP MULT PFCS Vcc

2.5V

2.5V E/A

INV

ZCD

PFG

CTR

EOLR

1.2V

0.7V

3.4V

0.75V

4.63V

+

+ _

_

Vcc

E/A

STARTER

DIS

RELAMP

MULTIP LIER

OPTIMIZER

OL

PFSTOP

OL

OVP

2V

and THD

S

EOLP

R

Q

COMPARATOR

2V

+

_

PWM

PWM COMP.

COMP.

WINDOW

& REF.

LEB

+

EOL

VCO

OSC EOIRF

1.7V

_

CHOKE

CHOKE SAT.

SAT.

PFSTOP

OVP

DIS

17V

LATCH

1.9V

UV

DETECTION

CONTROL

LOGIC

BOOTSTRAP DIODE

DEAD

TIME

SYNCHRONOUS

DRIVING

LOGIC

HB STOP

TIMING

MANAGEMENT

HVG

DRIVER

LEVEL

SHIFTER

LVG DRIVER

4.6

1.5

1.6V

Vcc

0.9V

Tch

Vcc

BOOT

HSD

OUT

LSD

GND

HBCS

May 2007 Rev 5 1/25

www.st.com

25

Contents L6585D

Contents

1 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.1 Start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.1.1 Pre-heating (time interval A Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.1.2 Ignition (time interval B Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.1.3 Run mode (time interval C Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 End of life – window comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7 Half-bridge current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8 CTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

9 Re–lamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

11 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2/25

L6585D Device description

1 Device description

Designed in High-voltage BCD Off-line technology, the L6585D embeds a PFC controller, a half-bridge controller, the relevant drivers and the logic necessary to build an electronic ballast.

The advanced and precise logic circuitry, combined with the programmability of the End-ofLife windows comparator threshold, makes the L6585D compliant with either "lamp-toground" or "block capacitor-to ground" configurations.

Another outstanding feature is the possibility of controlling and limiting the lamp voltage during the ignition phase.

The pre-heating and ignition durations are independently settable as well as the half-bridge switching frequencies for each operating phases (pre-heating, ignition and normal mode).

Other features (half-bridge over-current with frequency increase, PFC over-voltage) allow building a reliable and flexible solution with a reduced part count.

The PFC section achieves current mode control operating in Transition Mode; the highly linear multiplier includes a special circuit, able to reduce AC input current distortion, that allows wide-range-mains operation with an extremely low THD, even over a large load range.

The PFC output voltage is controlled by means of a voltage-mode error amplifier and a precise internal voltage reference.

The driver of the PFC is able to provide 300mA (source) and 600mA (sink) and the drivers of the half-bridge provide 290mA source and 480mA sink.

Figure 2. Typical system block diagram

L

PFC

C

BULK

R

12 3 45

OSC RF EOI

C

OSC

AC MAINS

R

4

PFG

PFCS

MULT

R

SNSPF

13

12

8

GND

4

ZCD

R

2

C

IN

R

3

6

INV

R

RUN

R

5

C

COMP

L6585D

R

PRE

C

IGN

COMP

HV BUS

R

7

91011

Tch

R

D

R

1

R

8

CTR

Vcc

7

17 20

7

17 20

6

EOLP

C

R

D

P

EOL-R

BOOT

19

18

16

1415

Charge

C

HSD

OUT

LSD

HBCS

pump

BOOT

R

SNSHB

L

B

C

RES

C

BLOCK

RES

LAMP

3/25

Pin settings L6585D

2 Pin settings

2.1 Connection

Figure 3. Pin sonnection (Top view)

BOOT

OSC

RF

EOI

TCH

EOLP

EOL-R

CTR

MULT

COMP

INV ZCD

BOOT

HSD

OUT

VCC

LSD

GND

HBCS

PFG

PFCS

4/25

L6585D Pin settings

2.2 Functions

Table 1. Pin functions

Pin num. Name Function

1OSC

2RF

3EOI

4Tch

5EOLP

6EOL-R

7CTR

8MULT

An external capacitor to GND fixes the half-bridge switching frequency with a ±3% precision.

Voltage reference able to source up to 240µA; the current sunk from this pin fixes the switching frequency of the half-bridge for each operating state.

A resistor (R

) connected to ground sets the half-bridge operating frequency

RUN

combined with the capacitor connected to the pin OSC. A resistor connected to EOI (R

) – in parallel with R

PRE

– sets the maximum

RUN

half-bridge switching frequency during pre-heating.

Connected to ground by a capacitor that, combined with R

, determines the

PRE

ignition duration

Pre-heating: low impedance to set high switching frequency Ignition and run mode: high impedance with controlled current sink in case of

HBCS threshold triggering.

Pin for setting the pre-heating time and the protection intervention. Connect a RC parallel network (R Pre-heating: the C

is charged by an internal current generator. When the pin

D

and CD) to ground

D

voltage reaches 4.63V the generator is disabled and the capacitor discharges because of RD; once the voltage drops below 1.52V, the preheating finishes, the ignition phase starts and the R

is discharged to ground.

DCD

Run mode: according to the kind of fault (either over-current or EOL) the internal generator charges the RC parallel network and appropriate actions are taken to stop the application. During proper behavior of the IC, this pin is low impedance.

Pin to program the EOL comparator. It is possible to select both the EOL sensing method and the window comparator

amplitude by connecting a resistor (R

EOLP

) to ground.

Input for the window comparator and re-lamp function. It can be used to detect the lamp ageing for either “lamp to ground” and “block

capacitor to ground” configurations. According to the EOLP pin setting, it is possible to program: – the window amplitude (V

– the center of the window (V

bus.

)

W

) either fixed or in tracking with the PFC output

SET

This function is blanked during the ignition phase. In case of either lamp disconnection or removal, a second threshold (V

SL-UP)

crossing latches the IC and drives the chip in “ready-mode” so that when the voltage at EOL-R pin is brought below V

SL-DOWN

(re-lamp) a new pre-

heating/ignition sequence is repeated.

Input pin for: – PFC over-voltage detection: the PFC driver is stopped until the voltage returns

in the proper operating range – Feedback disconnection detection – reference for End-of-life in case tracking reference; – shut-down: forcing the pin to a voltage lower than 0.75V, the IC shuts down in

unlatched condition.

Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the PFC current loop.

5/25

Pin settings L6585D

Table 1. Pin functions (continued)

Pin num. Name Function

Output of the error amplifier. A compensation network is placed between this pin

9COMP

10 INV

11 ZCD

12 PFCS

13 PFG

14 HBCS

15 GND Ground. Current return for both the signal part of the IC and the gate driver.

16 LSD

17 VCC

18 OUT

19 HSD

20 BOOT

and INV to achieve stability of the PFC voltage control loop and ensure high power factor and low THD.

Inverting input of the error amplifier. The information on the output voltage of the PFC pre-regulator is fed into the pin through a resistor divider. Input for the feedback disconnection comparator

Boost inductor’s demagnetization sensing input for PFC transition-mode operation. A negative-going edge triggers PFC MOSFET turn-on.

During start-up or when the voltage is not high enough to arm the internal comparator (e.g. AC Mains peak), the PFC driver is triggered by means of an internal starter.

Input to the PFC PWM comparator. The current flowing in the PFC mosfet is sensed by a resistor; the resulting voltage is applied to this pin and compared with an internal sinusoidal-shaped reference, generated by the multiplier, to determine the PFC MOSFET’ s turn-off.

A second comparison level detects abnormal currents (e.g. due to boost inductor saturation) and, on this occurrence, shuts down and latches the IC reducing its consumption to the start-up.

An internal LEB prevents undesired function triggering.

PFC gate driver output. The totem pole output stage is able to drive power MOSFET’S with a peak current of 300mA source and 600mA sink.

2-levels half-bridge current monitor for current control. The current flowing in the HB mosfet is sensed by a resistor; the resulting

voltage is applied to this pin. Low threshold (active during run mode): in case of thresholds crossing, the IC

reacts with self-adjusting frequency increase in order to limit the half-bridge (lamp) current.

High threshold:

– ignition: in case of thresholds crossing during the frequency shift, the IC reacts

with self-adjusting frequency increase in order to limit the lamp voltage and

preventing operation below resonance. – run mode: in case of thresholds crossing because of current spikes (due e. g.

to capacitive mode / cross-conduction), the L6585D latches to avoid

MOSFETs damaging,

Low side driver output: the output stage can deliver 290mA source and 480mA sink (typ. values).

Supply Voltage of both the signal part of the IC and the gate driver. Clamped with a Zener inside.

High Side Driver Floating Reference. This pin must be connected close to the source of the high side power MOS.

High side driver output: the output stage can deliver 290mA source and 480mA (typ. values).

Bootstrapped Supply Voltage. Between this pin and V must be connected.

A patented integrated circuitry replaces the external bootstrap diode, by means of a high voltage DMOS, synchronously driven with the low side power MOSFET.

, the bootstrap capacitor

CC

6/25

L6585D Electrical data

3 Electrical data

3.1 Maximum ratings

Table 2. Absolute maximum ratings

Symbol Pin Parameter Value Unit

V

BOOT

V

OUT

/dt 18 Floating ground max. slew rate 50 V/ns

dV

OUT

V

CC

20 Floating supply voltage -1 to 618 V

18 Floating ground voltage -3 to V

17 IC Supply voltage (ICC = 20mA)

(1)

Self-limited V

BOOT –

18 V

1, 3, 4,

8, 10, 12Analog input and outputs -0.3 to 5 V

2, 5 -0.3 to 2.7 V

6Vcc

7 -0.3 to 7 V

14 -5 to 5

9, 11 ZCD clamp (I

I

RF

I

EOLP

F

OSC(MAX)

P

TOT

1. The device has an internal Clamping Zener between GND and the VCC pin, it must not be supplied by a Low Impedance Voltage Source.

2 Current capability 240 µA

5 Current capability 100 µA

Maximum operating frequency 250 KHz

Power dissipation @TA = 70°C 0.83 W

< 4mA) Self-limited

ZCD

Note: ESD immunity for pins 18, 19 and 20 is guaranteed up to 900V (Human Body Model)

3.2 Thermal data

Table 3. Thermal data

Symbol Description Value Unit

R

thJA

T

STG

Max. thermal resistance junction to ambient 120 °C/W

Junction operating temperature range -40 to 150 °C

J

Storage temperature -55 to 150 °C

7/25

Electrical characteristics L6585D

4 Electrical characteristics

VCC = 15V, TA = 25°C, CL = 1nF, C

Table 4. Electrical characteristics

= 470pF, R

OSC

= 47K, unless otherwise specified

RUN

Symbol Pin Parameter Test condition Min Typ Max Unit

Supply voltage

Vcc V

V

CC(on)

V

CC(OFF)

VZ V

V

Operating range After turn-on 11 16 V

CC

Turn-on threshold

CC

Turn-off threshold

CC

Zener Voltage Icc = 20mA 16.2 17.2 17.7 V

CC

(1)

13.6 14.3 15 V

9.6 10.3 11 V

Supply current

I

ST-UP

ICC V

Iq V

V

Start-up current Before turn-on @ 13V 250 370 µA

CC

Operating supply current 7 mA

CC

Residual current IC latched 370 µA

CC

PFC section – multiplier input

IMULT MULT Input bias current V

V

∆V

MULT

∆V

MULT

K

CS

M

MULT Linear operation range V

MULT Output max. slope

MULT Gain V

= 0 -1 µA

MULT

= 3V 0 to 3 V

COMP

V

= 0 to 1V,

MULT

V

COMP

MULT

= 1V, V

= Upper clamp

= 3V 0.52 1/V

COMP

0.75 V/V

PFC section – error amplifier

VINV INV

INV Line regulation V

Voltage feedback input threshold

2.45 2.5 2.55 V

= 10.3V to 16V 50 mV

CC

IINV INV Input bias current -1 µA

Gv INV Voltage gain Open loop

GB INV Gain-bandwidth product

ICOMP COMP Source current V

Sink current V

V

COMP

COMP Upper clamp voltage I

Lower clamp voltage I

VDIS INV

Open loop detection threshold

(2)

COMP

SOURCE

SINK

CTR > 3.4 1.2 V

(2)

60 80 dB

1MHz

= 4V, V

= 2.4 V -2.6 mA

INV

= 2.6 V 4 mA

INV

= 0.5 mA 4.2 V

= 0.5 mA 2.25 V

COMP Static OVP threshold 2.1 2.25 2.4 V

8/25

L6585D Electrical characteristics

Table 4. Electrical characteristics (continued)

Symbol Pin Parameter Test condition Min Typ Max Unit

CTR pin

DIS CTR

PFOV CTR

Hysteresys 120 mV

Dynamic PFC overvoltage

Rising edge 3.4 V

Hysteresys 140 mV

Disable threshold Falling edge 0.75 V

Available range as tracking reference

CTR

Lower threshold (falling) 1.7 V

Hysteresys 0.12

Higher threshold (rising) 3.4 V

Hysteresys 0.14

PFC section – current sense comparator

ICS PFCS Input bias current V

tLEB PFCS Leading edge blanking

= 0 -1 µA

CS

(2)

100 200 300 ns

VCSdis PFCS IC disable level 1.65 1.75 1.85 V

td(H-L) PFCS Delay to output 120 ns

V

CSclamp

PFCS

Current sense reference clamp

V

= Upper clamp 1.0 1.08 1.16 V

COMP

PFC section – zero current detector

VZCDH ZCD Upper clamp voltage I

VZCDL ZCD Lower clamp voltage I

VZCDA ZCD

VZCDT ZCD

Arming voltage (positive-going edge)

Triggering voltage (negative-going edge)

IZCDb ZCD Input bias current V

I

ZCDsrc

I

ZCDsnk

ZCD Source current capability -4 mA

ZCD Sink current capability 4 mA

= 2.5 mA 5 V

ZCD

= -2.5 mA -0.3 0 0.3 V

ZCD

(2)

= 1 to 4.5 V 1 µA

ZCD

1.4 V

0.7 V

PFC section – gate driver

I

= 10mA 0.2 V

PFG Output high/low

SINK

I

SOURCE

= 10mA 14.5 V

tf PFG Fall time 40 90 ns

tr PFG Rise time 90 140 ns

I

SINK

I

SOURCE

PFG Peak sink current 475 600 mA

PFG Peak source current 200 300 mA

PFG Pull-down resistor 10 kΩ

9/25

Electrical characteristics L6585D

Table 4. Electrical characteristics (continued)

Symbol Pin Parameter Test condition Min Typ Max Unit

Half bridge section – Timing & oscillator

V

R

V

I

CH

CHP

CHN

TCH

I

EOI

REF

EOI

T

EOI Open state current V

Charge current V

CH

Charge threshold

CH

(positive going-edge)

Discharge threshold

CH

(negative going edge)

Leakage current

CH

Internal impedance Run mode 150 200 Ω

CH

= 2.2V 30 µA

TCH

(1)

1.5V < V

TCH

< 4.5V,

4.63 V

1.50 V

falling

= 2V 0.15 µA

EOI

0.1 µA

EOI EOI impedance During pre-heating 150 Ω

EOI current generator

EOI

during ignition and run mode

EOI EOI threshold

RF Reference voltage

Tspike = 200ns

Tspike = 400ns

Tspike = 600ns

Tspike = 1µs

(1)

(3)

1.83 1.9 1.98 V

1.92 2 2.08 V

20

100

200

270

IRF RF Max current capability 240 µA

OSC Rising threshold

OSC Falling threshold

(1)

3.7 V

0.9 V

D OSC Output duty cycle 48 50 52 %

T

DEAD

f

RUN

PRE

OSC Dead time 0.96 1.2 1.44 µs

OSC

Half-bridge oscillation frequency (run mode)

Half-bridge oscillation frequency (pre heating)

58.4 60.2 62 KHz

R

=50K 113.2 116.7 120.2 KHz

PRE

µA

Half bridge section – End Of Life FUNCTION and re-lamp comparator

EOLP Current capability 100 µA

EOLP Reference voltage 1.92 2 2.08 V

EOL-R Operating range EOLP=27K 0.95 4.15 V

220K = R

V

S

EOL-R

Window comparator reference

22K = R

R

EOLP

> 620K or

75K = R

220K = R 75K = R

V

W

Half window amplitude

R

EOLP

> 620K or

22K = R

EOLP

= 270K or

= 27K

= 91K

= 270K or

= 91K

= 27K

10/25

tracking with CTR

V

2.5

220 mV

720 mV

L6585D Electrical characteristics

Table 4. Electrical characteristics (continued)

Symbol Pin Parameter Test condition Min Typ Max Unit

EOL-R Sink/source capability 2.5 µA

EOL-R Relamp comparator 4.63 V

hysteresys 160 mV

Half bridge section – Half-bridge current sense

HBCSH HBCS

HBCSL HBCS V

Frequency increase threshold

< 1.9V (ignition) 1.53 1.6 1.66 V

V

EOI

> 1.9V (run mode) 0.850.910.97 V

EOI

HBCS Latched threshold Run mode 1.53 1.6 1.66 V

Half bridge section – Low side gate driver

LSD Output low voltage I

LSD Output high voltage I

= 10mA 0.3 V

SINK

SOURCE

= 10mA 14.5 V

LSD Peak source current 200 290 mA

LSD Peak sink current 400 480 mA

T

RISE

FAL L

LSD Rise time 120 ns

LSD Fall time 80 ns

LSD Pull-down resistor ; 45 KΩ

Half bridge section – High side gate driver (voltages referred to OUT)

HSD Output low voltage I

HSD Output high voltage I

= 10mA

SINK

SOURCE

= 10mA

HSD Peak source current 200 290 mA

HSD Peak sink current 400 480 mA

T

RISE

FAL L

HSD Rise time 120 ns

HSD Fall time 80 ns

HSD HSD-OUT pull-down 50 KΩ

V

BOOT

0.5

–

V

OUT

0.3

+

V

High-side floating gate-drive supply

(2)

5µA

BOOT Leakage current VBOOT = 600V

OUT Leakage current VOUT = 600V

Synchronous bootstrap diode on-resistance

1. Parameter in tracking

2. Specification over the -40°C to 125°C junction temperature range are ensured by design, characterization and statistical correlation

3. A pulse train has been sent to the HBCS pin with f=6KHz; the pulse duration is the one indicated in the notes as "TON"

V

= HIGH 250 Ω

LSD

11/25

Application information L6585D

5 Application information

5.1 Start-up sequence

5.1.1 Pre-heating (time interval A Figure 5)

After IC turn-on, unless a lamp absence is detected, the oscillator starts switching at a frequency (f

Equation 1

) set by values of C

PRE

OSC

and R

RUN

and R

Figure 4:

PRE

1.328

||

()⋅

OSCRRUNRPRE

The pre-heating time

is:

f

PRE

----------------------------------------------------------- -=

C

Equation 2

C

D

-------- - RDC I

CH

ln⋅⋅+⋅=

D

where C

T

and RD are shown in Figure 4 and ICH is typically 34 µA.

D

PRE

4.63

Figure 4. Oscillator, pre-heating and ignition circuitry

I

MAX

RF

R

RUN

C

IGN

R

PRE

EOI

4.63

-----------

1.52

V

REF

R

D

C

D

C

OSC

12/25

Tch

LOGIC

L6585D Application information

5.1.2 Ignition (time interval B Figure 5)

When the voltage at pin TCH drops down to 1.50V (typ.), the pin EOI is driven in high impedance state and C by C

IGN*RPRE

that defines the ignition time and the frequency shift starts.

The ignition time is the time necessary to EOI voltage to reach 1.9V, so, by means of simple calculation:

Equation 3

is exponentially charged according to the time constant τ given

IGN

T

IGN

3C

⋅⋅=

IGNRPRE

During this phase, the half-bridge current control can limit the maximum voltage applied to the lamp by forcing small frequency increases whenever the half-bridge sense resistor voltage exceeds the HBCSH threshold (see the “Half-Bridge current control” paragraph).

Figure 5, centre and right, shows the L6585D behavior as the lamp gets older; if it doesn’t

ignite for a time longer than the pre-heating one (counted by a cycle charge/discharge of the T

pin), the IC is stopped, enters low consumption and waits for either a re-lamp or an

CH

UVLO.

13/25

Application information L6585D

5.1.3 Run mode (time interval C Figure 5)

As the voltage at EOI exceeds 1.9V and the lamp has ignited, the L6585D enters Run mode and remains in this condition unless one of the protections (all enabled in this mode) is trigged.

The switching frequency reaches the F

value set by R

RUN

Equation 4

f

RUN

V

CC(on)

CC(off)

4.63V

1.9V

2V

f

PRE

f

RUN

τ = RDx C

1.5V

V

CC(on)

V

CC

D

Tch

EOI

f

HB

V

4.63V

1.5V

CC(on)

CC(off)

1.9V

2V

f

PRE

f

RUN

Figure 5. Oscillator, pre-heating and ignition sequence

V

CC

Tch

EOI

f

HB

---------------------------------- -=

R

RUNCOSC

1.328

⋅

V

Tch

EOI

and C

RUN

V

CC(on)

CC

f

HB

1.5V

V

CC(off)

1.9V

f

4.63V

2V

PRE

f

RUN

OSC

:

V

Z

V

HBCS

LAMP

ABC

V

HBCS

LAMP

ABC

14/25

V

HBCS

LAMP

ABC

L6585D End of life – window comparator

6 End of life – window comparator

To detect the ageing of the lamp with particular attention to the effect appearing as asymmetric rectification, a programmable (centered around “V higher than V

REF

” with amplitude “VW”) that triggers when the EOL-R voltage is

REF

+ VW/2 or lower than V

By means of the resistor connected to the EOLP pin, it is possible to select:

1. the sensing mode:

– fixed reference

: the centre of the window comparator (V

internal reference;

– tracking reference

: the centre of the window comparator is the voltage at pin CTR

(that is a signal proportional to the PFC output voltage).

2. the half-window amplitude (V

W

Figure 6. End-of-life detection circuitry and waveforms

R

P1

R

P2

C

BOOT

HV BUS

window comparator has been introduced

REF – VW

/2.

) is fixed at 2.5V by an

REF

/2): 220mV or 720mV.

HV BUS

C

BOOT

HV BUS

V

PFC

V

CB

CTR

EOLR

CTR

WINDOW

COMPARATOR

AMPLITUDE

EOLP

or R

R

FL

HVBUS (100Hz or 120Hz)

OUT

+ W/2

V

REF

V

–W/2

V

–W/2

V

–W/2

REF

FH

INTERNAL

INTERNAL FIXED REF.

FIXED REF.

INPUT

BOOT

EOLR

HSD

OUT

LSD

BOOT

CTR

BOOT

CTR

BOOT

CTR

FIXED REF.

WINDOW

COMPARATOR

AMPLITUDE

V

AMPLITUDE

LAMP

V

EOLR

EOLP

R

V

+ W/2 + V

V

+ W/2 + V

V

+ W/2 + V

REF

K

V

–W/2 –V

V

–W/2 –V

V

–W/2 –V

REF

V

+ W/2

REF

V

–W/2

V

–W/2

V

–W/2

REF

V

LAMP

V

K

R

E1

C

BLOCK

PFC

BLOCK

/2

OUT

R

E2

INTERNAL

INPUT

or R

FL

EOLR

FH

+ V

Z1

Z1 –VR2

HSD

OUT

LSD

R2

C

BLOCK

V

LAMP

V

K

R

E1

V

Z2

Z1

R

E2

BLOCK

15/25

End of life – window comparator L6585D

The four possible configurations are summarized in the following table, together with the value of resistance to be connected to the EOLP pin in order to obtain the desired setting:

Table 5. Configuration of the EOLP pin

EOLP resistor Symbol Reference Half–window amplitude

R

EOLP

220K = R

75K = R

22K = R

> 620K R

= 270K R

EOLP

= 91K R

EOLP

= 27K R

EOLP

FH

TL

FL

TL

Fixed 2.5V ± 720mV

Tracking with CTR ± 220mV

Fixed 2.5V ± 220mV

Tracking with CTR ± 720mV

Tracking reference:

this setting is suitable for the block capacitor to ground configuration

(Figure 6, left).

In this case the window comparator centre is set by the CTR voltage that is internally transferred to the EOL structure.

The effect of rectification appears as shifting of the DC voltage component across the block capacitor, which, under normal conditions, equals one half of the PFC output voltage.

A signal proportional to the DC block capacitor voltage is sent to the EOL-R pin by means of a resistive divider (R

and RE2); the dividers RE1 and RE2 and RP1 and R

E1

must be

P2

designed to set the EOL-R voltage equal to CTR under nominal condition.

Fixed reference:

this setting is suitable for the lamp to ground configuration (Figure 6, right).

The effect of rectification appears as shifting of the DC lamp voltage.

A resistive divider (R

and RE2) senses the voltage across the lamp under normal

E1

condition, that is an AC signal with zero average value whereas in case of asymmetric rectification the DC value can shift either in positive or negative direction. Two Zener diodes can be connected back-to-back between the EOL-R pin and the centre of the resistive divider.

The Zener voltages should differ by an amount as close as possible to the double of the internal reference to have a symmetrical detection, as it can easily obtained from the following equations:

● V

●

where VUP and V

UP

V

DOWN

= V

+ W/2 + V

REF

= V

REF

+ V

Z1

R2

– W/2 – VZ2 – V

are the VK values (equal in absolute value) that trigger the window

DOWN

R1

comparator.

To avoid an immediate intervention of the EOL protection, a filtering is introduced; as long as the fault condition persists, the Tch internal generator charges the C it opens. If this fault condition is still present when the Tch voltage decreases down to 1.5V, then the half bridge is stopped, otherwise (if the fault disappears) the counting is stopped and reset.

16/25

up to 4.63V and then

D

L6585D Half-bridge current control

7 Half-bridge current control

The information about the lamp current can be obtained by reading the voltage across a sense resistor placed in series to the source of the half-bridge low side MOS.

This circuitry is enabled at the end of the pre-heating phase and it enriches the L6585D with two features:

● Controlled lamp voltage/current during ignition (Figure 5): by properly setting the

sense resistor (such that the V voltage higher than the ignition voltage) it is possible to limit the maximum lamp voltage during ignition. In case of this occurrence, then the L6585D would react with a small frequency increase that allows limiting the lamp voltage (V risk of crossing the resonance frequency of the L ignites before T

reaches 1.50V (Figure 5 left) that is EOI has exceeded 1.9V, then:

CH

– EOI internal switch opens and its voltage moves asymptotically to 2V

– The switching frequency reaches the operating one;

– When T

reaches 1.52, it will be discharged

CH

If instead that the lamp hasn’t ignited after a time equal to the pre-heat time (Figure 5 right) the oscillator stops, the chip enters low consumption mode and this condition is latched until the mains supply voltage is removed or a re-lamp is detected.

● Over-current protection during run mode: if the HBCSL threshold is crossed, the T

internal generator is turned on as well as the one at pin EOI causing a frequency increase: this implements a current control structure.

level is crossed in correspondence of a lamp

HBCS

). This also prevents the

+IGN

BALLAST-CRES

circuit. If the lamp

CH

During run mode another protection is active: a second comparator (HBCSH) on the pin HBCS detects anomalous current flow through the sense resistor such as the spikes generated by the capacitive mode; the crossing of this second threshold latches the IC.

17/25

CTR L6585D

8 CTR

This is a multi-function pin, connected to a resistive divider to the PFC output bus:

● PFC over-voltage: in case of PFC output overshoot (e.g. at start-up) that causes a

threshold crossing, the PFC section stops switching until the pin voltage falls below

3.26V (typ.); this is helpful because the bandwidth of the PFC error amplifier is narrow so the control loop is not fast enough to properly reacts

● Feedback disconnection: The OVP function above described (together with the static

one embedded in the PFC error amplifier) is able to handle “normal” over-voltage conditions, i.e. those resulting from an abrupt load/line change or occurring at start-up. In case of over-voltage generated when the upper resistor of the feedback output divider fails open, the control loop can no longer read the information on the output voltage and will force the PFC pre-regulator to work at maximum ON time; if this occurs (i.e. the pin INV falls below 1.2V, typ.) and the CTR detects an OVP, the gate drivers activity is immediately stopped, the device enters low consumption and the condition is latched as long as the IC supply voltage is above the UVLO threshold;

● Reference for EOL in case of tracking reading.

● Disable: by forcing the pin below 0.75V an immediate unlatched shut-down is activated;

it can be also used as re-lamp in fact after the pin voltage is above 0.8V a preheating/ignition sequence is repeated.

18/25

L6585D Re–lamp

9 Re–lamp

A second comparator has been introduced on the pin EOL-R; a voltage higher than the internal threshold is read as lamp absence so the chip suddenly stops switching, enters idle mode (low consumption) and is ready for a new pre-heating/ignition sequence as soon as a new lamp is inserted.

In this idle mode the consumption of the chip is reduced so that the current flowing through the resistors (connected to the high voltage bus for the start-up) is enough to keep the V voltage above the UVLO threshold.

After a re-lamp cycle (that is the EOL-R voltage is brought above 4.63V and then released below), a new pre-heating/ignition sequence starts.

Table 6. IC configuration

Pre-heating Ignition Run mode

CC

EOI charge from 0 to

1.9V (typ.);

It depends on R

C

and

D

The frequency shifts

to f

from f

PRE

RUN

with

exponential trend

Until a fault appears or

the AC Mains is removed

RUN

---------------------------------- -=

R

RUNCOSC

Time duration

Half-bridge switching

frequency

cycle

1.328

()⋅

(1)

;

D

||

T

CH

It depends on RD and C

f

----------------------------------------------------------- -= f

PRE

C

OSCRRUNRPRE

RELAMP comparator ENABLED ENABLED ENABLED

CTR: PFC

overvoltage

ENABLED ENABLED ENABLED

CTR: disable function ENABLED ENABLED ENABLED

Half-bridge current

sense

EOL: window

comparator

ENABLED

DISABLED

– low threshold

disabled

– high threshold ⇒

increase

F

SW

⇒

DISABLED DISABLED ENABLED

ENABLED

– low threshold

increase

F

SW

– high threshold

latch

PFC choke saturation ENABLED ENABLED ENABLED

1. TCH cycle: charge of the TCH voltage up to 4.63V and discharge down to 1.50V following the RDCD time constant

1.328

⋅

⇒

19/25

Re–lamp L6585D

Table 7. Fault conditions

Fault Condition IC behavior Action required

–The TCH charge doesn’t start (no

ignition) – Drivers stopped – IC low consumption (V

clamped) Lamp replacement

cc

– All drivers stopped – IC low consumption (V

cycle

(1)

(reset if the fault

–T

CH

disappears) – drivers stopped at the end of T

cycle – IC low consumption (V

cycle

(1)

with lamp voltage

–T

CH

control – In case of HBCS at the end of the

TCH cycle, drivers stopped – IC low consumption (V

cycle

(1)

with lamp voltage

–T

CH

control (frequency increase)

clamped)

cc

clamped)

CC

clamped)

cc

CH

– In case of HBCS at the end of the

TCH cycle, drivers stopped – IC low consumption (V

clamped)

cc

– Drivers stopped – IC low consumption (V

clamped)

cc

(EOL-R below 4.63V)

Re-lamp cycle

(2)

Lamp absence

(re-lamp comparator)

End of life

Half-bridge current

sense

At turn-on: EOL-R voltage higher than

4.63V

Run mode: EOL-R voltage higher than

4.63V

EOL-R voltage outside the limits of window comparator

Ignition: HBCS threshold

Run mode: HBCSL threshold

Run mode: HBCSH threshold

When the CTR voltage

Shut-down

CTR voltage lower than

0.8V

– Drivers stopped – IC low consumption (V

clamped)

cc

returns above 0.8V, the

IC driver restart with a pre-heating sequence

Choke saturation

PFCS voltage higher than 1.6V

– Drivers stopped – IC low consumption (V

clamped)

cc

Re-lamp cycle

(2)(3)

When the CTR voltage

Over-voltage of PFC

output

CTR voltage higher than

3.4V

– PFC driver stopped

returns below

3.26V (Typ.), the PFC driver restarts

PFC open loop

(feedback

disconnection)

1. TCH cycle: charge of the TCH voltage up to 4.63V and discharge down to 1.50V following the RDCD time constant;

2. Re-lamp cycle: the voltage at EOL-R pin must be first pulled above 4.63V and then released below it; this typically happens in case of lamp replacement. After a re-lamp cycle, a new pre-heating sequence will be repeated.

3. This fault actually is a "board" fault so a lamp replacement is not effective to restart the ballast

CTR voltage higher than

3.4V AND INV voltage lower than 1.2

– Drivers stopped – IC low consumption (V

clamped)

cc

Re-lamp cycle

(2)(3)

20/25

L6585D Package mechanical data

10 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

21/25

Package mechanical data L6585D

Table 8. SO-20 mechanical data

Dimensions

mm. inch

Ref.

Min. Typ. Max. Min. Typ. Max.

A 2.65 0.104

a1 0.1 0.2 0.004 0.008

a2 2.45 0.096

b 0.35 0.49 0.014 0.019

b1 0.23 0.32 0.009 0.012

C 0.5 0.020

c1 45° (typ.)

D 12.60 13.00 0.496 0.512

E 10.00 10.65 0.393 0.419

e 1.27 0.050

e3 11.43 0.450

F 7.40 7.60 0.291 0.300

L 0.50 1.27 0.020 0.050

M 0.75 0.029

S 8° (max.)

Figure 7. Package dimensions

22/25

L6585D Order codes

11 Order codes

Table 9. Order codes

Part Number Package Packaging

L6585D SO-20 Tube

L6585DTR SO-20 Tape and Reel

23/25

Revision history L6585D

12 Revision history

Table 10. Revision history

Date Revision Changes

12-Jan-2006 1 Initial release

25-Oct-2006 2 Final datasheet

21-Dec-2006 3

12-Apr-2007 4 Updated electrical values on Ta bl e 4

23-May-2007 5 Updated Figure 1: Block diagram on page 1 and Eq.1 and 4

Updated f

page 8

value on Table 4: Electrical characteristics on

RUN

24/25

L6585D

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25/25

ST L6585D User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Device description

2 Pin settings

2.1 Connection

2.2 Functions

3 Electrical data

3.1 Maximum ratings

3.2 Thermal data

4 Electrical characteristics

5 Application information

5.1 Start-up sequence

5.1.1 Pre-heating (time interval A Figure 5)

5.1.2 Ignition (time interval B Figure 5)

5.1.3 Run mode (time interval C Figure 5)

7 Half-bridge current control

8 CTR

10 Package mechanical data

11 Order codes

12 Revision history