ST L6585D User Manual

L6585D

Combo IC for PFC and ballast control

Features

■Pre-heating and ignition phases independently programmable

■Ignition voltage control

■Transition mode PFC with over-current protection

■Programmable and precise End-of-life protection compliant with all ballast configurations

■Auto-adjusting half-bridge over-current control

■Automatic re-lamp

■3% oscillator precision

■1.2µs dead time

■PFC over-voltage protection and feedback disconnection

■Under voltage lock-out

SO-20

Applications

■ Electronic ballast

Figure 1. Block diagram

	COMP	MULT		PFCS			Vcc
2.5V	E/A
		MULTIPLIER		LEB
	+					1.7V					BOOT
	_	and THD
INV								17V
		OPTIMIZER								HVG
				+	+	_		UV			HSD
			_						SYNCHRONOUS	DRIVER
				PWM				DETECTION
1.2V	OL			COMP.				BOOTSTRAP DIODE			OUT
						CHOKE
								DEAD
ZCD						SAT.				LEVEL
								TIME	DRIVING	SHIFTER	Vcc
		S	R
0.7V	STARTER	Q						LATCH	LOGIC	LVG DRIVER
	Vcc										LSD
							OVP
								CONTROL		1.6V
PFG		PFSTOP	WINDOW			PFSTOP			HB STOP		GND
							DIS
			COMPARATOR					LOGIC
					EOL
CTR				& REF.
	OL
											HBCS
	OVP
3.4V								1.9V	TIMING		0.9V
	DIS
									MANAGEMENT		Vcc
0.75V	2V		2V							4.6
					VCO					1.5
EOLR
4.63V	RELAMP
		EOLP		RF	OSC		EOI				Tch
May 2007						Rev 5					1/25
											www.st.com

Contents	L6585D

Contents

1	Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. 3
2	Pin settings		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4
	2.1	Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		4
	2.2	Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		5
3	Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			7
	3.1	Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		7
	3.2	Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		7
4	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			8
5	Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			12
	5.1	Start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
		5.1.1	Pre-heating (time interval A Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . .	12
		5.1.2	Ignition (time interval B Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
		5.1.3	Run mode (time interval C Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
6	End of life – window comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			15
7	Half-bridge current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			17
8	CTR .	. . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
9	Re–lamp . . . .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
10	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			21
11	Order codes .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
12	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			24

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L6585D	Device description

1 Device description

Designed in High-voltage BCD Off-line technology, the L6585D embeds a PFC controller, a half-bridge controller, the relevant drivers and the logic necessary to build an electronic ballast.

The advanced and precise logic circuitry, combined with the programmability of the End-of- Life windows comparator threshold, makes the L6585D compliant with either "lamp-to- ground" or "block capacitor-to ground" configurations.

Another outstanding feature is the possibility of controlling and limiting the lamp voltage during the ignition phase.

The pre-heating and ignition durations are independently settable as well as the half-bridge switching frequencies for each operating phases (pre-heating, ignition and normal mode).

Other features (half-bridge over-current with frequency increase, PFC over-voltage) allow building a reliable and flexible solution with a reduced part count.

The PFC section achieves current mode control operating in Transition Mode; the highly linear multiplier includes a special circuit, able to reduce AC input current distortion, that allows wide-range-mains operation with an extremely low THD, even over a large load range.

The PFC output voltage is controlled by means of a voltage-mode error amplifier and a precise internal voltage reference.

The driver of the PFC is able to provide 300mA (source) and 600mA (sink) and the drivers of the half-bridge provide 290mA source and 480mA sink.

Figure 2. Typical system block diagram

LPFC

HV BUS

R5

R7

R1

CBULK

Charge

R4

R6

R8

pump

R2

CCOMP

CBOOT

AC MAINS

ZCD

INV

COMP

CTR

Vcc

BOOT

PFG

11

10

9

7

17

2019

13

HSD

LB

CIN

L6585D

18

12

OUT

PFCS

8

16

LSD

CRES

MULT

15

1

2

3

4

5

6

14

LAMP

GND

OSC

RF

EOI

Tch

EOLP

EOL-R

HBCS

R3

RSNSPF

RPRE

COSC

RRUN

RD

CD

RP

RSNSHB

CBLOCK

CIGN

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Pin settings	L6585D

2 Pin settings

2.1Connection

Figure 3. Pin sonnection (Top view)

OSC				BOOT
RF				HSD
EOI				OUT
TCH				VCC
EOLP				LSD
EOL-R				GND
CTR				HBCS
MULT				PFG
COMP				PFCS
INV				ZCD

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L6585D	Pin settings

2.2Functions

	Table 1.	Pin functions
	Pin num.	Name	Function
	1	OSC	An external capacitor to GND fixes the half-bridge switching frequency with a
			±3% precision.
			Voltage reference able to source up to 240µA; the current sunk from this pin fixes
			the switching frequency of the half-bridge for each operating state.
	2	RF	A resistor (RRUN) connected to ground sets the half-bridge operating frequency
			combined with the capacitor connected to the pin OSC.
			A resistor connected to EOI (RPRE) – in parallel with RRUN – sets the maximum
			half-bridge switching frequency during pre-heating.
			Connected to ground by a capacitor that, combined with RPRE, determines the
			ignition duration
	3	EOI	Pre-heating: low impedance to set high switching frequency
			Ignition and run mode: high impedance with controlled current sink in case of
			HBCS threshold triggering.
			Pin for setting the pre-heating time and the protection intervention.
			Connect a RC parallel network (RD and CD) to ground
			Pre-heating: the CD is charged by an internal current generator. When the pin
			voltage reaches 4.63V the generator is disabled and the capacitor discharges
	4	Tch	because of RD; once the voltage drops below 1.52V, the preheating finishes, the
			ignition phase starts and the RDCD is discharged to ground.
			Run mode: according to the kind of fault (either over-current or EOL) the
			internal generator charges the RC parallel network and appropriate actions are
			taken to stop the application. During proper behavior of the IC, this pin is low
			impedance.
			Pin to program the EOL comparator.
	5	EOLP	It is possible to select both the EOL sensing method and the window comparator
			amplitude by connecting a resistor (REOLP) to ground.
			Input for the window comparator and re-lamp function.
			It can be used to detect the lamp ageing for either “lamp to ground” and “block
			capacitor to ground” configurations.
			According to the EOLP pin setting, it is possible to program:
			– the window amplitude (VW)
	6	EOL-R	– the center of the window (VSET) either fixed or in tracking with the PFC output
			bus.
			This function is blanked during the ignition phase.
			In case of either lamp disconnection or removal, a second threshold (VSL-UP)
			crossing latches the IC and drives the chip in “ready-mode” so that when the
			voltage at EOL-R pin is brought below VSL-DOWN (re-lamp) a new pre-
			heating/ignition sequence is repeated.
			Input pin for:
			– PFC over-voltage detection: the PFC driver is stopped until the voltage returns
	7	CTR	in the proper operating range
			– Feedback disconnection detection
			– reference for End-of-life in case tracking reference;
			– shut-down: forcing the pin to a voltage lower than 0.75V, the IC shuts down in
			unlatched condition.
			Main input to the multiplier. This pin is connected to the rectified mains voltage
	8	MULT	via a resistor divider and provides the sinusoidal reference to the PFC current
			loop.

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Pin settings			L6585D
	Table 1.	Pin functions (continued)
	Pin num.	Name	Function
			Output of the error amplifier. A compensation network is placed between this pin
	9	COMP	and INV to achieve stability of the PFC voltage control loop and ensure high
			power factor and low THD.
			Inverting input of the error amplifier. The information on the output voltage of the
	10	INV	PFC pre-regulator is fed into the pin through a resistor divider. Input for the
			feedback disconnection comparator
			Boost inductor’s demagnetization sensing input for PFC transition-mode
			operation. A negative-going edge triggers PFC MOSFET turn-on.
	11	ZCD	During start-up or when the voltage is not high enough to arm the internal
			comparator (e.g. AC Mains peak), the PFC driver is triggered by means of an
			internal starter.
			Input to the PFC PWM comparator. The current flowing in the PFC mosfet is
			sensed by a resistor; the resulting voltage is applied to this pin and compared
			with an internal sinusoidal-shaped reference, generated by the multiplier, to
	12	PFCS	determine the PFC MOSFET’ s turn-off.
			A second comparison level detects abnormal currents (e.g. due to boost inductor
			saturation) and, on this occurrence, shuts down and latches the IC reducing its
			consumption to the start-up.
			An internal LEB prevents undesired function triggering.
	13	PFG	PFC gate driver output. The totem pole output stage is able to drive power
			MOSFET’S with a peak current of 300mA source and 600mA sink.
			2-levels half-bridge current monitor for current control.
			The current flowing in the HB mosfet is sensed by a resistor; the resulting
			voltage is applied to this pin.
			Low threshold (active during run mode): in case of thresholds crossing, the IC
			reacts with self-adjusting frequency increase in order to limit the half-bridge
	14	HBCS	(lamp) current.
			High threshold:
			– ignition: in case of thresholds crossing during the frequency shift, the IC reacts
			with self-adjusting frequency increase in order to limit the lamp voltage and
			preventing operation below resonance.
			– run mode: in case of thresholds crossing because of current spikes (due e. g.
			to capacitive mode / cross-conduction), the L6585D latches to avoid
			MOSFETs damaging,
	15	GND	Ground. Current return for both the signal part of the IC and the gate driver.
	16	LSD	Low side driver output: the output stage can deliver 290mA source and 480mA
			sink (typ. values).
	17	VCC	Supply Voltage of both the signal part of the IC and the gate driver.
			Clamped with a Zener inside.
	18	OUT	High Side Driver Floating Reference. This pin must be connected close to the
			source of the high side power MOS.
	19	HSD	High side driver output: the output stage can deliver 290mA source and 480mA
			(typ. values).
			Bootstrapped Supply Voltage. Between this pin and VCC, the bootstrap capacitor
	20	BOOT	must be connected.
			A patented integrated circuitry replaces the external bootstrap diode, by means
			of a high voltage DMOS, synchronously driven with the low side power MOSFET.

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L6585D	Electrical data

3 Electrical data

3.1Maximum ratings

Table 2.	Absolute maximum ratings
Symbol	Pin	Parameter	Value	Unit
VBOOT	20	Floating supply voltage	-1 to 618	V
VOUT	18	Floating ground voltage	-3 to VBOOT – 18	V
dVOUT /dt	18	Floating ground max. slew rate	50	V/ns
VCC	17	IC Supply voltage (ICC = 20mA)(1)	Self-limited	V
	1, 3, 4,
	8, 10,	Analog input and outputs	-0.3 to 5	V
	12
	2, 5		-0.3 to 2.7	V
	6		Vcc
	7		-0.3 to 7	V
	14		-5 to 5
	9, 11	ZCD clamp (IZCD < 4mA)	Self-limited
IRF	2	Current capability	240	µA
IEOLP	5	Current capability	100	µA
FOSC(MAX)		Maximum operating frequency	250	KHz
PTOT		Power dissipation @TA = 70°C	0.83	W

1.The device has an internal Clamping Zener between GND and the VCC pin, it must not be supplied by a Low Impedance Voltage Source.

Note:

ESD immunity for pins 18, 19 and 20 is guaranteed up to 900V (Human Body Model)

3.2Thermal data

Table 3.	Thermal data
Symbol	Description	Value	Unit
RthJA	Max. thermal resistance junction to ambient	120	°C/W
TJ	Junction operating temperature range	-40 to 150	°C
TSTG	Storage temperature	-55 to 150	°C

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Electrical characteristics	L6585D

4 Electrical characteristics

		VCC = 15V, TA = 25°C, CL = 1nF, COSC = 470pF, RRUN = 47K, unless otherwise specified
Table 4.		Electrical characteristics
Symbol			Pin	Parameter	Test condition	Min	Typ	Max	Unit
Supply voltage
	Vcc		VCC	Operating range	After turn-on	11		16	V
	VCC(on)		VCC	Turn-on threshold	(1)	13.6	14.3	15	V
VCC(OFF)			VCC	Turn-off threshold	(1)	9.6	10.3	11	V
	VZ		VCC	Zener Voltage	Icc = 20mA	16.2	17.2	17.7	V
Supply current
	IST-UP		VCC	Start-up current	Before turn-on @ 13V		250	370	µA
	ICC		VCC	Operating supply current			7		mA
	Iq		VCC	Residual current	IC latched			370	µA
PFC section – multiplier input
	IMULT		MULT	Input bias current	VMULT = 0			-1	µA
	VMULT		MULT	Linear operation range	VCOMP = 3V	0 to 3			V
	∆VCS		MULT	Output max. slope	VMULT = 0 to 1V,		0.75		V/V
	∆VMULT				VCOMP = Upper clamp
	KM		MULT	Gain	VMULT = 1V, VCOMP= 3V		0.52		1/V
PFC section – error amplifier
	VINV		INV	Voltage feedback input		2.45	2.5	2.55	V
				threshold
			INV	Line regulation	VCC = 10.3V to 16V			50	mV
	IINV		INV	Input bias current				-1	µA
	Gv		INV	Voltage gain	Open loop (2)	60	80		dB
	GB		INV	Gain-bandwidth product	(2)		1		MHz
	ICOMP		COMP	Source current	VCOMP = 4V, VINV = 2.4 V		-2.6		mA
				Sink current	VCOMP = 4V, VINV = 2.6 V		4		mA
	VCOMP		COMP	Upper clamp voltage	ISOURCE = 0.5 mA		4.2		V
				Lower clamp voltage	ISINK = 0.5 mA		2.25		V
	VDIS		INV	Open loop detection	CTR > 3.4		1.2		V
				threshold
			COMP	Static OVP threshold		2.1	2.25	2.4	V

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