ST L6566A User Manual

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L6566A

Multi-mode controller for SMPS with PFC front-end

Features

■Selectable multi-mode operation: fixed frequency or quasi-resonant

■On-board 700 V high-voltage start-up

■Advanced light load management

■Low quiescent current (< 3 mA)

■Adaptive UVLO

■Line feedforward for constant power capability vs. mains voltage

■Pulse-by-pulse OCP, shutdown on overload (latched or autorestart)

■Transformer saturation detection

■Switched supply rail for PFC controller

■Latched or autorestart OVP

■Brownout protection

■-600/+800 mA totem pole gate driver with active pull-down during UVLO

■SO16N package

SO16N

Applications

■Notebook, TV &LCD monitors adapters

■High power chargers

■PDP/LCD TV

■Consumer appliances, like DVD, VCR, set-top box

■IT equipment, games, aux. power supplies

■Power supplies in excess of 150 W

Figure 1. Block diagram

VREF

SS

COMP

VFF

10

14

9

15

VCC

6.4V

TIME

1

SOFT-START

OVP

-

OVPL

OUT

LOW CLAMP

OFF2

HV

1 mA

&

& DISABLE

+

FAULT MNGT

LINE VOLTAGE

7.7V

Q

Icharge

VOLTAGE

Reference

FEEDFORWARD

CS

VCC

REGULATOR

voltages

LEB

Internal supply

5

&

1.5 V

7

ADAPTIVE UVLO

UVLO

VCC

Vth

-

+

-

+

+

-

VCC

OCP2

PWM

OCP

Vcc_PFC

6

IC_LATCH

400 uA

+

AC_FAIL

-

-

Hiccup-mode

14V

UVLO_SHF

OCP logic

5.7V

BURST-MODE

+

OCP2

4

GD

OSC

13

OSCILLATOR

R

Q

DRIVER

MODE SELECTION

S

MODE/SC

12

&

TURN-ON LOGIC

50 mV

ZERO CURRENT

TIME

OVPL

-

OUT

100 mV

DETECTOR

ZCD

11

+

OFF2

4.5V

OVERVOLTAGE

OVP

-

LATCH

PROTECTION

+

DIS

8

IC_LATCH

16

-

AC_OK

AC_FAIL

DISABLE

15 µA

0.450V

3 V

+

UVLO

0.485V

3

GND

August 2007

Rev 1

1/51

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Contents	L6566A

Contents

1	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 6
2	Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
	2.1	Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
	2.2	Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
3	Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
	3.1	Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	3.2	Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
4	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
5	Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
	5.1	High-voltage start-up generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	5.2	Zero current detection and triggering block; oscillator block . . . . . . . . . .	21
	5.3	Burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . .	24
	5.4	Adaptive UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
	5.5	PWM control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
	5.6	PWM comparator, PWM latch and voltage feedforward blocks . . . . . . . .	27
	5.7	Hiccup-mode OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
	5.8	PFC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
	5.9	Latched disable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
	5.10	Soft-start and delayed latched shutdown upon overcurrent . . . . . . . . . . .	33
	5.11	OVP block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	35
	5.12	Brownout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	38
	5.13	Slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40
	5.14	Summary of L6566A power management functions . . . . . . . . . . . . . . . .	41

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L6566A		Contents
6	Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 44
7	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 47
8	Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 49
9	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 50

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List of tables	L6566A

List of tables

Table 2. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 6. L6566A light load management features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 7. L6566A protections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 8. External circuits that determine IC behavior upon OVP and OCP . . . . . . . . . . . . . . . . . . . 45 Table 9. SO16N mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 10. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4/51

L6566A	List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. Typical system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Pin connection (through top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Multi-mode operation with QR option active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5. High-voltage start-up generator: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6. Timing diagram: normal power-up and power-down sequences . . . . . . . . . . . . . . . . . . . . 19 Figure 7. Timing diagram showing short-circuit behavior (SS pin clamped at 5V). . . . . . . . . . . . . . . 20 Figure 8. Zero current detection block, triggering block, oscillator block and related logic . . . . . . . . 20 Figure 9. Drain ringing cycle skipping as the load is gradually reduced . . . . . . . . . . . . . . . . . . . . . . 21 Figure 10. Operation of ZCD, triggering and Oscillator blocks (QR option active). . . . . . . . . . . . . . . . 23 Figure 11. Load-dependent operating modes: timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 12. Addition of an offset to the current sense lowers the burst-mode operation threshold. . . . 25 Figure 13. Adaptive UVLO block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 14. Possible feedback configurations that can be used with the L6566A. . . . . . . . . . . . . . . . . 26 Figure 15. Externally controlled burst-mode operation by driving pin COMP: timing diagram. . . . . . . 27 Figure 16. Typical power capability change vs input voltage in QR flyback converters . . . . . . . . . . . 28 Figure 17. Left: Overcurrent setpoint vs. VFF voltage; right: Line Feedforward function block . . . . . . 29 Figure 18. Hiccup-mode OCP: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 19. Possible interfaces between the L6566A and a PFC controller . . . . . . . . . . . . . . . . . . . . . 32 Figure 20. Operation after latched disable activation: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 21. Soft-start pin operation under different operating conditions and settings . . . . . . . . . . . . . 34 Figure 22. OVP Function: internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 23. OVP function: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 24. Maximum allowed duty cycle vs. switching frequency for correct OVP detection. . . . . . . . 37 Figure 25. Brownout protection: internal block diagram and timing diagram . . . . . . . . . . . . . . . . . . . . 38 Figure 26. Ac voltage sensing with the L6566A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 27. Slope compensation waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 28. Typical low-cost application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 29. Typical full-feature application schematic (QR operation) . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 30. Typical full-feature application schematic (FF operation) . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 31. Frequency foldback at light load (FF operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 32. Latched shutdown upon mains overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

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Description	L6566A

1 Description

The L6566A is an extremely versatile current-mode primary controller IC specifically designed for high-performance offline flyback converters operated from front-end Power Factor Correction (PFC) stages in applications supposed to comply with EN61000-3-2 or JEITA-MITI regulations.

Both Fixed-frequency (FF) and Quasi-resonant (QR) operation are supported. The user can pick either of the two depending on application needs.

The device features an externally programmable oscillator: it defines converter's switching frequency in FF mode and the maximum allowed switching frequency in QR mode.

When FF operation is selected, the IC works like a standard current-mode controller with a maximum duty cycle limited at 70% min.

QR operation, when selected, occurs and is achieved through a transformer demagnetization sensing input that triggers MOSFET's turn-on. Under some conditions, ZVS (Zero-voltage Switching) can be achieved. Converter's power capability rise with the input voltage is compensated by line voltage feedforward. At medium and light load, as the QR operating frequency equals the oscillator frequency, a function (valley skipping) is activated to prevent further frequency rise and keep the operation as close to ZVS as possible.

With either FF or QR operation, at very light load the IC enters a controlled burst-mode operation that, along with the built-in non-dissipative high-voltage start-up circuit and a reduced quiescent current, helps keep low the consumption from the mains and meet energy saving recommendations.

To allow meeting them in two-stage power-factor-corrected systems as well, the L6566A provides an interface with the PFC controller that enables to turn off the pre-regulator at light load.

An innovative adaptive UVLO helps minimize the issues related to the fluctuations of the self-supply voltage due to transformer's parasitics.

The protection functions included in this device are: not-latched input undervoltage (brownout), output OVP (auto-restart or latch-mode selectable), a first-level OCP with delayed shutdown to protect the system during overload or short circuit conditions (autorestart or latch-mode selectable) and a second-level OCP that is invoked when the transformer saturates or the secondary diode fails short. A latched disable input allows easy implementation of OTP with an external NTC, while an internal thermal shutdown prevents IC overheating.

Programmable soft-start, leading-edge blanking on the current sense input for greater noise immunity, slope compensation (in FF mode only), and a shutdown function for externally controlled burst-mode operation or remote ON/OFF control complete the equipment of this device.

6/51

L6566A	Description

Figure 2. Typical system block diagram

PFC PRE-REGULATOR		FLYBACK DC-DC CONVERTER
Rectified
Mains		Voutdc
Voltage
	PWM/QR controller is turned off in case of PFC's
	anomalous operation, for safety
L6563/A		L6566A
PFC
	PFC is automatically turned off at light
	load to ease compliance with
	energy saving specifications.

7/51

Pin settings	L6566A

2 Pin settings

2.1Connections

Figure 3. Pin connection (through top view)

HVS		1	16		AC_OK
N.C.		2	15		VFF
GND		3	14		SS
GD		4	13		OSC
Vcc		5	12		MODE/SC
Vcc_PFC		6	11		ZCD
CS		7	10		VREF
DIS		8	9		COMP

2.2Pin description

Table 2. Pin functions

	N°	Pin	Function
			High-voltage start-up. The pin, able to withstand 700V, is to be tied directly to the
			rectified mains voltage. A 1 mA internal current source charges the capacitor
			connected between Vcc pin (5) and GND pin (3) until the voltage on the Vcc pin
			reaches the turn-on threshold, then it is shut down. Normally, the generator is re-
	1	HVS	enabled when the Vcc voltage falls below 5V to ensure a low power throughput
			during short circuit. Otherwise, when a latched protection is tripped the generator is
			re-enabled 0.5V below the turn-on threshold, to keep the latch supplied; or, when
			the IC is turned off by pin COMP (9) pulled low the generator is active just below
			the UVLO threshold to allow a faster restart.
	2	N.C.	Not internally connected. Provision for clearance on the PCB to meet safety
			requirements.
			Ground. Current return for both the signal part of the IC and the gate drive. All of
	3	GND	the ground connections of the bias components should be tied to a track going to
			this pin and kept separate from any pulsed current return.
	4	GD	Gate driver output. The totem pole output stage is able to drive power MOSFET’s
			and IGBT’s with a peak current capability of 800 mA source/sink.

8/51

L6566A			Pin settings
	Table 2. Pin functions (continued)
	N°	Pin	Function
			Supply Voltage of both the signal part of the IC and the gate driver. The internal
			high voltage generator charges an electrolytic capacitor connected between this
			pin and GND (pin 3) as long as the voltage on the pin is below the turn-on threshold
	5	Vcc	of the IC, after that it is disabled and the chip is turned on. The IC is disabled as the
			voltage on the pin falls below the UVLO threshold. This threshold is reduced at light
			load to counteract the natural reduction of the self-supply voltage. Sometimes a
			small bypass capacitor (0.1 µF typ.) to GND might be useful to get a clean bias
			voltage for the signal part of the IC.
			Supply pin output. This pin is intended for supplying the PFC controller IC in
			systems comprising a PFC pre-regulator or other compatible circuitry. It is internally
	6	Vcc_PFC	connected to the Vcc pin (5) via a controlled switch. The switch is closed as the IC
			starts up and opens when the voltage at pin COMP is lower than a threshold (light
			load), whenever the IC is shut down (either latched or not) and during UVLO. If not
			used, the pin will be left floating.
			Input to the PWM comparator. The current flowing in the MOSFET is sensed
			through a resistor, the resulting voltage is applied to this pin and compared with an
			internal reference to determine MOSFET’s turn-off. The pin is equipped with 150 ns
			min. blanking time after the gate-drive output goes high for improved noise
	7	CS	immunity. A second comparison level located at 1.5V latches the device off and
			reduces its consumption in case of transformer saturation or secondary diode short
			circuit. The information is latched until the voltage on the Vcc pin (5) goes below
			the UVLO threshold, hence resulting in intermittent operation. A logic circuit
			improves sensitivity to temporary disturbances.
			IC’s latched disable input. Internally the pin connects a comparator that, when the
			voltage on the pin exceeds 4.5V, latches off the IC and brings its consumption to a
			lower value. The latch is cleared as the voltage on the Vcc pin (5) goes below the
	8	DIS	UVLO threshold, but the HV generator keeps the Vcc voltage high (see pin 1
			description). It is then necessary to recycle the input power to restart the IC. For a
			quick restart pull pin 16 (AC_OK) below the disable threshold (see pin 16
			description).Bypass the pin with a capacitor to GND (pin 3) to reduce noise pick-up.
			Ground the pin if the function is not used.
			Control input for loop regulation. The pin will be driven by the phototransistor
			(emitter-grounded) of an optocoupler to modulate its voltage by modulating the
			current sunk. A capacitor placed between the pin and GND (3), as close to the IC
	9	COMP	as possible to reduce noise pick-up, sets a pole in the output-to-control transfer
			function. The dynamics of the pin is in the 2.5 to 5V range. A voltage below an
			internally defined threshold activates burst-mode operation. The voltage at the pin
			is bottom-clamped at about 2V. If the clamp is externally overridden and the voltage
			is pulled below 1.4V the IC will shut down.
			An internal generator furnishes an accurate voltage reference (5V±2%) that can be
			used to supply few mA to an external circuit. A small film capacitor (0.1 µF typ.),
	10	VREF	connected between this pin and GND (3), is recommended to ensure the stability of
			the generator and to prevent noise from affecting the reference. This reference is
			internally monitored by a separate auxiliary reference and any failure or drift will
			cause the IC to latch off.

9/51

Pin settings			L6566A
	Table 2. Pin functions (continued)
	N°	Pin	Function
			Transformer demagnetization sensing input for quasi-resonant operation and OVP
			input. The pin is externally connected to the transformer’s auxiliary winding through
			a resistor divider. A negative-going edge triggers MOSFET’s turn-on if QR mode is
11		ZCD	selected.
			A voltage exceeding 5V shuts the IC down and brings its consumption to a lower
			value (OVP). Latch-off or auto-restart mode is selectable externally. This function is
			strobed and digitally filtered to increase noise immunity.
			Operating mode selection. If the pin is connected to the VREF pin (7) Quasi-
			resonant operation is selected and the oscillator (pin 13, OSC) determines the
			maximum allowed operating frequency.
			Fixed-frequency operation is selected if the pin is not tied to VREF, in which case
12		MODE/SC	the oscillator determines the actual operating frequency, the maximum allowed
			duty cycle is set at 70% min. and the pin delivers a voltage ramp synchronized to
			the oscillator when the gate-drive output is high; the voltage delivered is zero while
			the gate-drive output is low. The pin is to be connected to pin CS (7) via a resistor
			for slope compensation.
			Oscillator pin. The pin is an accurate 1 V voltage source, and a resistor connected
			from the pin to GND (pin 3) defines a current. This current is internally used to set
13		OSC	the oscillator frequency that defines the maximum allowed switching frequency of
			the L6566A, if working in QR mode, or the operating switching frequency if working
			in FF mode.

Soft-start current source. At start-up a capacitor Css between this pin and GND (pin 3) is charged with an internal current generator. During the ramp, the internal reference clamp on the current sense pin (7, CS) rises linearly starting from zero to its final value, thus causing the duty cycle to increase progressively starting from

14SS zero as well. During soft-start the Adaptive UVLO function and all functions monitoring pin COMP are disabled. The soft-start capacitor is discharged whenever the supply voltage of the IC falls below the UVLO threshold. The same capacitor is used to delay IC’s shutdown (latch-off or auto-restart mode selectable) after detecting an overload condition (OLP).

Line voltage feedforward input. The information on the converter’s input voltage is fed into the pin through a resistor divider and is used to change the setpoint of the pulse-by-pulse current limitation (the higher the voltage, the lower the setpoint).

15 VFF

The linear dynamics of the pin ranges from 0 to 3V. A voltage higher than 3V makes the IC stop switching. If feedforward is not desired, tie the pin to GND (pin 3) directly if a latch-mode OVP is not required (see pin 11, ZCD) or through a resistor if a latch-mode OVP is required. Bypass the pin with a capacitor to GND (pin 3) to reduce noise pick-up.

Brownout protection input. A voltage below 0.45V shuts down (not latched) the IC, lowers its consumption, opens the Vcc_PFC pin (6), and clears the latch set by latched protections (DIS>4.5V, SS>6.4V, VFF>6.4V). IC’s operation is re-enabled as the voltage exceeds 0.45V. The comparator is provided with current hysteresis:

16 AC_OK an internal 15 µA current generator is ON as long as the voltage on the pin is below 0.45V and is OFF if this value is exceeded. Bypass the pin with a capacitor to GND (pin 3) to reduce noise pick-up. Tie to Vcc with a 220 to 680 kΩ resistor if the function is not used.

10/51

L6566A	Electrical data

3 Electrical data

3.1Maximum rating

Table 3. Absolute maximum ratings

Symbol	Pin	Parameter	Value	Unit
VHVS	1	Voltage range (referred to ground)	-0.3 to 700	V
IHVS	1	Start-up current	Self-limited
VCC	5	IC supply voltage (Icc = 20 mA)	Self-limited
VVcc_PFC	6	Voltage range	-0.3 to Vcc	V
IVcc_PFC	6	Max. source current (continuous)	30	mA
Vmax	7, 8, 10, 14	Analog inputs & outputs	-0.3 to 7	V
Vmax	9, 15, 16	Maximum pin voltage (Ipin ≤1mA)	Self-limited
IZCD	11	Zero current detector max. current	±5	mA
VMODE/SC	12	Voltage range	-0.3 to 5	V
VOSC	13	Voltage range	-0.3 to 3.3	V
PTOT		Power dissipation @TA = 50°C	0.75	W

3.2Thermal data

Table 4. Thermal data

Symbol	Parameter	Value	Unit
RthJA	Thermal resistance junction to ambient	120	°C/W
TJ	Junction operating temperature range	-40 to 150	°C

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Electrical characteristics	L6566A

4 Electrical characteristics

(TJ = -25 to 125°C, VCC = 12, CO = 1 nF; MODE/SC=VREF, RT = 20 kΩ from OSC to GND, unless otherwise specified).

Table 5. Electrical characteristics

	Symbol	Parameter	Test condition	Min.	Typ.	Max.	Unit
	Supply voltage
	Vcc	Operating range after turn-on	VCOMP > VCOMPL	10.6		23	V
			VCOMP = VCOMPO	8		23
	VccOn	Turn-on threshold	(1)	13	14	15	V
	VccOff	Turn-off threshold	(1) VCOMP > VCOMPL	9.4	10	10.6	V
			(1) VCOMP = VCOMPO	7.2	7.6	8.0
	Hys	Hysteresis	VCOMP > VCOMPL		4		V
	VZ	Zener voltage	Icc = 20 mA, IC disabled	23	25	27	V
	Supply current
	Istart-up	Start-up current	Before turn-on, Vcc = 13 V		200	250	µA
	Iq	Quiescent current	After turn-on, VZCD = VCS = 1V		2.6	2.8	mA
	Icc	Operating supply current	MODE/SC open		4	4.6	mA
	Iqdis	Quiescent current	IC disabled (2)	330		2500	µA
			IC latched off		440	500
	High-voltage start-up generator
	VHV	Breakdown voltage	IHV < 100 µA	700			V
	VHVstart	Start voltage	IVcc < 100 µA	65	80	100	V
	Icharge	Vcc charge current	VHV > VHvstart, Vcc > 3V	0.55	0.85	1	mA
	IHV, ON	ON-state current	VHV > VHvstart, Vcc > 3V			1.6	mA
			VHV > VHvstart, Vcc = 0			0.8
	IHV, OFF	OFF-state leakage current	VHV = 400 V			40	µA
			Vcc falling	4.4	5	5.6
	VCCrestart	Vcc restart voltage	(1) IC latched off	12.5	13.5	14.5	V
			(1) Disabled by	9.4	10	10.6
			VCOMP < VCOMPOFF

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L6566A							Electrical characteristics
Table 5. Electrical characteristics			(continued)
Symbol		Parameter		Test condition			Min.	Typ.	Max.	Unit
Reference voltage
V	REF	Output voltage		(1) T = 25 °C; I	REF	= 1 mA	4.95	5	5.05	V
				J
VREF		Total variation		IREF = 1 to 5 mA,			4.9		5.1	V
				Vcc= 10.6 to 23 V
IREF		Short circuit current		VREF = 0			10		30	mA
		Sink capability in UVLO		Vcc = 6V; Isink = 0.5 mA				0.2	0.5	V
VOV		Overvoltage threshold					5.3	5.7		V
Internal oscillator
				Operating range			10		300
				TJ = 25°C, VZCD = 0,			95	100	105
fsw		Oscillation frequency		MODE/SC = Open						kHz
				Vcc=12 to 23 V, VZCD = 0,			93	100	107
				MODE/SC = Open
VOSC		Voltage reference		(3)			0.97	1	1.03	V
Dmax		Maximum duty cycle		MODE/SC = Open,			70		75	%
				VCOMP = 5 V
Brownout protection
Vth		Threshold voltage		Voltage falling (turn-off)			0.432	0.450	0.468	V
				Voltage rising (turn-on)			0.452	0.458	0.518	V
IHys		Current Hysteresis		Vcc > 5V, VVFF = 0.3V			12	15	18	µA
VAC_OK_CL		Clamp level		(1) IAC_OK = 100µA			3	3.15	3.3	V
Line voltage feedforward
IVFF		Input bias current		VVFF = 0 to 3 V, VZCD < VZCDth					-1	µA
				VZCD > VZCDth			-0.7	-1		mA
VVFF		Linear operation range						0 to 3		V
VOFF		IC disable voltage					3	3.15	3.3	V
VVFFlatch		Latch-off/clamp level		VZCD > VZCDth				6.4		V
Kc		Control voltage gain (3)		VVFF = 1 V, VCOMP = 4 V				0.4		V/V
KFF		Feedforward gain (3)		VVFF = 1 V, VCOMP = 4 V				0.04		V/V

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Electrical characteristics							L6566A
Table 5. Electrical characteristics (continued)
Symbol		Parameter	Test condition	Min.	Typ.	Max.		Unit
Current sense comparator
	ICS	Input bias current	VCS = 0			-1		µA
	tLEB	Leading edge blanking		150	250	300		ns
	td(H-L)	Delay to output				100		ns
			VCOMP = VCOMPHI, VVFF = 0V	0.92	1	1.08
	VCSx	Overcurrent setpoint	VCOMP = VCOMPHI, VVFF = 1.5V	0.45	0.5	0.55		V
			VCOMP = VCOMPHI, VVFF = 3.0V		0	0.1
	VCSdis	Hiccup-mode OCP level	(1)	1.4	1.5	1.6		V
PWM control
VCOMPHI		Upper clamp voltage	ICOMP = 0		5.7			V
VCOMPLO		Lower clamp voltage	ISOURCE = -1mA		2.0			V
V	COMPSH	Linear dynamics upper limit	(1) V = 0V	4.8	5	5.2		V
			VFF
	ICOMP	Max. source current	VCOMP = 3.3 V	320	400	480		µA
RCOMP		Dynamic resistance	VCOMP = 2.6 to 4.8 V		25			kΩ
VCOMPBM		Burst-mode threshold	(1)	2.52	2.65	2.78		V
			(1) MODE/SC = Open	2.7	2.85	3
	Hys	Burst-mode hysteresis			20			mV
ICLAMPL		Lower clamp capability	VCOMP = 2V	-3.5		-1.5		mA
VCOMPOFF		Disable threshold	Voltage falling		1.4			V
Zero current detector/ overvoltage protection
VZCDH		Upper clamp voltage	IZCD = 3 mA	5.4	5.7	6		V
	VZCDL	Lower clamp voltage	IZCD = - 3 mA		-0.4			V
	VZCDA	Arming voltage	(1) positive-going edge	85	100	115		mV
	VZCDT	Triggering voltage	(1) negative-going edge	30	50	70		mV
	IZCD	Internal pull-up	VCOMP < VCOMPSH			-1		µA
			VZCD < 2 V, VCOMP = VCOMPHI	-130	-100	-70
IZCDsrc		Source current capability	VZCD = VZCDL	-3				mA
IZCDsnk		Sink current capability	VZCD = VZCDH	3				mA
TBLANK1		Turn-on inhibit time	After gate-drive going low		2.5			µs
VZCDth		OVP threshold		4.85	5	5.15		V
TBLANK2		OVP strobe delay	After gate-drive going low		2			µs

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L6566A						Electrical characteristics
Table 5. Electrical characteristics (continued)
Symbol		Parameter	Test condition			Min.	Typ.	Max.	Unit
Latched shutdown function
IOTP		Input bias current	VDIS = 0 to VOTP					-1	µA
VOTP		Disable threshold	(1)			4.32	4.5	4.68	V
Thermal shutdown
	Vth	Shutdown threshold					180		° C
	Hys	Hysteresis					40		° C
VCC_PFC function
	Ileak	OFF-state leakage current	VCOMP = 2.5V, VVcc_PFC = 0					1	µA
VVcc -		ON-state voltage dropout	VCOMP = 4V, I VCC_PFC = 10mA				0.15	0.3	V
VVcc_PFC
VCOMPO		Level for pin 6 open and lower	(3)			2.61	2.75	2.89	V
		UVLO off threshold (COMP
			(3) MODE/SC = Open			3.02	3.15	3.28
		voltage falling)
VCOMPL		Level for pin 6 closed and higher	(3)			2.9	3.05	3.2	V
		UVLO off threshold (COMP
			(3) MODE/SC = Open			3.41	3.55	3.69
		voltage rising)
Tdelay		Pin 6 change of state delay	Closed-to-open				10		ms
Mode selection / slope compensation
MODEth		Threshold for QR operation					3		V
SCpk		Ramp peak	RS-COMP = 3 kΩ to GND, GD				1.7		V
		(MODE/SC = Open)	pin high, VCOMP = 5 V
SCvy		Ramp starting value	RS-COMP = 3 kΩ to GND,				0.3		V
		(MODE/SC = Open)	GD pin high
		Ramp voltage	GD pin low				0		V
		(MODE/SC = Open)
		Source capability	VS-COMP = VS-COMPpk			0.8			mA
		(MODE/SC = Open)
Soft-start
ISS1			TJ = 25 °C, VSS < 2 V,			14	20	26
			VCOMP = 4 V
		Charge current							µA
ISS2			TJ = 25 °C, VSS > 2 V,			3.5	5	6.5
			VCOMP =VCOMPHi
ISSdis		Discharge current	VSS > 2 V			3.5	5	6.5	µA
VSSclamp		High saturation voltage	VCOMP = 4 V				2		V
V	SSDIS	Disable level	(1) V	=V	COMPHi	4.85	5	5.15	V
			COMP
VSSLAT		Latch-off level	VCOMP =VCOMPHi				6.4		V

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Electrical characteristics								L6566A
Table 5. Electrical characteristics		(continued)
Symbol	Parameter		Test condition		Min.	Typ.	Max.		Unit
Gate driver
VGDH	Output high voltage		IGDsource = 5 mA, Vcc = 12V		9.8	11			V
VGDL	Output low voltage		IGDsink = 100 mA			0.75			V
Isourcepk	Output source peak current				-0.6				A
Isinkpk	Output sink peak current				0.8				A
tf	Fall time					40			ns
tr	Rise time					50			ns
VGDclamp	Output clamp voltage		IGDsource = 5mA; Vcc = 20V		10	11.3	15		V
	UVLO saturation		Vcc = 0 to Vccon, Isink = 1mA			0.9	1.1		V
1. Parameters tracking one another.
2. See Table 6 on page 41 and Table 7 on page 42
3. The Voltage Feedforward block output is given by: Vcs = Kc (VCOMP 2.5)				KFF VVFF

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