ST L6566A User Manual
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Multi-mode controller for SMPS with PFC front-end
Features
■ Selectable multi-mode operation:
fixed frequency or quasi-resonant
■ On-board 700 V high-voltage start-up
■ Advanced light load management
■ Low quiescent current (< 3 mA)
■ Adaptive UVLO
■ Line feedforward for constant power capability
vs. mains voltage
■ Pulse-by-pulse OCP, shutdown on overload
(latched or autorestart)
■ Transformer saturation detection
■ Switched supply rail for PFC controller
■ Latched or autorestart OVP
■ Brownout protection
■ -600/+800 mA totem pole gate driver with
active pull-down during UVLO
■ SO16N package
L6566A
SO16N
Applications
■ Notebook, TV &LCD monitors adapters
■ High power chargers
■ PDP/LCD TV
■ Consumer appliances, like DVD, VCR, set-top
box
■ IT equipment, games, aux. power supplies
■ Power supplies in excess of 150 W
Figure 1. Block diagram
Vcc_PFC
OSC
MODE/S C
ZCD
AC_OK
VREF
10
1
HV
I
charge
V
CC
5
6
13
12
100 mV
11
16
50 mV
3 V
VOLTAGE
REGULATOR
ADAPTIVE UVLO
UVLO_SHF
OSCILLATOR
+
15 µA
&
OCP2
IC_LATCH
AC_ FAIL
ZERO CURRENT
DETECTOR
OVERVOLTAGE
0.450V
0.485V
SS
14
SOFT-START
&
FAULT MNGT
Ref er ence
voltages
Internal supply
UVL O
+
MODE SELECTIO N
&
TURN-ON LOGIC
PROTECTION
-
+
August 2007 Rev 1 1/51
COMP
915
TIME
OUT
LOW CLA MP
& DISABLE
Vth
V
CC
400 uA
+
-
5.7V
BURST-MODE
TIME
OVPL
OUT
OVP
LATCH
IC_LATCH
AC_FAIL
UVLO
DISABLE
VFF
OFF2
LINE VOLTAGE
FEEDFORWARD
+-
OCPPWM
R
Q
S
OFF2
OVP
+-
V
CC
+-
Hiccup-mode
OCP logic
OCP2
DRIVER
7.7V
1 mA
GND
6.4V
3
1.5 V
OVPL
+
Q
V
CC
14V
LEB
CS
7
4
GD
4.5V
+
DIS
8
www.st.com
51
Contents L6566A
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 High-voltage start-up generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2 Zero current detection and triggering block; oscillator block . . . . . . . . . . 21
5.3 Burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 24
5.4 Adaptive UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.5 PWM control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.6 PWM comparator, PWM latch and voltage feedforward blocks . . . . . . . . 27
5.7 Hiccup-mode OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.8 PFC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.9 Latched disable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.10 Soft-start and delayed latched shutdown upon overcurrent . . . . . . . . . . . 33
5.11 OVP block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.12 Brownout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.13 Slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.14 Summary of L6566A power management functions . . . . . . . . . . . . . . . . 41
2/51
L6566A Contents
6 Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3/51
List of tables L6566A
List of tables
Table 2. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. L6566A light load management features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 7. L6566A protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 8. External circuits that determine IC behavior upon OVP and OCP . . . . . . . . . . . . . . . . . . . 45
Table 9. SO16N mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 10. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4/51
L6566A List of figures
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Typical system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Pin connection (through top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Multi-mode operation with QR option active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5. High-voltage start-up generator: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 6. Timing diagram: normal power-up and power-down sequences . . . . . . . . . . . . . . . . . . . . 19
Figure 7. Timing diagram showing short-circuit behavior (SS pin clamped at 5V). . . . . . . . . . . . . . . 20
Figure 8. Zero current detection block, triggering block, oscillator block and related logic . . . . . . . . 20
Figure 9. Drain ringing cycle skipping as the load is gradually reduced . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. Operation of ZCD, triggering and Oscillator blocks (QR option active). . . . . . . . . . . . . . . . 23
Figure 11. Load-dependent operating modes: timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. Addition of an offset to the current sense lowers the burst-mode operation threshold. . . . 25
Figure 13. Adaptive UVLO block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14. Possible feedback configurations that can be used with the L6566A. . . . . . . . . . . . . . . . . 26
Figure 15. Externally controlled burst-mode operation by driving pin COMP: timing diagram. . . . . . . 27
Figure 16. Typical power capability change vs input voltage in QR flyback converters . . . . . . . . . . . 28
Figure 17. Left: Overcurrent setpoint vs. VFF voltage; right: Line Feedforward function block . . . . . . 29
Figure 18. Hiccup-mode OCP: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 19. Possible interfaces between the L6566A and a PFC controller . . . . . . . . . . . . . . . . . . . . . 32
Figure 20. Operation after latched disable activation: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 21. Soft-start pin operation under different operating conditions and settings . . . . . . . . . . . . . 34
Figure 22. OVP Function: internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 23. OVP function: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 24. Maximum allowed duty cycle vs. switching frequency for correct OVP detection. . . . . . . . 37
Figure 25. Brownout protection: internal block diagram and timing diagram . . . . . . . . . . . . . . . . . . . . 38
Figure 26. Ac voltage sensing with the L6566A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 27. Slope compensation waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 28. Typical low-cost application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 29. Typical full-feature application schematic (QR operation) . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 30. Typical full-feature application schematic (FF operation) . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 31. Frequency foldback at light load (FF operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 32. Latched shutdown upon mains overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5/51
Description L6566A
1 Description
The L6566A is an extremely versatile current-mode primary controller IC specifically
designed for high-performance offline flyback converters operated from front-end Power
Factor Correction (PFC) stages in applications supposed to comply with EN61000-3-2 or
JEITA-MITI regulations.
Both Fixed-frequency (FF) and Quasi-resonant (QR) operation are supported. The user can
pick either of the two depending on application needs.
The device features an externally programmable oscillator: it defines converter's switching
frequency in FF mode and the maximum allowed switching frequency in QR mode.
When FF operation is selected, the IC works like a standard current-mode controller with a
maximum duty cycle limited at 70% min.
QR operation, when selected, occurs and is achieved through a transformer
demagnetization sensing input that triggers MOSFET's turn-on. Under some conditions,
ZVS (Zero-voltage Switching) can be achieved. Converter's power capability rise with the
input voltage is compensated by line voltage feedforward. At medium and light load, as the
QR operating frequency equals the oscillator frequency, a function (valley skipping) is
activated to prevent further frequency rise and keep the operation as close to ZVS as
possible.
With either FF or QR operation, at very light load the IC enters a controlled burst-mode
operation that, along with the built-in non-dissipative high-voltage start-up circuit and a
reduced quiescent current, helps keep low the consumption from the mains and meet
energy saving recommendations.
To allow meeting them in two-stage power-factor-corrected systems as well, the L6566A
provides an interface with the PFC controller that enables to turn off the pre-regulator at light
load.
An innovative adaptive UVLO helps minimize the issues related to the fluctuations of the
self-supply voltage due to transformer's parasitics.
The protection functions included in this device are: not-latched input undervoltage
(brownout), output OVP (auto-restart or latch-mode selectable), a first-level OCP with
delayed shutdown to protect the system during overload or short circuit conditions (autorestart or latch-mode selectable) and a second-level OCP that is invoked when the
transformer saturates or the secondary diode fails short. A latched disable input allows easy
implementation of OTP with an external NTC, while an internal thermal shutdown prevents
IC overheating.
Programmable soft-start, leading-edge blanking on the current sense input for greater noise
immunity, slope compensation (in FF mode only), and a shutdown function for externally
controlled burst-mode operation or remote ON/OFF control complete the equipment of this
device.
6/51
L6566A Description
Figure 2. Typical system block diagram
PFC PRE-REGULATOR
Rectified
Mains
Voltage
L6563/A
PFC
FLYBACK DC-DC CONVERTER
PWM/QR controller is turned off in case of PFC's
anomalous operation, for safety
L6566A
PFC is automatically turned off at light
load to ease compliance with
energy saving specifications.
V outdc
7/51
Pin settings L6566A
2 Pin settings
2.1 Connections
Figure 3. Pin connection (through top view)
1
HVS AC_OK
HVS AC_OK
N.C.
N.C.
GND
GND
GD
GD
Vcc
Vcc
Vcc_PFC
Vcc_PFC
CS
CS
DIS
DIS
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
VFF
VFF
SS
SS
OSC
OSC
MODE/SC
MODE/SC
ZCD
ZCD
VREF
VREF
COMP
COMP
2.2 Pin description
Table 2. Pin functions
N° Pin Function
High-voltage start-up. The pin, able to withstand 700V, is to be tied directly to the
rectified mains voltage. A 1 mA internal current source charges the capacitor
connected between Vcc pin (5) and GND pin (3) until the voltage on the Vcc pin
reaches the turn-on threshold, then it is shut down. Normally, the generator is re-
1HVS
2N.C.
3GND
4GD
enabled when the Vcc voltage falls below 5V to ensure a low power throughput
during short circuit. Otherwise, when a latched protection is tripped the generator is
re-enabled 0.5V below the turn-on threshold, to keep the latch supplied; or, when
the IC is turned off by pin COMP (9) pulled low the generator is active just below
the UVLO threshold to allow a faster restart.
Not internally connected. Provision for clearance on the PCB to meet safety
requirements.
Ground. Current return for both the signal part of the IC and the gate drive. All of
the ground connections of the bias components should be tied to a track going to
this pin and kept separate from any pulsed current return.
Gate driver output. The totem pole output stage is able to drive power MOSFET’s
and IGBT’s with a peak current capability of 800 mA source/sink.
8/51
L6566A Pin settings
Table 2. Pin functions (continued)
N° Pin Function
Supply Voltage of both the signal part of the IC and the gate driver. The internal
high voltage generator charges an electrolytic capacitor connected between this
pin and GND (pin 3) as long as the voltage on the pin is below the turn-on threshold
5Vcc
6Vcc_PFC
7CS
of the IC, after that it is disabled and the chip is turned on. The IC is disabled as the
voltage on the pin falls below the UVLO threshold. This threshold is reduced at light
load to counteract the natural reduction of the self-supply voltage. Sometimes a
small bypass capacitor (0.1 µF typ.) to GND might be useful to get a clean bias
voltage for the signal part of the IC.
Supply pin output. This pin is intended for supplying the PFC controller IC in
systems comprising a PFC pre-regulator or other compatible circuitry. It is internally
connected to the Vcc pin (5) via a controlled switch. The switch is closed as the IC
starts up and opens when the voltage at pin COMP is lower than a threshold (light
load), whenever the IC is shut down (either latched or not) and during UVLO. If not
used, the pin will be left floating.
Input to the PWM comparator. The current flowing in the MOSFET is sensed
through a resistor, the resulting voltage is applied to this pin and compared with an
internal reference to determine MOSFET’s turn-off. The pin is equipped with 150 ns
min. blanking time after the gate-drive output goes high for improved noise
immunity. A second comparison level located at 1.5V latches the device off and
reduces its consumption in case of transformer saturation or secondary diode short
circuit. The information is latched until the voltage on the Vcc pin (5) goes below
the UVLO threshold, hence resulting in intermittent operation. A logic circuit
improves sensitivity to temporary disturbances.
8DIS
9COMP
10 VREF
IC’s latched disable input. Internally the pin connects a comparator that, when the
voltage on the pin exceeds 4.5V, latches off the IC and brings its consumption to a
lower value. The latch is cleared as the voltage on the Vcc pin (5) goes below the
UVLO threshold, but the HV generator keeps the Vcc voltage high (see pin 1
description). It is then necessary to recycle the input power to restart the IC. For a
quick restart pull pin 16 (AC_OK) below the disable threshold (see pin 16
description).Bypass the pin with a capacitor to GND (pin 3) to reduce noise pick-up.
Ground the pin if the function is not used.
Control input for loop regulation. The pin will be driven by the phototransistor
(emitter-grounded) of an optocoupler to modulate its voltage by modulating the
current sunk. A capacitor placed between the pin and GND (3), as close to the IC
as possible to reduce noise pick-up, sets a pole in the output-to-control transfer
function. The dynamics of the pin is in the 2.5 to 5V range. A voltage below an
internally defined threshold activates burst-mode operation. The voltage at the pin
is bottom-clamped at about 2V. If the clamp is externally overridden and the voltage
is pulled below 1.4V the IC will shut down.
An internal generator furnishes an accurate voltage reference (5V±2%) that can be
used to supply few mA to an external circuit. A small film capacitor (0.1 µF typ.),
connected between this pin and GND (3), is recommended to ensure the stability of
the generator and to prevent noise from affecting the reference. This reference is
internally monitored by a separate auxiliary reference and any failure or drift will
cause the IC to latch off.
9/51
Pin settings L6566A
Table 2. Pin functions (continued)
N° Pin Function
Transformer demagnetization sensing input for quasi-resonant operation and OVP
input. The pin is externally connected to the transformer’s auxiliary winding through
a resistor divider. A negative-going edge triggers MOSFET’s turn-on if QR mode is
11 ZCD
12 MODE/SC
13 OSC
14 SS
15 VFF
selected.
A voltage exceeding 5V shuts the IC down and brings its consumption to a lower
value (OVP). Latch-off or auto-restart mode is selectable externally. This function is
strobed and digitally filtered to increase noise immunity.
Operating mode selection. If the pin is connected to the VREF pin (7) Quasiresonant operation is selected and the oscillator (pin 13, OSC) determines the
maximum allowed operating frequency.
Fixed-frequency operation is selected if the pin is not tied to VREF, in which case
the oscillator determines the actual operating frequency, the maximum allowed
duty cycle is set at 70% min. and the pin delivers a voltage ramp synchronized to
the oscillator when the gate-drive output is high; the voltage delivered is zero while
the gate-drive output is low. The pin is to be connected to pin CS (7) via a resistor
for slope compensation.
Oscillator pin. The pin is an accurate 1 V voltage source, and a resistor connected
from the pin to GND (pin 3) defines a current. This current is internally used to set
the oscillator frequency that defines the maximum allowed switching frequency of
the L6566A, if working in QR mode, or the operating switching frequency if working
in FF mode.
Soft-start current source. At start-up a capacitor Css between this pin and GND
(pin 3) is charged with an internal current generator. During the ramp, the internal
reference clamp on the current sense pin (7, CS) rises linearly starting from zero to
its final value, thus causing the duty cycle to increase progressively starting from
zero as well. During soft-start the Adaptive UVLO function and all functions
monitoring pin COMP are disabled. The soft-start capacitor is discharged whenever
the supply voltage of the IC falls below the UVLO threshold. The same capacitor is
used to delay IC’s shutdown (latch-off or auto-restart mode selectable) after
detecting an overload condition (OLP).
Line voltage feedforward input. The information on the converter’s input voltage is
fed into the pin through a resistor divider and is used to change the setpoint of the
pulse-by-pulse current limitation (the higher the voltage, the lower the setpoint).
The linear dynamics of the pin ranges from 0 to 3V. A voltage higher than 3V makes
the IC stop switching. If feedforward is not desired, tie the pin to GND (pin 3)
directly if a latch-mode OVP is not required (see pin 11, ZCD) or through a resistor
if a latch-mode OVP is required. Bypass the pin with a capacitor to GND (pin 3) to
reduce noise pick-up.
Brownout protection input. A voltage below 0.45V shuts down (not latched) the IC,
lowers its consumption, opens the Vcc_PFC pin (6), and clears the latch set by
latched protections (DIS>4.5V, SS>6.4V, VFF>6.4V). IC’s operation is re-enabled
16 AC_OK
10/51
as the voltage exceeds 0.45V. The comparator is provided with current hysteresis:
an internal 15 µA current generator is ON as long as the voltage on the pin is below
0.45V and is OFF if this value is exceeded. Bypass the pin with a capacitor to GND
(pin 3) to reduce noise pick-up. Tie to Vcc with a 220 to 680 kΩ resistor if the
function is not used.
L6566A Electrical data
3 Electrical data
3.1 Maximum rating
Table 3. Absolute maximum ratings
Symbol Pin Parameter Value Unit
V
HVS
I
HVS
V
CC
V
Vcc_PFC
I
Vcc_PFC
V
max
V
max
I
ZCD
V
MODE/SC
V
OSC
P
TOT
1 Voltage range (referred to ground) -0.3 to 700 V
1 Start-up current Self-limited
5 IC supply voltage (Icc = 20 mA) Self-limited
6 Voltage range -0.3 to Vcc V
6 Max. source current (continuous) 30 mA
7, 8, 10, 14 Analog inputs & outputs -0.3 to 7 V
9, 15, 16 Maximum pin voltage (Ipin ≤ 1mA) Self-limited
11 Zero current detector max. current ±5 mA
12 Voltage range -0.3 to 5 V
13 Voltage range -0.3 to 3.3 V
Power dissipation @TA = 50°C
0.75 W
3.2 Thermal data
Table 4. Thermal data
Symbol Parameter Value Unit
R
thJA
T
Thermal resistance junction to ambient 120 °C/W
Junction operating temperature range -40 to 150 °C
J
11/51
Electrical characteristics L6566A
4 Electrical characteristics
(TJ = -25 to 125°C, VCC = 12, CO = 1 nF; MODE/SC=V
, RT = 20 kΩ from OSC to GND,
REF
unless otherwise specified).
Table 5. Electrical characteristics
Symbol Parameter Test condition Min. Typ. Max. Unit
Supply voltage
V
Vcc Operating range after turn-on
V
Vcc
Vcc
Turn-on threshold
On
Turn-off threshold
Off
Hys Hysteresis
V
Zener voltage Icc = 20 mA, IC disabled 23 25 27 V
Z
(1)
(1)
(1)
V
Supply current
I
start-up
I
q
Start-up current Before turn-on, Vcc = 13 V 200 250 µA
Quiescent current
After turn-on, V
Icc Operating supply current MODE/SC open 4 4.6 mA
I
qdis
Quiescent current
IC disabled
IC latched off 440 500
COMP
COMP
V
COMP
V
COMP
COMP
> V
= V
> V
COMPL
COMPO
> V
= V
COMPL
(2)
COMPL
COMPO
ZCD
= V
CS
= 1V
10.6 23
823
13 14 15 V
9.4 10 10.6
7.2 7.6 8.0
4V
2.6 2.8 mA
330 2500
V
V
µA
High-voltage start-up generator
I
V
HV
V
HVstart
I
charge
I
HV, ON
I
HV, OFF
Breakdown voltage
Start voltage
Vcc charge current
ON-state current
OFF-state leakage current
< 100 µA
HV
< 100 µA
I
Vcc
V
HV
V
HV
V
HV
V
HV
> V
Hvstart
> V
Hvstart
> V
Hvstart
= 400 V
Vcc falling 4.4 5 5.6
(1)
V
CCrestart
Vcc restart voltage
IC latched off
(1)
Disabled by
COMP
< V
V
12/51
, Vcc > 3V
, Vcc > 3V
, Vcc = 0
COMPOFF
700 V
65 80 100 V
0.55 0.85 1 mA
1.6
mA
0.8
40 µA
12.5 13.5 14.5
V
9.4 10 10.6
L6566A Electrical characteristics
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
Reference voltage
V
V
I
REF
REF
REF
Output voltage
To t al va r i at io n
Short circuit current
Sink capability in UVLO Vcc = 6V; Isink = 0.5 mA 0.2 0.5 V
V
OV
Overvoltage threshold 5.3 5.7 V
Internal oscillator
V
D
f
sw
OSC
max
Oscillation frequency
Voltage reference
Maximum duty cycle
Brownout protection
Vth Threshold voltage
I
Hys
V
AC_OK_CL
Current Hysteresis
Clamp level
(1)
TJ = 25 °C; I
I
= 1 to 5 mA,
REF
REF
Vcc= 10.6 to 23 V
= 0
V
REF
= 1 mA
4.95 5 5.05 V
4.9 5.1 V
10 30 mA
Operating range 10 300
TJ = 25°C, V
MODE/SC = Open
Vcc=12 to 23 V, V
MODE/SC = Open
(3)
MODE/SC = Open,
V
= 5 V
COMP
Voltage falling (turn-off)
Voltage rising (turn-on)
Vcc > 5V, V
(1)
I
AC_OK
ZCD
= 0.3V
VFF
= 100µA
= 0,
ZCD
= 0,
95 100 105
93 100 107
0.97 1 1.03 V
70 75 %
0.432 0.450 0.468 V
0.452 0.458 0.518 V
12 15 18 µA
33.153.3 V
kHz
Line voltage feedforward
I
VFF
V
VFF
V
OFF
V
VFFlatch
Kc
K
FF
Input bias current
Linear operation range 0 to 3 V
IC disable voltage 3 3.15 3.3 V
Latch-off/clamp level
Control voltage gain
Feedforward gain
(3)
(3)
V
V
V
V
V
VFF
ZCD
ZCD
VFF
VFF
= 0 to 3 V, V
> V
ZCDth
> V
ZCDth
= 1 V, V
= 1 V, V
COMP
COMP
ZCD
< V
= 4 V
= 4 V
ZCDth
-1 µA
-0.7 -1 mA
6.4 V
0.4 V/V
0.04 V/V
13/51
Electrical characteristics L6566A
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
Current sense comparator
V
= 0
CS
V
V
V
(1)
I
I
(1)
V
(1)
(1)
V
= V
COMP
COMP
COMP
COMP
SOURCE
V
COMP
COMP
COMPHI
= V
COMPHI
= V
COMPHI
= 0
= -1mA
= 0V
VFF
= 3.3 V
= 2.6 to 4.8 V
MODE/SC = Open
= 2V
COMP
, V
, V
, V
VFF
VFF
VFF
= 0V
= 1.5V
= 3.0V
-1 µA
0.92 1 1.08
0.45 0.5 0.55
00.1
1.4 1.5 1.6 V
5.7 V
2.0 V
4.8 5 5.2 V
320 400 480 µA
25 kΩ
2.52 2.65 2.78
2.7 2.85 3
-3.5 -1.5 mA
V
V
td
V
V
I
CS
t
LEB
(H-L)
CSx
CSdis
Input bias current
Leading edge blanking 150 250 300 ns
Delay to output 100 ns
Overcurrent setpoint
Hiccup-mode OCP level
PWM control
V
COMPHI
V
COMPLO
V
COMPSH
I
COMP
R
COMP
V
COMPBM
Upper clamp voltage
Lower clamp voltage
Linear dynamics upper limit
Max. source current V
Dynamic resistance
Burst-mode threshold
Hys Burst-mode hysteresis 20 mV
I
CLAMPL
V
COMPOFF
Lower clamp capability
Disable threshold Voltage falling 1.4 V
Zero current detector/ overvoltage protection
I
V
ZCDH
V
ZCDL
V
ZCDA
V
ZCDT
I
ZCD
I
ZCDsrc
I
ZCDsnk
T
BLANK1
V
ZCDth
T
BLANK2
Upper clamp voltage
Lower clamp voltage
Arming voltage
Triggering voltage
Internal pull-up
Source current capability
Sink current capability
Turn-on inhibit time After gate-drive going low 2.5 µs
OVP threshold 4.85 5 5.15 V
OVP strobe delay After gate-drive going low 2 µs
= 3 mA
ZCD
= - 3 mA
I
ZCD
(1)
positive-going edge
(1)
negative-going edge
V
V
V
V
< V
COMP
ZCD < 2 V, V
= V
ZCD
= V
ZCD
14/51
COMPSH
ZCDL
ZCDH
COMP
= V
COMPHI
5.4 5.7 6 V
-0.4 V
85 100 115 mV
30 50 70 mV
-1
µA
-130 -100 -70
-3 mA
3mA
L6566A Electrical characteristics
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
Latched shutdown function
V
I
V
OTP
OTP
Input bias current
Disable threshold
Thermal shutdown
Vth Shutdown threshold 180 °C
Hys Hysteresis 40 °C
VCC_PFC function
DIS
(1)
= 0 to V
OTP
-1 µA
4.32 4.5 4.68 V
I
leak
V
Vcc
V
Vcc_PFC
OFF-state leakage current V
-
ON-state voltage dropout V
Level for pin 6 open and lower
V
COMPO
UVLO off threshold (COMP
voltage falling)
Level for pin 6 closed and higher
V
COMPL
UVLO off threshold (COMP
voltage rising)
T
delay
Pin 6 change of state delay Closed-to-open 10 ms
Mode selection / slope compensation
MODE
SC
SC
Threshold for QR operation 3 V
th
Ramp peak
pk
(MODE/SC = Open)
Ramp starting value
vy
(MODE/SC = Open)
Ramp voltage
(MODE/SC = Open)
Source capability
(MODE/SC = Open)
= 2.5V, V
COMP
= 4V, I
COMP
(3)
(3)
MODE/SC = Open
(3)
(3)
MODE/SC = Open
R
S-COMP
pin high, V
R
S-COMP
VCC_PFC
= 3 kΩ to GND, GD
COMP
= 3 kΩ to GND,
GD pin high
Vcc_PFC
= 5 V
= 0
= 10mA
1µA
0.15 0.3 V
2.61 2.75 2.89 V
3.02 3.15 3.28
2.93.053.2 V
3.41 3.55 3.69
1.7 V
0.3 V
GD pin low 0 V
V
S-COMP = VS-COMPpk
0.8 mA
Soft-start
I
SS1
I
SS2
I
SSdis
V
SSclamp
V
SSDIS
V
SSLAT
Charge current
Discharge current
High saturation voltage
Disable level
Latch-off level
= 25 °C, VSS < 2 V,
T
J
= 4 V
V
COMP
TJ = 25 °C, VSS > 2 V,
=V
V
COMP
V
SS
V
COMP
(1)
V
COMP
V
> 2 V
= 4 V
COMP
=V
COMPHi
=V
COMPHi
COMPHi
15/51
14 20 26
µA
3.5 5 6.5
3.5 5 6.5 µA
2V
4.85 5 5.15 V
6.4 V
Electrical characteristics L6566A
−
−
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
Gate driver
V
GDH
V
GDL
I
sourcepk
I
sinkpk
t
t
V
GDclamp
Output high voltage
Output low voltage
Output source peak current -0.6 A
Output sink peak current 0.8 A
Fall time 40 ns
f
Rise time 50 ns
r
Output clamp voltage
UVLO saturation Vcc = 0 to V
1. Parameters tracking one another.
2. See Table 6 on page 41 and Table 7 on page 42
3. The Voltage Feedforward block output is given by:
I
GDsource
I
GDsink
I
GDsource
= 5 mA, Vcc = 12V
= 100 mA
= 5mA; Vcc = 20V
ccon, Isink = 1mA 0.9 1.1 V
()
=
9.8 11 V
0.75 V
10 11.3 15 V
VK5.2VKc V
VFFFFCOMPcs
16/51
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