ST L6564T User Manual

L6564T

10-pin transition-mode PFC controller

Features

■Guaranteed for extreme temperature range (outdoor)

■Fast “bi-directional” input voltage feedforward (1/V2 correction)

■Accurate adjustable output overvoltage protection

■Protection against feedback loop disconnection (latched shutdown)

■Inductor saturation protection

■AC brownout detection

■Low (≤100 µA) startup current

■6 mA max. operating bias current

■1% (@ TJ = 25 °C) internal reference voltage

■-600/+800 mA totem pole gate driver with active pull-down during UVLO

■SSOP10 package

SSOP10

Applications

■PFC pre-regulators for:

–High-end AC-DC adapter/charger

–Desktop PC, server, web server

–IEC61000-3-2 or JEITA-MITI compliant SMPS

■SMPS for LED luminaires

Figure 1. Block diagram

					=&'										9FF
					=HUR &XUUHQW			9ROWDJH		92/7$*(
							UHIHUHQFHV					89/2
	9			'LVDEOH	'HWHFWRU					5(*8/$725
	9				9		,QWHUQDO 6XSSO\ %XV
3)&B2.
	9				9							89/2
				293	/B293
	9
									6	4
															*'
	9								5				'5,9(5
													&/$03
									67$57(5		6WDUWHU
											2))
&203												',6$%/(
										'LVDEOH			4	6	/B293
,19							4	/(%			293
									21 2)) &RQWURO					5	89/2
	9
				(UURU$PSOLILHU
08/7
															*1'
					9
						08/7,3/,(5
	,GHDO UHFWLILHU														&6
21 2)) &RQWURO				9									'LVDEOH
				9					0$,16 '523		9
									'(7(&725
					9))

!-V

January 2012

Doc ID 022671 Rev 1

1/33

www.st.com

Contents	L6564T

Contents

1	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 5
2	Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
	2.1	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
	2.2	Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
3	Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		7
4	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		9
5	Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
6	Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		18
	6.1	Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	6.2	Feedback failure protection (FFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	6.3	Voltage feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	6.4	THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
	6.5	Inductor saturation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
	6.6	Power management/housekeeping functions . . . . . . . . . . . . . . . . . . . . . .	25
7	Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		27
8	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		29
9	Ordering codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		31
10	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		32

2/33	Doc ID 022671 Rev 1

L6564T	List of tables

List of tables

Table 1. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 5. Summary of L6564 idle states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 6. SSO10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 7. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Doc ID 022671 Rev 1

3/33

List of figures	L6564T

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. IC consumption vs. VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 4. IC consumption vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. Vcc Zener voltage vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. Startup and UVLO vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 7. Feedback reference vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 8. E/A output clamp levels vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 9. UVLO saturation vs. TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 10. OVP levels vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 11. Inductor saturation threshold vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 12. Vcs clamp vs. TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 13. ZCD sink/source capability vs. TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 14. ZCD clamp level vs. TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 15. R discharge vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 16. Line drop detection threshold vs. TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 17. VMULTpk - VVFF dropout vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 18. PFC_OK threshold vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 19. PFC_OK FFD threshold vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 20. Multiplier characteristics @ VFF = 1 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 21. Multiplier characteristics @ VFF = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 22. Multiplier gain vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 23. Gate drive clamp vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 24. Gate drive output saturation vs. TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 25. Delay to output vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 26. Startup timer period vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 27. Output voltage setting, OVP and FFP functions: internal block diagram . . . . . . . . . . . . . . 18 Figure 28. Voltage feedforward: squarer/divider (1/V2) block diagram and transfer characteristic . . 20 Figure 29. RFF·CFF as a function of 3rd harmonic distortion introduced in the input current . . . . . . . 21 Figure 30. THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 31. THD optimization: standard TM PFC controller (left side) and L6564T (right side) . . . . . . 23 Figure 32. Effect of boost inductor saturation on the MOSFET current and detection method . . . . . . 24 Figure 33. Interface circuits that let DC-DC converter's controller IC disable the L6564T. . . . . . . . . . 25 Figure 34. Demonstration board EVL6564-100W, wide-range mains: electrical schematic . . . . . . . . 27 Figure 35. L6564 100 W TM PFC: compliance with EN61000-3-2 standard . . . . . . . . . . . . . . . . . . . . 28 Figure 36. L6564 100 W TM PFC: compliance with JEITA-MITI standard . . . . . . . . . . . . . . . . . . . . . 28 Figure 37. L6564 100 W TM PFC: input current waveform @230-50 Hz - 100 W load. . . . . . . . . . . . 28 Figure 38. L6564 100W TM PFC: input current waveform @100 V-50 Hz - 100 W load . . . . . . . . . . 28 Figure 39. SSO10 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4/33	Doc ID 022671 Rev 1

L6564T	Description

1 Description

The L6564T is a current-mode PFC controller operating in transition mode (TM) and represents the compact version of the L6563S as it embeds the same driver, reference and control stages in a very compact 10-pin SO package.

The highly linear multiplier, along with a special correction circuit that reduces crossover distortion of the mains current, allows wide-range-mains operation with an extremely low THD even over a large load range.

The output voltage is controlled by means of a voltage-mode error amplifier and an accurate (1% @TJ = 25 °C) internal voltage reference. The loop stability is optimized by the voltage feedforward function (1/V2 correction), which in this IC uses a proprietary technique that also considerably improves line transient response in case of both mains drops and surges (“bidirectional”).

In addition to overvoltage protection able to control the output voltage during transient conditions, the IC also provides protection against feedback loop failures or erroneous settings. Other on-board protection functions allow brownout conditions and boost inductor saturation to be safely handled.

The totem-pole output stage, capable of a 600 mA source and 800 mA sink current, is suitable for a high power MOSFET or IGBT drive. This, combined with the other features and the possibility to operate with ST's proprietary fixed-off-time control, makes the device an excellent solution for SMPS up to 400 W that requires compliance with EN61000-3-2 and JEITA-MITI standards.

Doc ID 022671 Rev 1

5/33

Maximum ratings	L6564T

2 Maximum ratings

2.1Absolute maximum ratings

	Table 1.	Absolute maximum ratings
	Symbol	Pin	Parameter	Value	Unit
	Vcc	10	IC supply voltage (Icc ≤20 mA)	Self-limited	V
	---	1, 3, 6	Max. pin voltage (Ipin ≤1 mA)	Self-limited	V
	---	2, 4, 5	Analog inputs and outputs	-0.3 to 8	V
	IZCD	7	Zero current detector max. current	-10 (source)	mA
				10 (sink)
	VFF pin	5	Maximum withstanding voltage range	+/- 1750	V
			test condition: CDF-AEC-Q100-002
		1 to 4
	Other pins		“human body model”	+/- 2000	V
		6 to 10
			Acceptance criteria: “normal performance”

2.2Thermal data

Table 2.	Thermal data
Symbol	Parameter	Value	Unit
RthJA	Max. thermal resistance, junction-to-ambient	120	°C/W
Ptot	Power dissipation @TA = 50 °C	0.75	W
TJ	Junction temperature operating range	-40 to 150	°C
Tstg	Storage temperature	-55 to 150	°C

6/33	Doc ID 022671 Rev 1

	L6564T										Pin connection
	3			Pin connection
				Figure 2. Pin connection
					,19						9FF
					&203						*'
					08/7						*1'
					&6						=&'
					9))						3)&B2.
											!-V
	Table 3.			Pin description
	n°	Name						Function
					Inverting input of the error amplifier. The information on the output voltage of the PFC pre-
	1		INV		regulator is fed into the pin through a resistor divider.
					The pin normally features high impedance.
					Output of the error amplifier. A compensation network is placed between this pin and INV (pin
	2	COMP			1) to achieve stability of the voltage control loop and ensure high power factor and low THD.
					To avoid uncontrolled rise of the output voltage at zero load, when the voltage on the pin falls
					below 2.4 V the gate driver output is inhibited (burst-mode operation).
					Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor
	3	MULT			divider and provides the sinusoidal reference to the current loop. The voltage on this pin is used
					also to derive the information on the RMS mains voltage.
					Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor,
					the resulting voltage is applied to this pin and compared with an internal reference to determine
	4		CS		MOSFET’s turn-off.
					A second comparison level at 1.7 V detects abnormal currents (e.g. due to boost inductor
					saturation) and, on this occurrence, activates a safety procedure that temporarily stops the
					converter and limits the stress of the power components.
					Second input to the multiplier for 1/V2 function. A capacitor and a parallel resistor must be
					connected from the pin to GND. They complete the internal peak-holding circuit that derives the
					information on the RMS mains voltage. The voltage at this pin, a DC level equal to the peak
					voltage on pin MULT (3), compensates the control loop gain dependence on the mains voltage.
	5		VFF		Never connect the pin directly to GND but with a resistor ranging from 100 K ohm (minimum) to
					2 M ohm (maximum). This pin is internally connected to a comparator in order to provide the
					brownout (AC mains undervoltage) protection. A voltage below 0.8 V shuts down (not latched)
					the IC and brings its consumption to a considerably lower level. The IC restarts as the voltage
					at the pin goes above 0.88 V.

Doc ID 022671 Rev 1

7/33

Pin connection			L6564T
Table 3.		Pin description (continued)
n°	Name		Function
			PFC pre-regulator output voltage monitoring/disable function. This pin senses the output
			voltage of the PFC pre-regulator through a resistor divider and is used for protection purposes.
			If the voltage on the pin exceeds 2.5 V the IC stops switching and restarts as the voltage on the
			pin falls below 2.4 V. However, if at the same time the voltage of the INV pin falls below 1.66 V,
6	PFC_OK		a feedback failure is assumed. In this case the device is latched off. Normal operation can be
			resumed only by cycling Vcc. bringing its value lower than 6 V before moving up to the turn-on
			threshold.
			If the voltage on this pin is brought below 0.23 V the IC is shut down. To restart the IC the
			voltage on the pin must go above 0.27 V. This can be used as a remote on/off control input.
7		ZCD	Boost inductor’s demagnetization sensing input for transition-mode operation. A negative-going
			edge triggers MOSFET’s turn-on.
8		GND	Ground. Current return for both the signal part of the IC and the gate driver.
			Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s
9		GD	with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is
			clamped at about 12 V to avoid excessive gate voltages.
			Supply voltage of both the signal part of the IC and the gate driver. Sometimes a small bypass
10		Vcc	capacitor (0.1 µF typ.) to GND might be useful to get a clean bias voltage for the signal part of
			the IC.

8/33	Doc ID 022671 Rev 1

L6564T	Electrical characteristics

4 Electrical characteristics

TJ = -40 to 125 °C, VCC = 12 V, CO = 1 nF between pin GD and GND, CFF = 1 µF and RFF = 1 MΩ between pin VFF and GND; unless otherwise specified.

Table 4.	Electrical characteristics
Symbol	Parameter	Test condition	Min.	Typ.	Max.	Unit
Supply voltage
Vcc	Operating range	After turn-on	10.3		22.5	V
VccOn	Turn-on threshold	(1)	11	12	13.2	V
VccOff	Turn-off threshold	(1)	8.7	9.5	10.5	V
Vccrestart	Vcc for resuming from latch	OVP latched	5	6	7	V
Hys	Hysteresis		2.3		2.7	V
VZ	Zener voltage	Icc = 20 mA	22.5	25	28	V
Supply current
Istart-up	Startup current	Before turn-on, Vcc=10 V		90	180	µA
Iq	Quiescent current	After turn-on, VMULT = 1 V		4	5.5	mA
ICC	Operating supply current	@ 70 kHz		5	6.0	mA
		VPFC_OK> VPFC_OK_S AND VINV <		180	320	µA
Iqdis	Idle state quiescent current	VFFD
		VPFC_OK<VPFC_OK_D		1.5	2.5	µA
Iq	Quiescent current	VPFC_OK>VPFC_OK_S OR		2.2	3.2	µA
		VCOMP<2.3V
Multiplier input
IMULT	Input bias current	VMULT = 0 to 3 V		-0.2	-1	µA
VMULT	Linear operation range		0 to 3			V
VCLAMP	Internal clamp level	IMULT = 1 mA	9	9.5		V
∆Vcs	Output max. slope	VMULT = 0 to 0.4 V, VVFF = 1 V	1.33	1.66		V/V
∆VMULT		VCOMP = upper clamp
KM	Gain (2)	VMULT = 1 V, VCOMP= 4 V	0.375	0.45	0.525	V
Error amplifier
VINV	Voltage feedback input threshold	TJ = 25 °C	2.475	2.5	2.525	V
		10.3 V < Vcc < 22.5 V (3)	2.45		2.55
	Line regulation	Vcc = 10.3 V to 22.5 V		2	5	mV
IINV	Input bias current	VINV = 0 to 4 V		-0.2	-1	µA
VINVCLAMP	Internal clamp level	IINV = 1 mA	8	9		V
Gv	Voltage gain	Open loop	60	80		dB

Doc ID 022671 Rev 1

9/33

Electrical characteristics							L6564T
Table 4.		Electrical characteristics	(continued)
	Symbol	Parameter		Test condition	Min.	Typ.	Max.	Unit
	GB	Gain-bandwidth product				1		MHz
	ICOMP	Source current		VCOMP = 4 V, VINV = 2.4 V	1.5	4		mA
		Sink current		VCOMP = 4 V, VINV = 2.6 V	2	4.5		mA
		Upper clamp voltage		ISOURCE = 0.5 mA	5.7	6.2	6.7
	VCOMP	Burst-mode voltage		(3)	2.3	2.4	2.5	V
		Lower clamp voltage		ISINK = 0.5 mA (3)	2.1	2.25	2.4
Boost inductor saturation detector
	VCS_th	Threshold on current sense		(3)	1.6	1.7	1.8	V
	IINV	E/A input pull-up current		After VCS > VCS_th, before restarting	5	10	13	µA
Startup timer
tSTART_DEL		Startup delay		First cycle after wake-up	20	50	100	µs
	tSTART	Timer period			75	150	350	µs
				Restart after VCS > VCS_th	150	300	700
Current sense comparator
	ICS	Input bias current		VCS = 0			1	µA
	tLEB	Leading edge blanking			70	150	300	ns
	td(H-L)	Delay to output			70	200	350	ns
	VCSclamp	Current sense reference clamp		VCOMP = upper clamp,	0.97	1.08	1.2	V
				VMULT =1 V, VVFF = 1 V
	Vcsofst	Current sense offset		VMULT = 0 V, VVFF = 3 V		40	70	mV
				VMULT = 3 V, VVFF = 3 V		20
PFC_OK functions
	IPFC_OK	Input bias current		VPFC_OK = 0 to 2.6 V		-0.1	-1	µA
VPFC_OK_C		Clamp voltage		IPFC_OK = 1 mA	8.5	9.5		V
VPFC_OK_S		OVP threshold		(1) Voltage rising	2.435	2.5	2.565	V
VPFC_OK_R		Restart threshold after OVP		(1) Voltage falling	2.34	2.4	2.46	V
VPFC_OK_D		Disable threshold		(1) Voltage falling	0.08		0.40	V
VPFC_OK_D		Disable threshold		(1) Voltage falling Tj = 25 °C	0.17	0.23	0.29	V
VPFC_OK_E		Enable threshold		(1) Voltage rising	0.10		0.43	V
VPFC_OK_E		Enable threshold		(1) Voltage rising Tj = 25 °C	0.21	0.27	0.32	V
	VFFD	Feedback failure detection		VPFC_OK = VPFC_OK_S	1.61	1.66	1.71	V
		threshold (VINV falling)

10/33

Doc ID 022671 Rev 1