ST L6564H User Manual

High voltage startup transition-mode PFC

Features

■ Onboard 700 V startup source

■ Fast “bi-directional” input voltage feedforward

■ Accurate adjustable output overvoltage

■ Protection against feedback loop

■ Inductor saturation protection

■ AC brownout detection

■ Low (≤ 100 µA) startup current

■ 6 mA max. operating bias current

■ 1% (@ T

■ -600/+800 mA totem pole gate driver with

■ SO-14 package

2

(1/V

correction)

protection

disconnection (latched shutdown)

= 25 °C) internal reference voltage

J

active pull-down during UVLO

L6564H

Datasheet − production data

SO-14

Application

■ PFC pre-regulators for:

– High-end AC-DC adapter/charger
– IEC61000-3-2 or JEITA-MITI compliant

SMPS, in excess of 400 W

– SMPS for LED luminaires

Figure 1. Block diagram

0.23 V

0.27 V

6

PFC_OK

COMP

MULT

INV

2.5 V

2.4 V

1.66 V

2

1

2.5 V

3

ON/OFF Control

+

-

-

+

+

-

-

+

Ideal rectif ier

Disable

OVP

Error A mplif ier

-

+

+

0.8 V

0.88 V

-

L_OVP

1.4V

0.7V

VFF

ZCD

5

11

Zero Current

Detector

-

+

2

1/V

MULTIPLIER

Voltage

referen ces

Intern al Supply Bus

Q1

LEB

-+

HVS

8

VOLTAGE

…

REGULATOR

SRQ1

STARTER

Disable

ON/OFF Control

MAINS DROP

DETECTOR

OVP

Starter

OFF

1.7 V

UVLO

DISABLE

+

-

UVLO

charge

I

Q S

Disable

Vcc

14

13

GD

L_OVP

R

UVLO

12

GND

4

CS

AM11475v1

June 2012 Doc ID 022960 Rev 2 1/35

This is information on a product in full production.

www.st.com

35

Contents L6564H

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.1 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.2 Feedback failure protection (FFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.3 Voltage feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.4 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.5 Inductor saturation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.6 Power management/housekeeping functions . . . . . . . . . . . . . . . . . . . . . . 24

7 High voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8 Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

10 Ordering codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2/35 Doc ID 022960 Rev 2

L6564H List of tables

List of tables

Table 1. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 5. Summary of L6564H idle states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 6. SO-14 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 7. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Doc ID 022960 Rev 2 3/35

List of figures L6564H

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. Typical system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. IC consumption vs. V
Figure 5. IC consumption vs. T
Figure 6. V

Zener voltage vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

CC

Figure 7. Startup and UVLO vs. T
Figure 8. Feedback reference vs. T
Figure 9. E/A output clamp levels vs. T
Figure 10. UVLO saturation vs. T
Figure 11. OVP levels vs. T

J

Figure 12. Inductor saturation threshold vs. T
Figure 13. Vcs clamp vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

J

Figure 14. ZCD sink/source capability vs. T
Figure 15. ZCD clamp level vs. T
Figure 16. R discharge vs. T
Figure 17. Line drop detection threshold vs. T
Figure 18. VMULTpk - VVFF dropout vs. T
Figure 19. PFC_OK threshold vs. T
Figure 20. PFC_OK FFD threshold vs. T

Figure 21. Multiplier characteristics @VFF=1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 22. Multiplier characteristics @VFF=3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 23. Multiplier gain vs. T
Figure 24. Gate drive clamp vs. T
Figure 25. Gate drive output saturation vs. T
Figure 26. Delay to output vs. T
Figure 27. Startup timer period vs. T
Figure 28. HV start voltage vs. T
Figure 29. V

restart voltage vs. TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CC

Figure 30. HV breakdown voltage vs. T

Figure 31. Output voltage setting, OVP and FFP functions: internal block diagram . . . . . . . . . . . . . . 18

Figure 32. Voltage feedforward: squarer/divider (1/V2) block diagram and transfer characteristics . . 19

Figure 33. RFF·CFF as a function of 3rd harmonic distortion introduced in the input current . . . . . . . 21

Figure 34. THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 35. THD optimization: standard TM PFC controller (left side) and L6564H (right side) . . . . . . 23

Figure 36. Effect of boost inductor saturation on the MOSFET current and detection method . . . . . . 24

Figure 37. Interface circuits that let the DC-DC converter’s controller IC disable the L6564H . . . . . . 25

Figure 38. High voltage startup generator: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 39. Timing diagram: normal power-up and power-down sequences . . . . . . . . . . . . . . . . . . . . 26

Figure 40. High voltage startup behavior during latch-off protection . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 41. High voltage startup managing the DC-DC output short-circuit . . . . . . . . . . . . . . . . . . . . . 28

Figure 42. Demonstration board EVL6564H - 100 W, wide-range mains: electrical schematic. . . . . . 29

Figure 43. EVL6564H demonstration board: compliance to EN61000-3-2 standard . . . . . . . . . . . . . . 30

Figure 44. EVL6564H demonstration board: compliance to JEITA-MITI standard . . . . . . . . . . . . . . . 30

Figure 45. EVL6564H demonstration board: input current waveform @230 V -50 Hz - 100 W load . . 30
Figure 46. EVL6564H demonstration board: input current waveform @100 V - 50 Hz - 100 W load . 30

Figure 47. SO-14 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

J

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4/35 Doc ID 022960 Rev 2

L6564H Description

1 Description

The L6564H is a current-mode PFC controller operating in transition mode (TM) which
embeds the same features existing in the L6564 with the addition of a high voltage startup
source. These functions make the IC especially suitable for applications that must be
compliant with energy saving regulations and where the PFC preregulator works as the
master stage.

The highly linear multiplier, along with a special correction circuit that reduces crossover
distortion of the mains current, allows wide-range-mains operation with an extremely low
THD even over a large load range.

The output voltage is controlled by means of a voltage-mode error amplifier and an accurate
(1% @T
feedforward function (1/V
also considerably improves line transient response in the case of both mains drops and
surges (“bi-directional”).

In addition to overvoltage protection able to control the output voltage during transient
conditions, the IC also provides protection against feedback loop failures or erroneous
settings. Other onboard protection functions allow brownout conditions and boost inductor
saturation to be safely handled.

= 25 °C) internal voltage reference. The loop stability is optimized by the voltage

J

2

correction), which, in this IC, uses a proprietary technique that

The totem pole output stage, capable of a 600 mA source and 800 mA sink current, is
suitable for a high power MOSFET or IGBT drive. This, combined with the other features
and the possibility to operate with ST's proprietary fixed-off-time control, makes the device
an excellent solution for SMPS up to 400 W that requires compliance with EN61000-3-2 and
JEITA-MITI standards.

Doc ID 022960 Rev 2 5/35

Maximum ratings L6564H

2 Maximum ratings

2.1 Absolute maximum ratings

Table 1. Absolute maximum ratings

Symbol Pin Parameter Value Unit

V

HVS

I

HVS

V

CC

--- 1, 3, 6 Max. pin voltage (Ipin ≤

--- 2, 4, 5 Analog inputs and outputs -0.3 to 8 V

I

ZCD

VFF pin 5 Maximum withstanding voltage range

Other pins

1 to 4

6, 8, 11 to 14

2.2 Thermal data

Table 2. Thermal data

Symbol Parameter Value Unit

R

thJA

Ptot Power dissipation @T

T

T

Max. thermal resistance, junction-to-ambient 120 °C/W

Junction temperature operating range -40 to 150 °C

J

Storage temperature -55 to 150 °C

stg

8 Voltage range (referred to ground) -0.3 to 700 V

8 Output current Self-limited I

HVS

14 IC supply voltage (Icc ≤ 20 mA) Self-limited V

1 mA) Self-limited V

11 Zero current detector max. current

test condition: CDF-AEC-Q100-002
“human body model”
acceptance criteria: “normal performance”

= 50 °C 0.75 W

A

-10 (source)
10 (sink)

+/- 1750 V

+/- 2000 V

mA

6/35 Doc ID 022960 Rev 2

L6564H Pin connection

3 Pin connection

Figure 2. Pin connection

INV

COMP

MULT

CS

VFF

PFC_OK

N.C.

1

2

3

4

5

6

78

Table 3. Pin description

n° Name Function

Inverting input of the error amplifier. The information on the output voltage of the PFC pre-

1INV

2COMP

regulator is fed into the pin through a resistor divider. The pin normally features high
impedance.

Output of the error amplifier. A compensation network is placed between this pin and INV (pin

1) to achieve stability of the voltage control loop and ensure high power factor and low THD. To
avoid an uncontrolled rise of the output voltage at zero load, when the voltage on the pin falls
below 2.4 V the gate driver output is inhibited (burst-mode operation).

14

13

12

11

10

Vcc

GD

GND

ZCD

N.C.

9

N.C.

HVS

AM11476v1

3MULT

4CS

5VFF

Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor
divider and provides the sinusoidal reference to the current loop. The voltage on this pin is used
also to derive the information on the RMS mains voltage.

Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor,
the resulting voltage is applied to this pin and compared with an internal reference to determine
MOSFET turn-off. A second comparison level at 1.7 V detects abnormal currents (e.g. due to
boost inductor saturation) and, on this occurrence, activates a safety procedure that temporarily
stops the converter and limits the stress of the power components.

2

Second input to the multiplier for 1/V
connected from the pin to GND. They complete the internal peak-holding circuit that derives the
information on the RMS mains voltage. The voltage at this pin, a DC level equal to the peak
voltage on the MULT pin (3), compensates the control loop gain dependence on the mains
voltage. Never connect the pin directly to GND but with a resistor ranging from 100 KΩ
(minimum) to 2 MΩ (maximum).

Doc ID 022960 Rev 2 7/35

function. A capacitor and a parallel resistor must be

Pin connection L6564H

Table 3. Pin description (continued)

n° Name Function

PFC pre-regulator output voltage monitoring/disable function. This pin senses the output
voltage of the PFC pre-regulator through a resistor divider and is used for protection purposes.

If the voltage on the pin exceeds 2.5 V, the IC stops switching and restarts as the voltage on the

6PFC_OK

7 N.C. Not internally connected. Provision for clearance on the PCB to meet safety requirements.

8HVS

9 N.C. Not internally connected. Provision for clearance on the PCB to meet safety requirements.

pin falls below 2.4 V. However, if at the same time the voltage of the INV pin falls below 1.66 V,
a feedback failure is assumed. In this case the device is latched off. Normal operation can be
resumed only by cycling V

. bringing its value lower than 6 V before moving up to the turn-on

CC

threshold. If the voltage on this pin is brought below 0.23 V, the IC is shut down. To restart the
IC the voltage on the pin must go above 0.27 V. This can be used as a remote on/off control
input.

High voltage startup. The pin, able to withstand 700 V, is to be tied directly to the rectified mains
voltage. A 1 mA internal current source charges the capacitor connected between the V
(14) and the GND pin (12) until the voltage on the V
then shut down. Normally, the generator is re-enabled when the V

pin reaches the startup threshold, it is

CC

voltage falls below 6 V to

CC

CC

pin

ensure a low power throughput during short-circuit. Otherwise, when a latched protection is
tripped the generator is re-enabled as V

reaches the UVLO threshold to keep the latch

CC

supplied.

10 N.C. Not internally connected. Provision for clearance on the PCB to meet safety requirements.

11 ZCD

Boost inductor demagnetization sensing input for transition-mode operation. A negative-going
edge triggers MOSFET turn-on.

12 GND Ground. Current return for both the signal part of the IC and the gate driver.

Gate driver output. The totem pole output stage is able to drive Power MOSFETs and IGBTs

13 GD

with a peak current of 600 mA source and 800 mA sink. The high level voltage of this pin is
clamped at about 12 V to avoid excessive gate voltages.

Supply voltage of both the signal part of the IC and the gate driver. Sometimes a small bypass

14 V

CC

capacitor (0.1 µF typ.) to GND might be useful to get a clean bias voltage for the signal part of
the IC.

Figure 3. Typical system block diagram

PFC PRE-REGULATOR DC-DC CONVERTER

inac

V

PWM is turned off in case of PFC's

anomalous operation for safety

PWM or

L6564H

PFC can be handled off/on according
to the load c ondition to ease compliance

with energy saving regulations.

Resonant

CONTROLLER

V

outd c

AM11477v1

8/35 Doc ID 022960 Rev 2

L6564H Electrical characteristics

4 Electrical characteristics

(TJ = -25 to 125 °C, VCC= 12 V, CO = 1 nF between pin GD and GND, C

= 1 µF and RFF =

FF

1 MΩ between pin VFF and GND; unless otherwise specified.)

Table 4. Electrical characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

Supply voltage

V

CC

V

CCOn

V

CCOff

V

CCrestartVCC

Hys Hysteresis 2.3 2.7 V

V

Supply current

I

start-up

I

q

I

CC

I

qdis

I

q

High voltage startup generator

Operating range After turn-on 10.3 22.5 V

Turn-on threshold

Turn-off threshold

(1)

(1)

11 12 13 V

8.7 9.5 10.3 V

for resuming from latch OVP latched 5 6 7 V

Zener voltage Icc = 20 mA 22.5 25 28 V

Z

Startup current Before turn-on, VCC = 10 V 90 150 µA

Quiescent current After turn-on, V

= 1 V 4 5 mA

MULT

Operating supply current @ 70 kHz 5 6.0 mA

Idle state quiescent current

Quiescent current

V
V

V

V
V

> V

PFC_OK

INV<VFFD

PFC_OK<VPFC_OK_D

PFC_OK>VPFC_OK_S

COMP

PFC_OK_S

< 2.3 V

AND

OR

180 280 µA

1.5 2.2 mA

2.2 3 mA

V

HV

V

HVstart

I

charge

I

HV, ON

I

HV, OFF

V

CCrestartVCC

Breakdown voltage I

Start voltage IVCC < 100 µA 65 80 100 V

VCC charge current VHV > V

ON-state current VHV > V

OFF-state leakage current VHV = 400 V 40 µA

Multiplier input

I

MULT

V

MULT

V

CLAMP

Input bias current V

Linear operation range 0 to 3 V

Internal clamp level I

restart voltage

< 100 µA 700 V

HV

, VCC> 3 V 0.55 0.85 1 mA

Hvstart

, VCC> 3 V 1.6 mA

Hvstart

> V

V

HV

V

falling 5 6 7

CC

(1)

IC latched off 8.7 9.5 10.3

MULT

= 1 mA 9 9.5 V

MULT

, V

Hvstart

= 0 0.8

CC

V

= 0 to 3 V -0.2 -1 µA

Doc ID 022960 Rev 2 9/35

Electrical characteristics L6564H

Table 4. Electrical characteristics (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

∆V

CS

------------- ---------

∆V

MULT

K

Output max. slope

Gain

M

Error amplifier

V

INV

Voltage feedback input
threshold

Line regulation VCC = 10.3 V to 22.5 V 2 5 mV

(2)

= 0 to 0.4 V, V

V

MULT

= upper clamp

V

COMP

V

= 1 V, V

MULT

T

= 25 °C 2.475 2.5 2.525

J

10.3 V < V

COMP

< 22.5 V

CC

= 1 V

VFF

1.33 1.66 V/V

= 4 V 0.375 0.45 0.525 V

(2)

2.455 2.545

V

I

INV

V

INVCLAMP

Input bias current V

Internal clamp level I

= 0 to 4 V -0.2 -1 µA

INV

= 1 mA 8 9 V

INV

Gv Voltage gain Open loop 60 80 dB

GB Gain-bandwidth product 1 MHz

I

COMP

V

COMP

Source current V

Sink current V

Upper clamp voltage I

Burst-mode voltage

Lower clamp voltage I

COMP

COMP

SOURCE

(1)

= 0.5 mA

SINK

= 4 V, V

= 4 V, V

= 2.4 V 2 4 mA

INV

= 2.6 V 2.5 4.5 mA

INV

= 0.5 mA 5.7 6.2 6.7 V

2.3 2.4 2.5

(1)

2.1 2.25 2.4

Current sense comparator

I

CS

t

LEB

td

(H-L)

V

CSclamp

Vcs

Input bias current VCS = 0 1 µA

Leading edge blanking 100 150 250 ns

Delay to output 100 200 300 ns

V

= upper clamp,

Current sense reference clamp

Current sense offset

ofst

COMP

V

MULT

V

MULT

V

MULT

=1 V, V

= 0, V

= 3 V, V

= 1 V

VFF

= 3 V 40 70

VFF

= 3 V 20

VFF

1.0 1.08 1.16 V

Boost inductor saturation detector

V

CS_th

I

INV

Threshold on current sense

E/A input pull-up current

(1)

After V

CS

restarting

> V

CS_th

, before

1.6 1.7 1.8 V

51013µA

mV

PFC_OK functions

I

PFC_OK

V

PFC_OK_C

V

PFC_OK_S

V

PFC_OK_R

Input bias current V

Clamp voltage I

OVP threshold

Restart threshold after OVP

PFC_OK

(1)

(1)

= 0 to 2.6 V -0.1 -1 µA

PFC_OK

= 1 mA 9 9.5 V

voltage rising 2.435 2.5 2.565 V

voltage falling 2.34 2.4 2.46 V

10/35 Doc ID 022960 Rev 2

L6564H Electrical characteristics

Table 4. Electrical characteristics (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

V

PFC_OK_D

V

PFC_OK_D

V

PFC_OK_E

V

PFC_OK_E

V

FFD

Disable threshold

Disable threshold

Enable threshold

Enable threshold

V

feedback failure detection

INV

threshold (V

Zero current detector

INV

falling)

(1)

voltage falling 0.12 0.35 V

(1)

voltage falling TJ = 25 °C 0.17 0.23 0.29 V

(1)

voltage rising 0.15 0.38 V

(1)

voltage rising TJ = 25 °C 0.21 0.27 0.32 V

V

PFC_OK

> V

PFC_OK_S

1.61 1.66 1.71 V

V

ZCDH

V

ZCDL

V

ZCDA

V

ZCDT

I

ZCDb

I

ZCDsrc

I

ZCDsnk

Upper clamp voltage I

Lower clamp voltage I

Arming voltage
(positive-going edge)

Triggering voltage
(negative-going edge)

Input bias current V

Source current capability -2.5 -4 mA

Sink current capability 2.5 5 mA

Startup timer

t

START_DEL

t

START

Startup delay First cycle after wake-up 25 50 75 µs

Timer period 75 150 300 µs

Voltage feedforward

V

VFF

Linear operation range 1 3 V

∆V Dropout V

∆V

∆V

R

DISCH

V

V

VFF

VFF

DIS

EN

Line drop detection threshold Below peak value 40 70 100 mV

Line drop detection threshold

Internal discharge resistor

Disable threshold

Enable threshold

Gate driver

V

V

I

srcpk

I

snkpk

OL

OH

Output low voltage I

Output high voltage I

Peak source current -0.6 A

Peak sink current 0.8 A

MULTpk-VVFF

= 2.5 mA 5.0 5.7 V

ZCD

= - 2.5 mA -0.3 0 0.3 V

ZCD

1.1 1.4 1.9 V

0.5 0.7 0.9 V

= 1 to 4.5 V 1 µA

ZCD

Restart after V

VCC< V

V

CCOn

> or = to V

CC

Below peak value

= 25 °C

T

J

T

= 25 °C 7.5 10 12.5 kΩ

J

CS

CCOn

> V

CS_th

150 300 600

800 mV

20

50 70 90 mV

520

(1)

voltage falling 0.745 0.8 0.855 V

(1)

voltage rising 0.845 0.88 0.915 V

= 100 mA 0.6 1.2 V

sink

= 5 mA 9.8 10.3 V

source

Doc ID 022960 Rev 2 11/35

Electrical characteristics L6564H

Table 4. Electrical characteristics (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

V

Oclamp

t

t

Voltage fall time 30 60 ns

f

Voltage rise time 45 110 ns

r

Output clamp voltage I

UVLO saturation V

1. Parameters tracking each other.

2. The multiplier output is given by:

()

K+ V=csV

·

MCS_Ofst

COMPMULT

2

V

VF F

= 5 mA; VCC = 20 V 10 12 15 V

source

= 0 to V

CC

5.2V·V

-

CCOn

, I

= 2 mA 1.1 V

sink

12/35 Doc ID 022960 Rev 2

L6564H Typical electrical performance

5 Typical electrical performance

Figure 4. IC consumption vs. V

100

10

1

Icc [mA]

0.1

0.01

0.001
0 5 10 15 20 25 30

Vcc [V]

Co=1nF
f =70kHz
Tj = 25°C

CC

VccOFF

VccON

AM11478v1

Figure 6. VCC Zener voltage vs. T

28

27

26

V

25

24

23

J

Figure 5. IC consumption vs. T

10

1

VCC=12V
Co = 1 nF
f =70kHz

Ic current (mA)

0.1

0.01

-50 -25 0 25 50 75 100 125 150 175

Tj (C)

J

Operating

Quiescent

Disabled or
during OVP

Latched of f

Befo re Sta rt up

Figure 7. Startup and UVLO vs. T

13

12

11

10

V

9

8

7

VCC-ON

VCC-OFF

AM11433v1

J

22

-50 -25 0 25 50 75 100 125 150 175
Tj (C)

AM11434v1

Figure 8. Feedback reference vs. T

2.6

2.55

2.5

pin INV (V)

2.45

2.4

-50 -25 0 25 50 75 100 125 150 175
Tj (C)

J

VCC = 12V

AM11436v1

Doc ID 022960 Rev 2 13/35

6

-50 -25 0 25 50 75 100 125 150 175

Tj (C)

AM11435v1

Figure 9. E/A output clamp levels vs. T

7

6

5

4

3

VCOMP (V)

2

1

0

-50 -25 0 25 50 75 100 125 150 175

Tj (C)

Uper Clamp

VCC = 12V

Lower Clamp

AM11437v1

J

Typical electrical performance L6564H

Figure 10. UVLO saturation vs. T

1

0.9

0.8

0.7

0.6

0.5

V

0.4

0.3

0.2

0.1

0

-50 - 25 0 25 50 75 100 125 150 175
Tj (C)

J

VCC = 0 V

Figure 11. OVP levels vs. T

2.5

2.48

2.46

2.44

2.42

PFC_OK level s (V)

2.4

2.38

2.36

-50 -25 0 25 50 75 100 125 150 175

Tj (C)

AM11438v1

Figure 12. Inductor saturation threshold vs. TJFigure 13. Vcs clamp vs. T

1.9

1.8

1.7

1.6

1.5

CS pin (V)

1.4

1.3

1.2

1.1

-50 -25 0 25 50 75 100 125 150 175

Tj (C)

1.4

1.3

1.2

VCSx (V)

1.1

1

-50 -25 0 25 50 75 100 125 150 175

Tj (C)

AM11440v1

J

OVP Th

Restart Th

J

VCC = 12V
VCOMP =Upper clamp

AM11439v1

AM11441v1

Figure 14. ZCD sink/source capability vs. T

8

6

4

2

0

IZCDsrc (mA)

-2

-4

-6

-8

-50 -25 0 25 50 75 100 125 150 175

Sink current

VCC = 12V

Source curre nt

Tj (C)

Figure 15. ZCD clamp level vs. T

J

AM11442v1

14/35 Doc ID 022960 Rev 2

J

7

6

5

4

3

VZCD pin (V)

2

1

0

-1

-50 -25 0 25 50 75 100 125 150 175
Tj (C)

Upper Clamp

VCC = 12V
Izcd =

Lower Clamp

±

2.5mV

AM11443v1

L6564H Typical electrical performance

Figure 16. R discharge vs. T

20

18

16

14

12

10

kOhm

8

6

4

2

0

-50 -25 0 25 50 75 1 00 125 150 175

J

Tj (C)

AM11444v1

Figure 18. V

MULTpk

2

1.5

1

0.5

0

(mV)

-0.5

-1

-1.5

-2

-50 -25 0 25 50 75 100 125 150 175

- V

dropout vs. T

VFF

Tj (C)

J

AM11446v1

Figure 17. Line drop detection threshold vs. T

90

80

70

60

50

mV

40

30

20

10

0

-50 -25 0 25 50 75 100 125 150 175

Figure 19. PFC_OK threshold vs. T

0.4

0.35

0.3

0.25

0.2

Th (V)

0.15

0.1

0.05

0

-50 -25 0 25 50 75 100 125 150 175

Tj (C)

AM11445v1

J

ON

OFF

Tj (C)

AM11447v1

J

Figure 20. PFC_OK FFD threshold vs. T

2

1.9

1.8

1.7

VFFD Th (V)

1.6

1.5

1.4

-50 -25 0 25 50 75 100 125 150 175

Tj(C)

J

AM11448v1

Doc ID 022960 Rev 2 15/35

Typical electrical performance L6564H

Figure 21. Multiplier characteristics @VFF=1 V Figure 22. Multiplier characteristics @VFF=3 V

1.2

1.1

1

0.9

0.8

0.7

0.6

VCS (V)

0.5

0.4

0.3

0.2

0.1

0

00.10.20.3 0.4 0.5 0.6 0. 7 0.8 0. 9 1 1.1

Upper voltage clamp

VMULT (V)

VCOMP

5.5

5.0V

4.5V

4.0V

3.5V

3.0

2.6V

AM11449v1

Figure 23. Multiplier gain vs. T

0.5

0.4

Gain (1/V)

0.3

J

VCC = 12V
VCOMP = 4V
VMULT = VFF = 1V

700

600

500

400

VCS (mV)

300

200

100

0

00.511.5 22.5 33.5

Upper vol tage

VMULT (V)

Figure 24. Gate drive clamp vs. T

12.9

12.85

12.8

V

12.75

VCC = 20V

VCOMP

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.6V

AM11450v1

J

12.7

0.2

-50 -25 0 25 50 75 100 125 150 175

Tj (C)

12.65

-50 -25 0 25 50 75 100 125 150 175
Tj (C)

AM11451v1

Figure 25. Gate drive output saturation vs. TJFigure 26. Delay to output vs. T

12

10

8

V

6

4

2

0

-50 -25 0 25 50 75 100 125 150 175
Tj (C)

High le vel

Low le vel

300

250

200

TD(H-L) (ns)

150

100

50

-50 -25 0 25 50 75 100 125 150 175
Tj (C)

AM11453v1

AM11452v1

J

VCC = 12V

AM11454v1

16/35 Doc ID 022960 Rev 2

L6564H Typical electrical performance

Figure 27. Startup timer period vs. T

450

400

350

300

250

200

Time (us)

150

100

50

0

-50 -25 0 25 50 75 100 125 150 175
Tj (C)

Afte r OCP

J

Timer

Fir st Cicle

AM11455v1

Figure 29. V

14

12

10

8

V

6

4

2

0

-50 -25 0 25 50 75 100 125 150 175

restart voltage vs. T

CC

Tj (C)

J

ICC

falling

AM11457v1

Figure 28. HV start voltage vs. T

100

80

60

V

40

20

0

-50 -25 0 25 50 75 100 125 150 175

Tj (C)

J

Figure 30. HV breakdown voltage vs. T

800

750

700

V

650

600

550

500

-50 -25 0 25 50 75 100 125 150 175

Tj (C)

AM11456v1

J

AM11458v1

Doc ID 022960 Rev 2 17/35

Application information L6564H

6 Application information

6.1 Overvoltage protection

Normally, the voltage control loop keeps the output voltage Vo of the PFC pre-regulator
close to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider. A
pin of the device (PFC_OK) has been dedicated to monitor the output voltage with a
separate resistor divider (R3 high, R4 low, see
the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value, usually
larger than the maximum V

that can be expected.

o

Figure 31

). This divider is selected so that

Example 1: V

= 400 V, V

o

= 434 V. Select: R3 = 8.8 MΩ; then: R4 = 8.8 MΩ ·2.5/(434-2.5)

OX

= 51 kΩ.

When this function is triggered, the gate drive activity is immediately stopped until the
voltage on the PFC_OK pin drops below 2.4 V. Note that R1, R2, R3 and R4 can be selected
without any constraints. The unique criterion is that both dividers must sink a current from
the output bus which needs to be significantly higher than the bias current of both INV and
PFC_OK pins.

Figure 31. Output voltage setting, OVP and FFP functions: internal block diagram

Vout

Vout

R3a

R3a

R3

R3

R3b

R3b

R4

R4

R1a

R1a

R1b

R1b

R2

R2

R1

R1

Frequency

Frequency

compensation

compensation

PFC_OK

PFC_OK

COMP

COMP

INV

INV

0.23 V

0.23 V

0.27 V

0.27 V

6

6

2.5 V

2.5 V

2.4 V

2.4 V

1.66 V

1.66 V

2

2

1

1

2.5 V

2.5 V

+

+

-

-

-

-

+

+

+

+

-

-

-

-

-

+

+

+

Disable

Disable

OVP

OVP

Error Amplifier

Error Amplifier

L_OVP

L_OVP

6.2 Feedback failure protection (FFP)

The OVP function described above handles “normal” overvoltage conditions, i.e. those
resulting from an abrupt load/line change or occurring at startup. If the overvoltage is
generated by a feedback disconnection, for instance when the upper resistor of the output
divider (R1) fails to open, the comparator detects the voltage at the INV pin. If the voltage is
lower than 1.66 V and the OVP is active, the FFP is triggered, the gate drive activity is

18/35 Doc ID 022960 Rev 2

AM11459v1

L6564H Application information

immediately stopped, the device is shut down, its quiescent consumption is reduced below
180 µA, and the condition is latched as long as the supply voltage of the IC is above the
UVLO threshold. To restart the system it is necessary to recycle the input power, so that the
V

voltage of the L6564H goes below 6 V.

CC

The PFC_OK pin doubles its function as a not-latched IC ‘disable’: a voltage below 0.23 V
shuts down the IC, reducing its consumption below 2 mA. To restart the IC simply let the
voltage at the pin go above 0.27 V.

Note that these functions offer complete protection against not only feedback loop failures or
erroneous settings, but also against a failure of the protection itself. Either resistor of the
PFC_OK voltage divider in a short condition or open, or the PFC_OK pin left floating, results
in shutting down the IC and stopping the pre-regulator.

6.3 Voltage feedforward

The power stage gain of PFC pre-regulators varies with the square of the RMS input
voltage. So does the crossover frequency f
has a single pole characteristic. This leads to a large trade-off in the design.

of the overall open-loop gain because the gain

c

For example, setting the gain of the error amplifier to get f
having f

≈ 4 Hz @ 88 Vac, resulting in sluggish control dynamics. Additionally, the slow

c

control loop causes large transient current flow during rapid line or load changes that are
limited by the dynamics of the multiplier output. This limit is considered when selecting the
sense resistor to let the full load power pass under minimum line voltage conditions, with
some margin. But a fixed current limit allows excessive power input at high line, whereas a
fixed power limit requires the current limit to vary inversely with the line voltage.

Voltage feedforward can compensate for the gain variation with the line voltage and allow
the minimizing of all the issues mentioned above. It consists of deriving a voltage
proportional to the input RMS voltage, feeding this voltage into a squarer/divider circuit (1/V
corrector) and providing the resulting signal to the multiplier that generates the current
reference for the inner current control loop (see

Figure 32. Voltage feedforward: squarer/divider (1/V

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Doc ID 022960 Rev 2 19/35

Application information L6564H

In this way a change of the line voltage causes an inversely proportional change of the half
sine amplitude at the output of the multiplier (if the line voltage doubles the amplitude of the
multiplier output is halved and vice versa) so that the current reference is adapted to the new
operating conditions with (ideally) no need for invoking the slow dynamics of the error
amplifier. Additionally, the loop gain is constant throughout the input voltage range, which
significantly improves dynamic behavior at low line and simplifies loop design.

Actually, deriving a voltage proportional to the RMS line voltage implies a form of integration,
which has its own time constant. If it is too small, the voltage generated is affected by a
considerable amount of ripple at twice the mains frequency which causes distortion of the
current reference (resulting in high HD and poor PF); if it is too large there is a considerable
delay in setting the right amount of feedforward, resulting in excessive overshoot and
undershoot of the pre-regulator output voltage in response to large line voltage changes.
Clearly a trade-off was required.

The L6564H realizes a new voltage feedforward that, with a technique that makes use of just
two external parts, strongly minimizes this time constant trade-off issue whichever voltage
change occurs on the mains, both surges and drops. A capacitor C

and a resistor RFF,

FF

both connected from the VFF pin (#5) to ground, complete an internal peak-holding circuit
that provides a DC voltage equal to the peak of the rectified sine wave applied on the MULT
pin (#3). In this way, in the case of sudden line voltage rise, C

is rapidly charged through

FF

the low impedance of the internal diode; in the case of line voltage drop, an internal “mains
drop” detector enables a low impedance switch which suddenly discharges C
long settling time before reaching the new voltage level. The discharge of C

avoiding a

FF

is stopped as

FF

its voltage equals the voltage on the MULT pin or if the voltage on the VFF pin falls below

0.88 V, to prevent the “brownout protection” function from being improperly activated (see

Section 6.6: Power management/housekeeping functions

).

As a result of the VFF pin functionality, an acceptably low steady-state ripple and low current
distortion can be achieved with a limited undershoot or overshoot on the pre-regulator
output.

The twice-mains-frequency (2

•f

) ripple appearing across CFF is triangular with a peak-to-

L

peak amplitude that, with good approximation, is given by:

V2

MULTpk

=V∆

where f

is the line frequency. The amount of 3rd harmonic distortion introduced by this

L

ripple, related to the amplitude of its 2

Figure 33

shows a diagram that helps in choosing the time constant RFF · CFF based on the

FF

+

•f

component, is:

L

=

%D

3

100

CRf41

FFFFL

CRfπ2

FFFFL

amount of maximum desired 3rd harmonic distortion. Note that there is a minimum value for
the time constant R

FF×CFF

occur. In fact, the twice-mains frequency ripple across C

below which improper activation of the VFF fast discharge may

under steady-state conditions

FF

must be lower than the minimum line drop detection threshold (DVVFF_min = 40 mV).
Therefore: must be lower than the minimum line drop detection threshold (∆V

FF_min

= 40

mV).

20/35 Doc ID 022960 Rev 2

L6564H Application information

So:

CR

Always connect R

and CFF to the pin, the IC does not work properly if the pin is either left

FF

floating or connected directly to ground.

Figure 33. R

FF·CFF

as a function of 3rd harmonic distortion introduced in the input

current

10

1

R · C [s]

FFFF

0.1

f = 60 Hz

L

0.01

V

2

∆V

>

FFFF

D %

3

max_MUL Tpk

min_VFF

f4

min_L

f = 50 Hz

L

1-

0111.0

AM11460v1

Doc ID 022960 Rev 2 21/35

Application information L6564H

6.4 THD optimizer circuit

The L6564H is provided with a special circuit that reduces the conduction dead-angle
occurring at the AC input current near the zero-crossings of the line voltage (crossover
distortion). In this way the THD (total harmonic distortion) of the current is considerably
reduced.

A major cause of this distortion is the inability of the system to transfer energy effectively
when the instantaneous line voltage is very low. This effect is magnified by the high­frequency filter capacitor placed after the bridge rectifier, which retains some residual
voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input
current flow to temporarily stop.

To overcome this issue the device forces the PFC pre-regulator to process more energy
near the line voltage zero-crossings as compared to that commanded by the control loop.
This results in both minimizing the time interval where energy transfer is lacking and fully
discharging the high-frequency filter capacitor after the bridge.

Figure 34

shows the internal block diagram of the THD optimizer circuit.

Figure 34. THD optimizer circuit

T

T

T

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-5,4

T

T

T



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

#/-0

#/-0

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T

T













TO07-

TO07-

TO07-

COMPARATOR

COMPARATOR

COMPARATOR

T

T

T

T

T

T

6AC

6AC

6AC

6AC6AC

6AC6AC

6AC6AC

22/35 Doc ID 022960 Rev 2

T

T

T

!-V

L6564H Application information

Figure 35. THD optimization: standard TM PFC controller (left side) and L6564H (right side)

Input current

MOSFET's drai n voltage

Vdrain

AM11461v1

Imains

Input c urrent

Input cur rent

Rectified mains voltage

MOSFET's drai n voltage

Vdrain

Imains

Input cur rent

Rectified mains voltage

Essentially, the circuit artificially increases the ON-time of the power switch with a positive
offset added to the output of the multiplier in the proximity of the line voltage zero-crossings.
This offset is reduced as the instantaneous line voltage increases, so that it becomes
negligible as the line voltage moves toward the top of the sinusoid. Furthermore, the offset is
modulated by the voltage on the VFF pin (see

Section 6.3

) so as to have little offset at low
line, where energy transfer at zero crossings is typically quite good, and a larger offset at
high line where the energy transfer worsens.

The effect of the circuit is shown in

Figure 35

PFC controller are compared to those of this chip.

To take maximum benefit from the THD optimizer circuit, the high-frequency filter capacitor
after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large
capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself ­even with an ideal energy transfer by the PFC pre-regulator - therefore reducing the
effectiveness of the optimizer circuit.

6.5 Inductor saturation detection

The boost inductor's hard saturation may be a fatal event for a PFC pre-regulator: the
current up-slope becomes so large (50-100 times steeper, see
current sense propagation delay the current may reach abnormally high values. The voltage
drop caused by this abnormal current on the sense resistor reduces the gate-to-source
voltage, so that the MOSFET may work in the active region and dissipate a huge amount of
power, which leads to a catastrophic failure after few switching cycles.

However, in some applications such as AC-DC adapters, where the PFC pre-regulator is
turned off at light load for energy saving reasons, even a well-designed boost inductor may

Doc ID 022960 Rev 2 23/35

, where the key waveforms of a standard TM

Figure 36

) that during the

Application information L6564H

occasionally slightly saturate when the PFC stage is restarted because of a larger load
demand. This happens when the restart occurs at an unfavorable line voltage phase, i.e.
when the output voltage is significantly below the rectified peak voltage. As a result, in the
boost inductor, the inrush current coming from the bridge rectifier adds to the switched
current and, furthermore, there is little or no voltage available for demagnetization.

To cope with a saturated inductor, the L6564H is provided with a second comparator on the
current sense pin (CS, pin 4) that stops the IC if the voltage, normally limited within 1.1 V,
exceeds 1.7 V. After that, the IC attempts to restart through the internal starter circuitry; the
starter repetition time is twice the nominal value to guarantee lower stress for the inductor
and boost diode. Hence, system safety is considerably increased.

Figure 36. Effect of boost inductor saturation on the MOSFET current and detection method

6.6 Power management/housekeeping functions

A communication line with the control IC of the cascaded DC-DC converter can be
established via the disable function included in the PFC_OK pin (see
details). This line is typically used to allow the PWM controller of the cascaded DC-DC
converter to shut down the L6564H in case of light load and to minimize the no-load input
consumption. Should the residual consumption of the chip be an issue, it is also possible to
cut down the supply voltage. Interface circuits are shown in
operation assumes that the cascaded DC-DC converter stage works as the master and the
PFC stage as the slave or, in other words, that the DC-DC stage starts first, it powers both
controllers and enables/disables the operation of the PFC stage.

Figure 37

AM11462v1

Section 6.2

for more

. Needless to say, this

24/35 Doc ID 022960 Rev 2

L6564H Application information

Figure 37. Interface circuits that let the DC-DC converter’s controller IC disable the

L6564H

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Another function available is the brownout protection which is basically a not-latched
shutdown function that is activated when a condition of mains undervoltage is detected. This
condition may cause overheating of the primary power section due to an excess of RMS
current. Brownout can also cause the PFC pre-regulator to function in open loop and this
may be dangerous to the PFC stage itself and the downstream converter, should the input
voltage return abruptly to its rated value. Another problem is the spurious restarts that may
occur during converter power-down and that cause the output voltage of the converter not to
decay to zero monotonically. For these reasons it is usually preferable to shut down the unit
in case of brownout. The brownout threshold is internally fixed at 0.8 V and is sensed on the
VFF pin (#5) during the voltage falling and an 80 mV threshold hysteresis prevents
rebounding at input voltage turn-off. In

Ta bl e 5

it is possible to find a summary of all of the

above mentioned working conditions that cause the device to stop operating.

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Doc ID 022960 Rev 2 25/35

High voltage startup generator L6564H

7 High voltage startup generator

Figure 38

shows the internal schematic of the high voltage startup generator (HV
generator). It is made up of a high voltage N-channel FET, whose gate is biased by a 15 MΩ
resistor, with a temperature-compensated current generator connected to its source.

Figure 38. High voltage startup generator: internal schematic

HVS

12

GND

8

HV

I

Vcc

14

charge

I

AM11463v1

Vcc_OK

15MW

HV_EN

CONTROL

The HV generator is physically located on a separate chip, made with BCD offline
technology able to withstand 700 V, controlled by a low voltage chip, where all of the control
functions reside.

With reference to the timing diagram of

Figure 39

, when power is first applied to the
converter the voltage on the bulk capacitor (Vin) builds up and, at about 80 V, the HV
generator is enabled to operate (HV_EN is pulled high) so that it draws about 1 mA. This
current, minus device consumption, charges the bypass capacitor connected from the V

CC

pin (14) to ground and causes its voltage to rise almost linearly.

Figure 39. Timing diagram: normal power-up and power-down sequences

VHV

V

HVstart

Vcc

(pin 14 )

ON

Vcc

OFF

Vcc

restart

Vcc

GD

(pin 13 )

HV_EN

Vcc_OK

I

charge

0.85 mA

26/35 Doc ID 022960 Rev 2

Rectified input voltage

Power-on Power-off

Normal

operation

Input so urce is removed here

DC- DC loses regulation here

HV con nected to bulk cap

HV connected to
rectified input voltage

Bulk cap voltage

t

t

t

t

t

t

AM11464v1

L6564H High voltage startup generator

As the VCC voltage reaches the startup threshold (12 V typ.) the low voltage chip starts
operating and the HV generator is cut off by the V
powered by the energy stored in the V

capacitor until the self-supply circuit (we assume

CC

_OK signal asserted high. The device is

CC

that it is made with an auxiliary winding in the transformer of the cascaded DC-DC converter
and a steering diode) develops a voltage high enough to sustain the operation. The residual
consumption of this circuit is just the one on the 15 MΩ resistor (≈ 10 mW at 400 Vdc),
typically 50-70 times lower, under the same conditions, as compared to a standard startup
circuit made with external dropping resistors.

At converter power-down the DC-DC converter loses regulation as soon as the input voltage
is so low that either peak current or maximum duty cycle limitation is tripped. V
and stop IC activity as it falls below the UVLO threshold (9.5 V typ.). The V
de-asserted as the V
HV generator can now restart. However, if Vin < V

voltage goes below a threshold V

CC

HVstart

CCrestart

located at about 6 V. The

, HV_EN is de-asserted too and the

then drops

CC

_OK signal is

CC

HV generator is disabled. This prevents converter restart attempts and ensures monotonic
output voltage decay at power-down in systems where brownout protection (see

Section 6.6: Power management/housekeeping functions

) is not used.

If the device detects a fault due to feedback failure, the internal V
over the V

(turn-off threshold). As a result, shown in

Off

CC

Figure 40

CCrestart

is brought up to

, the voltage at the VCC
pin oscillates between its turn-on and turn-off thresholds until the HV bus is recycled and
drops below the startup threshold of the HV generator.

The high voltage startup circuitry is capable of guaranteeing a safe behavior in case of
short-circuit present on the DC-DC output when the V
by the same auxiliary inding.

Figure 41

shows how the PFC manages the VCC cycling and

of both controllers are generated

CC

the associated power transfer. At short-circuit the auxiliary circuit is no longer able to sustain
the V
consumption and drops more until the V
startup generator restarts and when the V

which starts dropping; reaching its V

CC

threshold the IC stops switching, reduces

Off

CC

CCrestart

threshold is tripped. Now, the high voltage

again crosses its turn-on threshold the IC

CC

starts switching. In this manner the power is transferred from mains to PFC output only
during a short time for each trep cycle.

Figure 40. High voltage startup behavior during latch-off protection

Vcc

(pin 1 4)

Vcc

Vcc

Vcc

restart

GD

(pin 1 3)

HV_EN

ON

OFF

Fault occurs here

HV generator is turned on

Disable latch is reset here

HV generator turn-on is disabled here

Input source is removed here

t

t

V

Vin

HVstart

t

t

AM11465v1

Doc ID 022960 Rev 2 27/35

High voltage startup generator L6564H

Figure 41. High voltage startup managing the DC-DC output short-circuit

Vcc

(pin 1 4)

Vcc

Vcc

Vcc

GD

(pin 1 3)

Vcc_OK

I

charge

0.85 mA

ON

OFF

restart

Short-circuit o ccurs here

T

rep

Table 5 . Summary of L6564H idle states

Condition Caused or revealed by IC behavior Restart condition

UVLO V

Feedback

disconnected

< V

CC

PFC_OK > V

and

INV < 1.66 V

CCOff

PFC_OK_S

Disabled VCC > V

Latched

VCC < V

CCrestart

VCC > V

CCOn

CCOn

then

t

t

t

t

AM11466v1

Typical IC

consumption

90 µA

180 µA

Standby PFC_OK < V

PFC_OK_D

Stop switching

AC brownout RUN < VDIS Stop switching RUN > V

OVP PFC_OK > V

Low

consumption

Saturated

boost inductor

PFC_OK_S

COMP < 2.4 V Burst mode COMP > 2.4 V 2.2 mA

Vcs > V

CS_th

Stop Switching

Doubled T

28/35 Doc ID 022960 Rev 2

PFC_OK >
V

PFC_OK_E

EN

PFC_OK <
V

PFC_OK_R

Auto restart 2.2 mA

start

1.5 mA

1.5 mA

2.2 mA

L6564H Application examples and ideas

8 Application examples and ideas

Figure 42. Demonstration board EVL6564H - 100 W, wide-range mains: electrical schematic

J2

1

2

MKDS 1, 5/ 2-5,08

R3

3M3

R6

3M3

R11

2M2

R2

1M0

C6

47uF - 450V

R1

NTC 2R5-S237

D3

STTH2L06

D4

LL4148

D2

1N4005

3

R4

5

L2

SRW2620PQ-XXXV002

SUBMIT X08041-01-B (TDK VERSION)

6

100R

C7

4N7

8

R8

1M0

R10

1M0

D5

BZX79-C18

R5

68K

R15

51K

HS1

HEAT-SINK

R26

Q1

STF8NM50N

R20

N.M.

D6

N.M.

R21

0R68

R25

0R47

R22

100K

GND

VCC

ON/OFF

R24

220R

27R

123

J3

CON3

R31

10R

C11

C5

470N - 400V

+

_

D1

~

GBU4J

L1

HF2826-203Y1R5-T01

F1

FUSE 4A

J1

MKDS 1, 5/ 3-5,08

123

~

R14

C4

470N

C1

470N

27K

R13

62K

R9

2M2

R12

2M2

47uF-50V

C10

100N

13

14

GD

VCC

U1

L6564H

INV1COMP2MULT3CS4VFF5PFC_OK6NC

R18

82K

680N

C8

C9

68N

R17

2M2

R30

1K

10

12

11

ZCD

GND

R19

51K

C12

2N2

8

NC9NC

HVS

7

R27

1M

C13

1uF

C16

2N2

C15

220p

90-264Vac

AM11471v1

Doc ID 022960 Rev 2 29/35

Application examples and ideas L6564H

Figure 43. EVL6564H demonstration board:

compliance to EN61000-3-2
standard

Figure 45. EVL6564H demonstration board:

input current waveform @230 V -50
Hz - 100 W load

Figure 44. EVL6564H demonstration board:

compliance to JEITA-MITI standard

Figure 46. EVL6564H demonstration board:

input current waveform @100 V - 50
Hz - 100 W load

30/35 Doc ID 022960 Rev 2

L6564H Package mechanical data

9 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK
specifications, grade definitions and product status are available at:

packages, depending on their level of environmental compliance. ECOPACK

www.st.com

. ECOPACK

is an ST trademark.

Table 6 . SO-14 mechanical data

Databook (mm.)

Dim.

Min. Typ. Max.

A 1.35 1.75

A1 0.10 0.25

A2 1.10 1.65

B 0.33 0.51

C 0.19 0.25

D 8.55 8.75

E 3.80 4.00

e 1.27

H5.80 6.20

h0.25 0.50

L 0.40 1.27

K 0 8

e0.40

ddd 0.10

Doc ID 022960 Rev 2 31/35

Package mechanical data L6564H

Figure 47. SO-14 package dimensions

32/35 Doc ID 022960 Rev 2

0016019_E

L6564H Ordering codes

10 Ordering codes

Table 7. Ordering information

Order codes Package Packing

L6564H

SO-14

L6564HTR Tape and reel

Tube

Doc ID 022960 Rev 2 33/35

Revision history L6564H

11 Revision history

Table 8. Document revision history

Date Revision Changes

19-Apr-2012 1 Initial release.

07-Jun-2012 2 Datasheet promoted from preliminary data to production data.

34/35 Doc ID 022960 Rev 2

L6564H

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Doc ID 022960 Rev 2 35/35