ST L6564H User Manual

This is information on a product in full production.

June 2012 Doc ID 022960 Rev 2 1/35

L6564H

High voltage startup transition-mode PFC

Datasheet − production data

Features

■ Onboard 700 V startup source

■ Fast “bi-directional” input voltage feedforward

(1/V

correction)

■ Accurate adjustable output overvoltage

protection

■ Protection against feedback loop

disconnection (latched shutdown)

■ Inductor saturation protection

■ AC brownout detection

■ Low (≤ 100 µA) startup current

■ 6 mA max. operating bias current

■ 1% (@ T

= 25 °C) internal reference voltage

■ -600/+800 mA totem pole gate driver with

active pull-down during UVLO

■ SO-14 package

Application

■ PFC pre-regulators for:

– High-end AC-DC adapter/charger

– IEC61000-3-2 or JEITA-MITI compliant

SMPS, in excess of 400 W

– SMPS for LED luminaires

Figure 1. Block diagram

SO-14

AM11475v1

VFF

STARTER

LEB

VOLTAGE

REGULATOR

UVLO

2.5 V

MULTIPLIER

…

Intern al Supply Bus

Voltage

referen ces

0.23 V

Vcc

GND

MULT

INV

PFC_OK

ZCD

Disable

OVP

UVLO

Disable

Q S

DISABLE

L_OVP

UVLO

Error A mplif ier

COMP

Ideal rectif ier

1/V

2.5 V

2.4 V

OVP

L_OVP

Starter

OFF

0.7V

1.4V

Detector

Zero Current

ON/OFF Control

DETECTOR

MAINS DROP

1.7 V

Disable

charge

HVS

0.27 V

1.66 V

0.8 V

0.88 V

ON/OFF Control

www.st.com

Contents L6564H

2/35 Doc ID 022960 Rev 2

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.1 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.2 Feedback failure protection (FFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.3 Voltage feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.4 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.5 Inductor saturation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.6 Power management/housekeeping functions . . . . . . . . . . . . . . . . . . . . . . 24

7 High voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8 Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

10 Ordering codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

L6564H List of tables

Doc ID 022960 Rev 2 3/35

List of tables

Table 1. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 5. Summary of L6564H idle states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 6. SO-14 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 7. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

List of figures L6564H

4/35 Doc ID 022960 Rev 2

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. Typical system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. IC consumption vs. V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 5. IC consumption vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6. V

Zener voltage vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7. Startup and UVLO vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 8. Feedback reference vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 9. E/A output clamp levels vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 10. UVLO saturation vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 11. OVP levels vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 12. Inductor saturation threshold vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 13. Vcs clamp vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 14. ZCD sink/source capability vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 15. ZCD clamp level vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 16. R discharge vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 17. Line drop detection threshold vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 18. VMULTpk - VVFF dropout vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 19. PFC_OK threshold vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 20. PFC_OK FFD threshold vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 21. Multiplier characteristics @VFF=1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 22. Multiplier characteristics @VFF=3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 23. Multiplier gain vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 24. Gate drive clamp vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 25. Gate drive output saturation vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 26. Delay to output vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 27. Startup timer period vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 28. HV start voltage vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 29. V

restart voltage vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 30. HV breakdown voltage vs. T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 31. Output voltage setting, OVP and FFP functions: internal block diagram . . . . . . . . . . . . . . 18

Figure 32. Voltage feedforward: squarer/divider (1/V2) block diagram and transfer characteristics . . 19

Figure 33. RFF·CFF as a function of 3rd harmonic distortion introduced in the input current . . . . . . . 21

Figure 34. THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 35. THD optimization: standard TM PFC controller (left side) and L6564H (right side) . . . . . . 23

Figure 36. Effect of boost inductor saturation on the MOSFET current and detection method . . . . . . 24

Figure 37. Interface circuits that let the DC-DC converter’s controller IC disable the L6564H . . . . . . 25

Figure 38. High voltage startup generator: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 39. Timing diagram: normal power-up and power-down sequences . . . . . . . . . . . . . . . . . . . . 26

Figure 40. High voltage startup behavior during latch-off protection . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 41. High voltage startup managing the DC-DC output short-circuit . . . . . . . . . . . . . . . . . . . . . 28

Figure 42. Demonstration board EVL6564H - 100 W, wide-range mains: electrical schematic. . . . . . 29

Figure 43. EVL6564H demonstration board: compliance to EN61000-3-2 standard . . . . . . . . . . . . . . 30

Figure 44. EVL6564H demonstration board: compliance to JEITA-MITI standard . . . . . . . . . . . . . . . 30

Figure 45. EVL6564H demonstration board: input current waveform @230 V -50 Hz - 100 W load . . 30

Figure 46. EVL6564H demonstration board: input current waveform @100 V - 50 Hz - 100 W load . 30

Figure 47. SO-14 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

L6564H Description

Doc ID 022960 Rev 2 5/35

1 Description

The L6564H is a current-mode PFC controller operating in transition mode (TM) which

embeds the same features existing in the L6564 with the addition of a high voltage startup

source. These functions make the IC especially suitable for applications that must be

compliant with energy saving regulations and where the PFC preregulator works as the

master stage.

The highly linear multiplier, along with a special correction circuit that reduces crossover

distortion of the mains current, allows wide-range-mains operation with an extremely low

THD even over a large load range.

The output voltage is controlled by means of a voltage-mode error amplifier and an accurate

(1% @T

= 25 °C) internal voltage reference. The loop stability is optimized by the voltage

feedforward function (1/V

correction), which, in this IC, uses a proprietary technique that

also considerably improves line transient response in the case of both mains drops and

surges (“bi-directional”).

In addition to overvoltage protection able to control the output voltage during transient

conditions, the IC also provides protection against feedback loop failures or erroneous

settings. Other onboard protection functions allow brownout conditions and boost inductor

saturation to be safely handled.

The totem pole output stage, capable of a 600 mA source and 800 mA sink current, is

suitable for a high power MOSFET or IGBT drive. This, combined with the other features

and the possibility to operate with ST's proprietary fixed-off-time control, makes the device

an excellent solution for SMPS up to 400 W that requires compliance with EN61000-3-2 and

JEITA-MITI standards.

Maximum ratings L6564H

6/35 Doc ID 022960 Rev 2

2 Maximum ratings

2.1 Absolute maximum ratings

2.2 Thermal data

Table 1. Absolute maximum ratings

Symbol Pin Parameter Value Unit

HVS

8 Voltage range (referred to ground) -0.3 to 700 V

HVS

8 Output current Self-limited I

HVS

14 IC supply voltage (Icc ≤ 20 mA) Self-limited V

--- 1, 3, 6 Max. pin voltage (Ipin ≤

1 mA) Self-limited V

--- 2, 4, 5 Analog inputs and outputs -0.3 to 8 V

ZCD

11 Zero current detector max. current

-10 (source)

10 (sink)

VFF pin 5 Maximum withstanding voltage range

test condition: CDF-AEC-Q100-002

“human body model”

acceptance criteria: “normal performance”

+/- 1750 V

Other pins

1 to 4

6, 8, 11 to 14

+/- 2000 V

Table 2. Thermal data

Symbol Parameter Value Unit

thJA

Max. thermal resistance, junction-to-ambient 120 °C/W

Ptot Power dissipation @T

= 50 °C 0.75 W

Junction temperature operating range -40 to 150 °C

stg

Storage temperature -55 to 150 °C

L6564H Pin connection

Doc ID 022960 Rev 2 7/35

3 Pin connection

Figure 2. Pin connection

AM11476v1

HVS

COMP

MULT

VFF

GND

ZCD

PFC_OK

INV

Vcc

N.C.

Table 3. Pin description

n° Name Function

1INV

Inverting input of the error amplifier. The information on the output voltage of the PFC pre-

regulator is fed into the pin through a resistor divider. The pin normally features high

impedance.

2COMP

Output of the error amplifier. A compensation network is placed between this pin and INV (pin

1) to achieve stability of the voltage control loop and ensure high power factor and low THD. To

avoid an uncontrolled rise of the output voltage at zero load, when the voltage on the pin falls

below 2.4 V the gate driver output is inhibited (burst-mode operation).

3MULT

Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor

divider and provides the sinusoidal reference to the current loop. The voltage on this pin is used

also to derive the information on the RMS mains voltage.

4CS

Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor,

the resulting voltage is applied to this pin and compared with an internal reference to determine

MOSFET turn-off. A second comparison level at 1.7 V detects abnormal currents (e.g. due to

boost inductor saturation) and, on this occurrence, activates a safety procedure that temporarily

stops the converter and limits the stress of the power components.

5VFF

Second input to the multiplier for 1/V

function. A capacitor and a parallel resistor must be

connected from the pin to GND. They complete the internal peak-holding circuit that derives the

information on the RMS mains voltage. The voltage at this pin, a DC level equal to the peak

voltage on the MULT pin (3), compensates the control loop gain dependence on the mains

voltage. Never connect the pin directly to GND but with a resistor ranging from 100 KΩ

(minimum) to 2 MΩ (maximum).

Pin connection L6564H

8/35 Doc ID 022960 Rev 2

Figure 3. Typical system block diagram

6PFC_OK

PFC pre-regulator output voltage monitoring/disable function. This pin senses the output

voltage of the PFC pre-regulator through a resistor divider and is used for protection purposes.

If the voltage on the pin exceeds 2.5 V, the IC stops switching and restarts as the voltage on the

pin falls below 2.4 V. However, if at the same time the voltage of the INV pin falls below 1.66 V,

a feedback failure is assumed. In this case the device is latched off. Normal operation can be

resumed only by cycling V

. bringing its value lower than 6 V before moving up to the turn-on

threshold. If the voltage on this pin is brought below 0.23 V, the IC is shut down. To restart the

IC the voltage on the pin must go above 0.27 V. This can be used as a remote on/off control

input.

7 N.C. Not internally connected. Provision for clearance on the PCB to meet safety requirements.

8HVS

High voltage startup. The pin, able to withstand 700 V, is to be tied directly to the rectified mains

voltage. A 1 mA internal current source charges the capacitor connected between the V

(14) and the GND pin (12) until the voltage on the V

pin reaches the startup threshold, it is

then shut down. Normally, the generator is re-enabled when the V

voltage falls below 6 V to

ensure a low power throughput during short-circuit. Otherwise, when a latched protection is

tripped the generator is re-enabled as V

reaches the UVLO threshold to keep the latch

supplied.

9 N.C. Not internally connected. Provision for clearance on the PCB to meet safety requirements.

10 N.C. Not internally connected. Provision for clearance on the PCB to meet safety requirements.

11 ZCD

Boost inductor demagnetization sensing input for transition-mode operation. A negative-going

edge triggers MOSFET turn-on.

12 GND Ground. Current return for both the signal part of the IC and the gate driver.

13 GD

Gate driver output. The totem pole output stage is able to drive Power MOSFETs and IGBTs

with a peak current of 600 mA source and 800 mA sink. The high level voltage of this pin is

clamped at about 12 V to avoid excessive gate voltages.

14 V

Supply voltage of both the signal part of the IC and the gate driver. Sometimes a small bypass

capacitor (0.1 µF typ.) to GND might be useful to get a clean bias voltage for the signal part of

the IC.

Table 3. Pin description (continued)

n° Name Function

AM11477v1

inac

outd c

PWM is turned off in case of PFC's

anomalous operation for safety

PFC can be handled off/on according

to the load c ondition to ease compliance

with energy saving regulations.

L6564H

PWM or

Resonant

CONTROLLER

PFC PRE-REGULATOR DC-DC CONVERTER

L6564H Electrical characteristics

Doc ID 022960 Rev 2 9/35

4 Electrical characteristics

= -25 to 125 °C, V

= 12 V, C

= 1 nF between pin GD and GND, C

= 1 µF and R

1 MΩ between pin VFF and GND; unless otherwise specified.)

Table 4. Electrical characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

Supply voltage

Operating range After turn-on 10.3 22.5 V

CCOn

Turn-on threshold

(1)

11 12 13 V

CCOff

Turn-off threshold

(1)

8.7 9.5 10.3 V

CCrestart

for resuming from latch OVP latched 5 6 7 V

Hys Hysteresis 2.3 2.7 V

Zener voltage Icc = 20 mA 22.5 25 28 V

Supply current

start-up

Startup current Before turn-on, V

= 10 V 90 150 µA

Quiescent current After turn-on, V

MULT

= 1 V 4 5 mA

Operating supply current @ 70 kHz 5 6.0 mA

qdis

Idle state quiescent current

PFC_OK

> V

PFC_OK_S

AND

INV

FFD

180 280 µA

PFC_OK

PFC_OK_D

1.5 2.2 mA

Quiescent current

PFC_OK

PFC_OK_S

COMP

< 2.3 V

2.2 3 mA

High voltage startup generator

Breakdown voltage I

< 100 µA 700 V

HVstart

Start voltage IV

< 100 µA 65 80 100 V

charge

charge current V

> V

Hvstart

, V

> 3 V 0.55 0.85 1 mA

HV, ON

ON-state current V

> V

Hvstart

, V

> 3 V 1.6 mA

> V

Hvstart

, V

= 0 0.8

HV, OFF

OFF-state leakage current V

= 400 V 40 µA

CCrestart

restart voltage

falling 5 6 7

(1)

IC latched off 8.7 9.5 10.3

Multiplier input

MULT

Input bias current V

MULT

= 0 to 3 V -0.2 -1 µA

MULT

Linear operation range 0 to 3 V

CLAMP

Internal clamp level I

MULT

= 1 mA 9 9.5 V

Electrical characteristics L6564H

10/35 Doc ID 022960 Rev 2

Output max. slope

MULT

= 0 to 0.4 V, V

VFF

= 1 V

COMP

= upper clamp

1.33 1.66 V/V

Gain

(2)

MULT

= 1 V, V

COMP

= 4 V 0.375 0.45 0.525 V

Error amplifier

INV

Voltage feedback input

threshold

= 25 °C 2.475 2.5 2.525

10.3 V < V

< 22.5 V

(2)

2.455 2.545

Line regulation V

= 10.3 V to 22.5 V 2 5 mV

INV

Input bias current V

INV

= 0 to 4 V -0.2 -1 µA

INVCLAMP

Internal clamp level I

INV

= 1 mA 8 9 V

Gv Voltage gain Open loop 60 80 dB

GB Gain-bandwidth product 1 MHz

COMP

Source current V

COMP

= 4 V, V

INV

= 2.4 V 2 4 mA

Sink current V

COMP

= 4 V, V

INV

= 2.6 V 2.5 4.5 mA

COMP

Upper clamp voltage I

SOURCE

= 0.5 mA 5.7 6.2 6.7 V

Burst-mode voltage

(1)

2.3 2.4 2.5

Lower clamp voltage I

SINK

= 0.5 mA

(1)

2.1 2.25 2.4

Current sense comparator

Input bias current V

= 0 1 µA

LEB

Leading edge blanking 100 150 250 ns

(H-L)

Delay to output 100 200 300 ns

CSclamp

Current sense reference clamp

COMP

= upper clamp,

MULT

=1 V, V

VFF

= 1 V

1.0 1.08 1.16 V

Vcs

ofst

Current sense offset

MULT

= 0, V

VFF

= 3 V 40 70

MULT

= 3 V, V

VFF

= 3 V 20

Boost inductor saturation detector

CS_th

Threshold on current sense

(1)

1.6 1.7 1.8 V

INV

E/A input pull-up current

After V

> V

CS_th

, before

restarting

51013µA

PFC_OK functions

PFC_OK

Input bias current V

PFC_OK

= 0 to 2.6 V -0.1 -1 µA

PFC_OK_C

Clamp voltage I

PFC_OK

= 1 mA 9 9.5 V

PFC_OK_S

OVP threshold

(1)

voltage rising 2.435 2.5 2.565 V

PFC_OK_R

Restart threshold after OVP

(1)

voltage falling 2.34 2.4 2.46 V

Table 4. Electrical characteristics (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

∆V

MULT

------------- ---------

L6564H Electrical characteristics

Doc ID 022960 Rev 2 11/35

PFC_OK_D

Disable threshold

(1)

voltage falling 0.12 0.35 V

PFC_OK_D

Disable threshold

(1)

voltage falling T

= 25 °C 0.17 0.23 0.29 V

PFC_OK_E

Enable threshold

(1)

voltage rising 0.15 0.38 V

PFC_OK_E

Enable threshold

(1)

voltage rising T

= 25 °C 0.21 0.27 0.32 V

FFD

INV

feedback failure detection

threshold (V

INV

falling)

PFC_OK

> V

PFC_OK_S

1.61 1.66 1.71 V

Zero current detector

ZCDH

Upper clamp voltage I

ZCD

= 2.5 mA 5.0 5.7 V

ZCDL

Lower clamp voltage I

ZCD

= - 2.5 mA -0.3 0 0.3 V

ZCDA

Arming voltage

(positive-going edge)

1.1 1.4 1.9 V

ZCDT

Triggering voltage

(negative-going edge)

0.5 0.7 0.9 V

ZCDb

Input bias current V

ZCD

= 1 to 4.5 V 1 µA

ZCDsrc

Source current capability -2.5 -4 mA

ZCDsnk

Sink current capability 2.5 5 mA

Startup timer

START_DEL

Startup delay First cycle after wake-up 25 50 75 µs

START

Timer period 75 150 300 µs

Restart after V

> V

CS_th

150 300 600

Voltage feedforward

VFF

Linear operation range 1 3 V

∆V Dropout V

MULTpk

-V

VFF

< V

CCOn

800 mV

> or = to V

CCOn

∆V

VFF

Line drop detection threshold Below peak value 40 70 100 mV

∆V

VFF

Line drop detection threshold

Below peak value

= 25 °C

50 70 90 mV

DISCH

Internal discharge resistor

= 25 °C 7.5 10 12.5 kΩ

520

DIS

Disable threshold

(1)

voltage falling 0.745 0.8 0.855 V

Enable threshold

(1)

voltage rising 0.845 0.88 0.915 V

Gate driver

Output low voltage I

sink

= 100 mA 0.6 1.2 V

Output high voltage I

source

= 5 mA 9.8 10.3 V

srcpk

Peak source current -0.6 A

snkpk

Peak sink current 0.8 A

Table 4. Electrical characteristics (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

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