ST L6564H User Manual
High voltage startup transition-mode PFC
Features
■ Onboard 700 V startup source
■ Fast “bi-directional” input voltage feedforward
■ Accurate adjustable output overvoltage
■ Protection against feedback loop
■ Inductor saturation protection
■ AC brownout detection
■ Low (≤ 100 µA) startup current
■ 6 mA max. operating bias current
■ 1% (@ T
■ -600/+800 mA totem pole gate driver with
■ SO-14 package
2
(1/V
correction)
protection
disconnection (latched shutdown)
= 25 °C) internal reference voltage
J
active pull-down during UVLO
L6564H
Datasheet − production data
SO-14
Application
■ PFC pre-regulators for:
– High-end AC-DC adapter/charger
– IEC61000-3-2 or JEITA-MITI compliant
SMPS, in excess of 400 W
– SMPS for LED luminaires
Figure 1. Block diagram
0.23 V
0.27 V
6
PFC_OK
COMP
MULT
INV
2.5 V
2.4 V
1.66 V
2
1
2.5 V
3
ON/OFF Control
+
-
-
+
+
-
-
+
Ideal rectif ier
Disable
OVP
Error A mplif ier
-
+
+
0.8 V
0.88 V
-
L_OVP
1.4V
0.7V
VFF
ZCD
5
11
Zero Current
Detector
-
+
2
1/V
MULTIPLIER
Voltage
referen ces
Intern al Supply Bus
Q1
LEB
-+
HVS
8
VOLTAGE
…
REGULATOR
SRQ1
STARTER
Disable
ON/OFF Control
MAINS DROP
DETECTOR
OVP
Starter
OFF
1.7 V
UVLO
DISABLE
+
-
UVLO
charge
I
Q S
Disable
Vcc
14
13
GD
L_OVP
R
UVLO
12
GND
4
CS
AM11475v1
June 2012 Doc ID 022960 Rev 2 1/35
This is information on a product in full production.
www.st.com
35
Contents L6564H
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 Feedback failure protection (FFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 Voltage feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.5 Inductor saturation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.6 Power management/housekeeping functions . . . . . . . . . . . . . . . . . . . . . . 24
7 High voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8 Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10 Ordering codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2/35 Doc ID 022960 Rev 2
L6564H List of tables
List of tables
Table 1. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Summary of L6564H idle states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 6. SO-14 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 7. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Doc ID 022960 Rev 2 3/35
List of figures L6564H
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Typical system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. IC consumption vs. V
Figure 5. IC consumption vs. T
Figure 6. V
Zener voltage vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CC
Figure 7. Startup and UVLO vs. T
Figure 8. Feedback reference vs. T
Figure 9. E/A output clamp levels vs. T
Figure 10. UVLO saturation vs. T
Figure 11. OVP levels vs. T
J
Figure 12. Inductor saturation threshold vs. T
Figure 13. Vcs clamp vs. T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
J
Figure 14. ZCD sink/source capability vs. T
Figure 15. ZCD clamp level vs. T
Figure 16. R discharge vs. T
Figure 17. Line drop detection threshold vs. T
Figure 18. VMULTpk - VVFF dropout vs. T
Figure 19. PFC_OK threshold vs. T
Figure 20. PFC_OK FFD threshold vs. T
Figure 21. Multiplier characteristics @VFF=1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 22. Multiplier characteristics @VFF=3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 23. Multiplier gain vs. T
Figure 24. Gate drive clamp vs. T
Figure 25. Gate drive output saturation vs. T
Figure 26. Delay to output vs. T
Figure 27. Startup timer period vs. T
Figure 28. HV start voltage vs. T
Figure 29. V
restart voltage vs. TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CC
Figure 30. HV breakdown voltage vs. T
Figure 31. Output voltage setting, OVP and FFP functions: internal block diagram . . . . . . . . . . . . . . 18
Figure 32. Voltage feedforward: squarer/divider (1/V2) block diagram and transfer characteristics . . 19
Figure 33. RFF·CFF as a function of 3rd harmonic distortion introduced in the input current . . . . . . . 21
Figure 34. THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 35. THD optimization: standard TM PFC controller (left side) and L6564H (right side) . . . . . . 23
Figure 36. Effect of boost inductor saturation on the MOSFET current and detection method . . . . . . 24
Figure 37. Interface circuits that let the DC-DC converter’s controller IC disable the L6564H . . . . . . 25
Figure 38. High voltage startup generator: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 39. Timing diagram: normal power-up and power-down sequences . . . . . . . . . . . . . . . . . . . . 26
Figure 40. High voltage startup behavior during latch-off protection . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 41. High voltage startup managing the DC-DC output short-circuit . . . . . . . . . . . . . . . . . . . . . 28
Figure 42. Demonstration board EVL6564H - 100 W, wide-range mains: electrical schematic. . . . . . 29
Figure 43. EVL6564H demonstration board: compliance to EN61000-3-2 standard . . . . . . . . . . . . . . 30
Figure 44. EVL6564H demonstration board: compliance to JEITA-MITI standard . . . . . . . . . . . . . . . 30
Figure 45. EVL6564H demonstration board: input current waveform @230 V -50 Hz - 100 W load . . 30
Figure 46. EVL6564H demonstration board: input current waveform @100 V - 50 Hz - 100 W load . 30
Figure 47. SO-14 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
J
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
J
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
J
4/35 Doc ID 022960 Rev 2
L6564H Description
1 Description
The L6564H is a current-mode PFC controller operating in transition mode (TM) which
embeds the same features existing in the L6564 with the addition of a high voltage startup
source. These functions make the IC especially suitable for applications that must be
compliant with energy saving regulations and where the PFC preregulator works as the
master stage.
The highly linear multiplier, along with a special correction circuit that reduces crossover
distortion of the mains current, allows wide-range-mains operation with an extremely low
THD even over a large load range.
The output voltage is controlled by means of a voltage-mode error amplifier and an accurate
(1% @T
feedforward function (1/V
also considerably improves line transient response in the case of both mains drops and
surges (“bi-directional”).
In addition to overvoltage protection able to control the output voltage during transient
conditions, the IC also provides protection against feedback loop failures or erroneous
settings. Other onboard protection functions allow brownout conditions and boost inductor
saturation to be safely handled.
= 25 °C) internal voltage reference. The loop stability is optimized by the voltage
J
2
correction), which, in this IC, uses a proprietary technique that
The totem pole output stage, capable of a 600 mA source and 800 mA sink current, is
suitable for a high power MOSFET or IGBT drive. This, combined with the other features
and the possibility to operate with ST's proprietary fixed-off-time control, makes the device
an excellent solution for SMPS up to 400 W that requires compliance with EN61000-3-2 and
JEITA-MITI standards.
Doc ID 022960 Rev 2 5/35
Maximum ratings L6564H
2 Maximum ratings
2.1 Absolute maximum ratings
Table 1. Absolute maximum ratings
Symbol Pin Parameter Value Unit
V
HVS
I
HVS
V
CC
--- 1, 3, 6 Max. pin voltage (Ipin ≤
--- 2, 4, 5 Analog inputs and outputs -0.3 to 8 V
I
ZCD
VFF pin 5 Maximum withstanding voltage range
Other pins
1 to 4
6, 8, 11 to 14
2.2 Thermal data
Table 2. Thermal data
Symbol Parameter Value Unit
R
thJA
Ptot Power dissipation @T
T
T
Max. thermal resistance, junction-to-ambient 120 °C/W
Junction temperature operating range -40 to 150 °C
J
Storage temperature -55 to 150 °C
stg
8 Voltage range (referred to ground) -0.3 to 700 V
8 Output current Self-limited I
HVS
14 IC supply voltage (Icc ≤ 20 mA) Self-limited V
1 mA) Self-limited V
11 Zero current detector max. current
test condition: CDF-AEC-Q100-002
“human body model”
acceptance criteria: “normal performance”
= 50 °C 0.75 W
A
-10 (source)
10 (sink)
+/- 1750 V
+/- 2000 V
mA
6/35 Doc ID 022960 Rev 2
L6564H Pin connection
3 Pin connection
Figure 2. Pin connection
INV
COMP
MULT
CS
VFF
PFC_OK
N.C.
1
2
3
4
5
6
78
Table 3. Pin description
n° Name Function
Inverting input of the error amplifier. The information on the output voltage of the PFC pre-
1INV
2COMP
regulator is fed into the pin through a resistor divider. The pin normally features high
impedance.
Output of the error amplifier. A compensation network is placed between this pin and INV (pin
1) to achieve stability of the voltage control loop and ensure high power factor and low THD. To
avoid an uncontrolled rise of the output voltage at zero load, when the voltage on the pin falls
below 2.4 V the gate driver output is inhibited (burst-mode operation).
14
13
12
11
10
Vcc
GD
GND
ZCD
N.C.
9
N.C.
HVS
AM11476v1
3MULT
4CS
5VFF
Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor
divider and provides the sinusoidal reference to the current loop. The voltage on this pin is used
also to derive the information on the RMS mains voltage.
Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor,
the resulting voltage is applied to this pin and compared with an internal reference to determine
MOSFET turn-off. A second comparison level at 1.7 V detects abnormal currents (e.g. due to
boost inductor saturation) and, on this occurrence, activates a safety procedure that temporarily
stops the converter and limits the stress of the power components.
2
Second input to the multiplier for 1/V
connected from the pin to GND. They complete the internal peak-holding circuit that derives the
information on the RMS mains voltage. The voltage at this pin, a DC level equal to the peak
voltage on the MULT pin (3), compensates the control loop gain dependence on the mains
voltage. Never connect the pin directly to GND but with a resistor ranging from 100 KΩ
(minimum) to 2 MΩ (maximum).
Doc ID 022960 Rev 2 7/35
function. A capacitor and a parallel resistor must be
Pin connection L6564H
Table 3. Pin description (continued)
n° Name Function
PFC pre-regulator output voltage monitoring/disable function. This pin senses the output
voltage of the PFC pre-regulator through a resistor divider and is used for protection purposes.
If the voltage on the pin exceeds 2.5 V, the IC stops switching and restarts as the voltage on the
6PFC_OK
7 N.C. Not internally connected. Provision for clearance on the PCB to meet safety requirements.
8HVS
9 N.C. Not internally connected. Provision for clearance on the PCB to meet safety requirements.
pin falls below 2.4 V. However, if at the same time the voltage of the INV pin falls below 1.66 V,
a feedback failure is assumed. In this case the device is latched off. Normal operation can be
resumed only by cycling V
. bringing its value lower than 6 V before moving up to the turn-on
CC
threshold. If the voltage on this pin is brought below 0.23 V, the IC is shut down. To restart the
IC the voltage on the pin must go above 0.27 V. This can be used as a remote on/off control
input.
High voltage startup. The pin, able to withstand 700 V, is to be tied directly to the rectified mains
voltage. A 1 mA internal current source charges the capacitor connected between the V
(14) and the GND pin (12) until the voltage on the V
then shut down. Normally, the generator is re-enabled when the V
pin reaches the startup threshold, it is
CC
voltage falls below 6 V to
CC
CC
pin
ensure a low power throughput during short-circuit. Otherwise, when a latched protection is
tripped the generator is re-enabled as V
reaches the UVLO threshold to keep the latch
CC
supplied.
10 N.C. Not internally connected. Provision for clearance on the PCB to meet safety requirements.
11 ZCD
Boost inductor demagnetization sensing input for transition-mode operation. A negative-going
edge triggers MOSFET turn-on.
12 GND Ground. Current return for both the signal part of the IC and the gate driver.
Gate driver output. The totem pole output stage is able to drive Power MOSFETs and IGBTs
13 GD
with a peak current of 600 mA source and 800 mA sink. The high level voltage of this pin is
clamped at about 12 V to avoid excessive gate voltages.
Supply voltage of both the signal part of the IC and the gate driver. Sometimes a small bypass
14 V
CC
capacitor (0.1 µF typ.) to GND might be useful to get a clean bias voltage for the signal part of
the IC.
Figure 3. Typical system block diagram
PFC PRE-REGULATOR DC-DC CONVERTER
inac
V
PWM is turned off in case of PFC's
anomalous operation for safety
PWM or
L6564H
PFC can be handled off/on according
to the load c ondition to ease compliance
with energy saving regulations.
Resonant
CONTROLLER
V
outd c
AM11477v1
8/35 Doc ID 022960 Rev 2
L6564H Electrical characteristics
4 Electrical characteristics
(TJ = -25 to 125 °C, VCC= 12 V, CO = 1 nF between pin GD and GND, C
= 1 µF and RFF =
FF
1 MΩ between pin VFF and GND; unless otherwise specified.)
Table 4. Electrical characteristics
Symbol Parameter Test condition Min. Typ. Max. Unit
Supply voltage
V
CC
V
CCOn
V
CCOff
V
CCrestartVCC
Hys Hysteresis 2.3 2.7 V
V
Supply current
I
start-up
I
q
I
CC
I
qdis
I
q
High voltage startup generator
Operating range After turn-on 10.3 22.5 V
Turn-on threshold
Turn-off threshold
(1)
(1)
11 12 13 V
8.7 9.5 10.3 V
for resuming from latch OVP latched 5 6 7 V
Zener voltage Icc = 20 mA 22.5 25 28 V
Z
Startup current Before turn-on, VCC = 10 V 90 150 µA
Quiescent current After turn-on, V
= 1 V 4 5 mA
MULT
Operating supply current @ 70 kHz 5 6.0 mA
Idle state quiescent current
Quiescent current
V
V
V
V
V
> V
PFC_OK
INV<VFFD
PFC_OK<VPFC_OK_D
PFC_OK>VPFC_OK_S
COMP
PFC_OK_S
< 2.3 V
AND
OR
180 280 µA
1.5 2.2 mA
2.2 3 mA
V
HV
V
HVstart
I
charge
I
HV, ON
I
HV, OFF
V
CCrestartVCC
Breakdown voltage I
Start voltage IVCC < 100 µA 65 80 100 V
VCC charge current VHV > V
ON-state current VHV > V
OFF-state leakage current VHV = 400 V 40 µA
Multiplier input
I
MULT
V
MULT
V
CLAMP
Input bias current V
Linear operation range 0 to 3 V
Internal clamp level I
restart voltage
< 100 µA 700 V
HV
, VCC> 3 V 0.55 0.85 1 mA
Hvstart
, VCC> 3 V 1.6 mA
Hvstart
> V
V
HV
V
falling 5 6 7
CC
(1)
IC latched off 8.7 9.5 10.3
MULT
= 1 mA 9 9.5 V
MULT
, V
Hvstart
= 0 0.8
CC
V
= 0 to 3 V -0.2 -1 µA
Doc ID 022960 Rev 2 9/35
Electrical characteristics L6564H
Table 4. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
∆V
CS
------------- ---------
∆V
MULT
K
Output max. slope
Gain
M
Error amplifier
V
INV
Voltage feedback input
threshold
Line regulation VCC = 10.3 V to 22.5 V 2 5 mV
(2)
= 0 to 0.4 V, V
V
MULT
= upper clamp
V
COMP
V
= 1 V, V
MULT
T
= 25 °C 2.475 2.5 2.525
J
10.3 V < V
COMP
< 22.5 V
CC
= 1 V
VFF
1.33 1.66 V/V
= 4 V 0.375 0.45 0.525 V
(2)
2.455 2.545
V
I
INV
V
INVCLAMP
Input bias current V
Internal clamp level I
= 0 to 4 V -0.2 -1 µA
INV
= 1 mA 8 9 V
INV
Gv Voltage gain Open loop 60 80 dB
GB Gain-bandwidth product 1 MHz
I
COMP
V
COMP
Source current V
Sink current V
Upper clamp voltage I
Burst-mode voltage
Lower clamp voltage I
COMP
COMP
SOURCE
(1)
= 0.5 mA
SINK
= 4 V, V
= 4 V, V
= 2.4 V 2 4 mA
INV
= 2.6 V 2.5 4.5 mA
INV
= 0.5 mA 5.7 6.2 6.7 V
2.3 2.4 2.5
(1)
2.1 2.25 2.4
Current sense comparator
I
CS
t
LEB
td
(H-L)
V
CSclamp
Vcs
Input bias current VCS = 0 1 µA
Leading edge blanking 100 150 250 ns
Delay to output 100 200 300 ns
V
= upper clamp,
Current sense reference clamp
Current sense offset
ofst
COMP
V
MULT
V
MULT
V
MULT
=1 V, V
= 0, V
= 3 V, V
= 1 V
VFF
= 3 V 40 70
VFF
= 3 V 20
VFF
1.0 1.08 1.16 V
Boost inductor saturation detector
V
CS_th
I
INV
Threshold on current sense
E/A input pull-up current
(1)
After V
CS
restarting
> V
CS_th
, before
1.6 1.7 1.8 V
51013µA
mV
PFC_OK functions
I
PFC_OK
V
PFC_OK_C
V
PFC_OK_S
V
PFC_OK_R
Input bias current V
Clamp voltage I
OVP threshold
Restart threshold after OVP
PFC_OK
(1)
(1)
= 0 to 2.6 V -0.1 -1 µA
PFC_OK
= 1 mA 9 9.5 V
voltage rising 2.435 2.5 2.565 V
voltage falling 2.34 2.4 2.46 V
10/35 Doc ID 022960 Rev 2
L6564H Electrical characteristics
Table 4. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
V
PFC_OK_D
V
PFC_OK_D
V
PFC_OK_E
V
PFC_OK_E
V
FFD
Disable threshold
Disable threshold
Enable threshold
Enable threshold
V
feedback failure detection
INV
threshold (V
Zero current detector
INV
falling)
(1)
voltage falling 0.12 0.35 V
(1)
voltage falling TJ = 25 °C 0.17 0.23 0.29 V
(1)
voltage rising 0.15 0.38 V
(1)
voltage rising TJ = 25 °C 0.21 0.27 0.32 V
V
PFC_OK
> V
PFC_OK_S
1.61 1.66 1.71 V
V
ZCDH
V
ZCDL
V
ZCDA
V
ZCDT
I
ZCDb
I
ZCDsrc
I
ZCDsnk
Upper clamp voltage I
Lower clamp voltage I
Arming voltage
(positive-going edge)
Triggering voltage
(negative-going edge)
Input bias current V
Source current capability -2.5 -4 mA
Sink current capability 2.5 5 mA
Startup timer
t
START_DEL
t
START
Startup delay First cycle after wake-up 25 50 75 µs
Timer period 75 150 300 µs
Voltage feedforward
V
VFF
Linear operation range 1 3 V
∆V Dropout V
∆V
∆V
R
DISCH
V
V
VFF
VFF
DIS
EN
Line drop detection threshold Below peak value 40 70 100 mV
Line drop detection threshold
Internal discharge resistor
Disable threshold
Enable threshold
Gate driver
V
V
I
srcpk
I
snkpk
OL
OH
Output low voltage I
Output high voltage I
Peak source current -0.6 A
Peak sink current 0.8 A
MULTpk-VVFF
= 2.5 mA 5.0 5.7 V
ZCD
= - 2.5 mA -0.3 0 0.3 V
ZCD
1.1 1.4 1.9 V
0.5 0.7 0.9 V
= 1 to 4.5 V 1 µA
ZCD
Restart after V
VCC< V
V
CCOn
> or = to V
CC
Below peak value
= 25 °C
T
J
T
= 25 °C 7.5 10 12.5 kΩ
J
CS
CCOn
> V
CS_th
150 300 600
800 mV
20
50 70 90 mV
520
(1)
voltage falling 0.745 0.8 0.855 V
(1)
voltage rising 0.845 0.88 0.915 V
= 100 mA 0.6 1.2 V
sink
= 5 mA 9.8 10.3 V
source
Doc ID 022960 Rev 2 11/35
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