ST L6563S User Manual

L6563S

Enhanced transition-mode PFC controller

Features

■Tracking boost function

■Fast “bidirectional” input voltage feedforward (1/V2 correction)

■Interface for cascaded converter's PWM controller

■Remote ON/OFF control

■Accurate adjustable output overvoltage protection

■Protection against feedback loop disconnection (latched shutdown)

■Inductor saturation protection

■Low (≤ 100 µA) start-up current

■6 mA max. operating bias current

■1% (@ TJ = 25 °C) internal reference voltage

■-600/+800 mA totem pole gate driver with active pull-down during UVLO

■SO14 package

Figure 1. Block diagram

SO14

Applications

PFC pre-regulators for:

■High-end AC-DC adapter/charger

■Desktop PC, server, Web server

■IEC61000-3-2 or JEITA-MITI compliant SMPS, in excess of 400 W

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December 2010

Doc ID 16116 Rev 4

1/43

www.st.com

Contents	L6563S

Contents

1	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 6
2	Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		7
	2.1	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
	2.2	Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
3	Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
4	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
5	Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
6	Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		23
	6.1	Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
	6.2	Feedback failure protection (FFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
	6.3	Voltage feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
	6.4	THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
	6.5	Tracking boost function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
	6.6	Inductor saturation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
	6.7	Power management/housekeeping functions . . . . . . . . . . . . . . . . . . . . . .	31
7	Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		35
8	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		39
9	Ordering codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		41
10	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		42

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L6563S	List of table

List of table

Table 1. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 5. Summary of L6563S idle states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 6. SO14 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 7. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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List of figure	L6563S

List of figure

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. Typical system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. IC consumption vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 5. IC consumption vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6. Vcc Zener voltage vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Start-up and UVLO vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. Feedback reference vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 9. E/A output clamp levels vs TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 10. UVLO saturation vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 11. OVP levels vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 12. Inductor saturation threshold vs TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 13. Vcs clamp vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 14. ZCD sink/source capability vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 15. ZCD clamp level vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 16. TBO clamp vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 17. VVFF - VTBO dropout vs TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 18. IINV - ITBO current mismatch vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 19. IINV - ITBO mismatch vs ITBO current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 20. R discharge vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 21. Line drop detection threshold vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 22. VMULTpk - VVFF dropout vs TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 23. PFC_OK threshold vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 24. PFC_OK FFD threshold vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 25. PWM_LATCH high saturation vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 26. RUN threshold vs TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 27. PWM_STOP low saturation vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 28. Multiplier characteristics @ VFF = 1 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 29. Multiplier characteristics @ VFF = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 30. Multiplier gain vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 31. Gate drive clamp vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 32. Gate drive output saturation vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 33. Delay to output vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 34. Start-up timer period vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 35. Output voltage setting, OVP and FFP functions: internal block diagram . . . . . . . . . . . . . . 23 Figure 36. Voltage feedforward: squarer-divider (1/V2) block diagram and transfer characteristic . . 25 Figure 37. RFF·CFF as a function of 3rd harmonic distortion introduced in the input current . . . . . . . 26 Figure 38. THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 39. THD optimization: standard TM PFC controller (left side) and L6563S (right side) . . . . . . 28 Figure 40. Tracking boost block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 41. Tracking output voltage vs Input voltage characteristic with TBO . . . . . . . . . . . . . . . . . . . 30 Figure 42. Effect of boost inductor saturation on the MOSFET current and detection method . . . . . . 31 Figure 43. Interface circuits that let dc-dc converter's controller IC drive L6563S in burst mode . . . . 32 Figure 44. Interface circuits that let the L6563S switch on or off a PWM controller. . . . . . . . . . . . . . . 32 Figure 45. Interface circuits for power up sequencing when dc-dc has the SS function . . . . . . . . . . . 33 Figure 46. Interface circuits for actual power-up sequencing (master PFC) . . . . . . . . . . . . . . . . . . . . 33 Figure 47. Brownout protection (master PFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 48. Demonstration board EVL6563S-100W, wide-range mains: electrical schematic . . . . . . . 35

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L6563S	List of figure
Figure 49.	L6563S 100 W TM PFC demonstration board: compliance to EN61000-3-2 standard . . .	36
Figure 50.	L6563S 100 W TM PFC demonstration board: compliance to JEITA-MITI standard . . . . .	36
Figure 51. L6563S 100 W TM PFC demonstration board: input current waveform @230-50 Hz - 100 W
load	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	36
Figure 52. L6563S 100W TM PFC demonstration board: input current waveform @100 V-50 Hz - 100
W load	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	36
Figure 53.	EVL6563S-250W TM PFC demonstration board: electrical schematic . . . . . . . . . . . . . . .	37
Figure 54.	EVL6563S-400W FOT PFC demonstration board: electrical schematic . . . . . . . . . . . . . .	37
Figure 55.	EVL6563S-ZRC200W 200W PFC pre-regulator with ripple-free input current: electrical sche-
matic	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	38
Figure 56.	Package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40

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Description	L6563S

1 Description

The L6563S is a current-mode PFC controller operating in transition mode (TM). Coming with the same pin-out as its predecessor L6563, it offers improved performance and additional functions.

The highly linear multiplier, along with a special correction circuit that reduces crossover distortion of the mains current, allows wide-range-mains operation with an extremely low THD even over a large load range.

The output voltage is controlled by means of a voltage-mode error amplifier and an accurate (1% @ TJ = 25 °C) internal voltage reference. Loop’s stability is optimized by the voltage feedforward function (1/V2 correction), which in this IC uses a proprietary technique that considerably improves line transient response as well in case of mains both drops and surges (“bidirectional”).

Additionally, the IC provides the option for tracking boost operation, i.e. the output voltage is changed tracking the mains voltage.

The device includes disable functions suitable for remote ON/OFF control both in systems where the PFC pre-regulator works as a master and in those where it works as a slave. In addition to an overvoltage protection able to keep the output voltage under control during transient conditions, the IC is provided also with a protection against feedback loop failures or erroneous settings. Other on-board protection functions allow that brownout conditions and boost inductor saturation can be safely handled.

An interface with the PWM controller of the DC-DC converter supplied by the PFC preregulator is provided: the purpose is to stop the operation of the converter in case of anomalous conditions for the PFC stage (feedback loop failure, boost inductor’s core saturation, etc.) and to disable the PFC stage in case of light load for the DC-DC converter, so as to make it easier to comply with energy saving norms (Blue Angel, EnergyStar, Energy2000, etc.).

The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable for big MOSFET or IGBT drive. This, combined with the other features and the possibility to operate with ST’s proprietary Fixed-Off-Time control, makes the device an excellent solution for SMPS up to 400 W that need to be compliant with EN61000-3-2 and JEITA-MITI standards.

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L6563S	Maximum ratings

2 Maximum ratings

2.1Absolute maximum ratings

	Table 1.	Absolute maximum ratings
	Symbol	Pin	Parameter	Value	Unit
	Vcc	14	IC supply voltage (Icc = 20 mA)	self-limited	V
	---	1, 3, 7	Max. pin voltage (Ipin =1 mA)	Self-limited	V
	---	2, 4 to 6, 8, 10	Analog inputs and outputs	-0.3 to 8	V
	VPWM_STOP	9	Analog output	-0.3 to Vcc	V
	IPWM_STOP	9	Max. sink current	3	mA
	IZCD	11	Zero current detector max. current	-10 (source)	mA
				10 (sink)
	VFF pin	5	Maximum withstanding voltage range	+/- 1250	V
			test condition: CDF-AEC-Q100-002
		1 to 4
	Other pins		“human body model”	+/- 2000	V
		6 to 14
			Acceptance criteria: “normal performance”

2.2Thermal data

Table 2.	Thermal data
Symbol	Parameter	Value	Unit
RthJA	Max. thermal resistance, junction-to-ambient	120	°C/W
Ptot	Power dissipation @TA = 50 °C	0.75	W
TJ	Junction temperature operating range	-40 to 150	°C
Tstg	Storage temperature	-55 to 150	°C

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Pin connection	L6563S

3 Pin connection

Figure 2. Pin connection

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	Table 3.		Pin description
	n°	Name		Function
				Inverting input of the error amplifier. The information on the output voltage of the PFC pre-
				regulator is fed into the pin through a resistor divider.
	1		INV	The pin normally features high impedance but, if the tracking boost function is used, an internal
				current generator programmed by TBO (pin 6) is activated. It sinks current from the pin to
				change the output voltage so that it tracks the mains voltage.
				Output of the error amplifier. A compensation network is placed between this pin and INV (pin
	2	COMP		1) to achieve stability of the voltage control loop and ensure high power factor and low THD.
				To avoid uncontrolled rise of the output voltage at zero load, when the voltage on the pin falls
				below 2.4 V the gate driver output will be inhibited (burst-mode operation).
				Mains input to the multiplier. This pin is connected to the rectified mains voltage via a resistor
	3	MULT		divider and provides the sinusoidal reference to the current loop. The voltage on this pin is used
				also to derive the information on the RMS mains voltage.
				Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor,
				the resulting voltage is applied to this pin and compared with an internal reference to determine
	4		CS	MOSFET’s turn-off.
				A second comparison level at 1.7 V detects abnormal currents (e.g. due to boost inductor
				saturation) and, on this occurrence, activates a safety procedure that temporarily stops the
				converter and limits the stress of the power components.
				Second input to the multiplier for 1/V2 function. A capacitor and a parallel resistor must be
				connected from the pin to GND. They complete the internal peak-holding circuit that derives the
	5		VFF	information on the RMS mains voltage. The voltage at this pin, a dc level equal to the peak
				voltage on pin MULT (3), compensates the control loop gain dependence on the mains voltage.
				Never connect the pin directly to GND but with a resistor ranging from 100 kΩ (minimum)
				to 2 MΩ (maximum).
				Tracking boost function. This pin provides a buffered VFF voltage. A resistor connected
	6		TBO	between this pin and GND defines a current that is sunk from pin INV (#1). In this way, the
				output voltage is changed proportionally to the mains voltage (tracking boost). If this function is
				not used leave this pin open.

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L6563S			Pin connection
Table 3.		Pin description (continued)
n°	Name		Function
			PFC pre-regulator output voltage monitoring/disable function. This pin senses the output
			voltage of the PFC pre-regulator through a resistor divider and is used for protection purposes.
			If the voltage on the pin exceeds 2.5 V the IC stops switching and restarts as the voltage on the
			pin falls below 2.4 V. However, if at the same time the voltage of the INV pin falls below 1.66V, a
7	PFC_OK		feedback failure is assumed. In this case the device is latched off and the pin PWM_LATCH (#8)
			is asserted high. Normal operation can be resumed only by cycling Vcc bringing its value lower
			than 6V before to move up the Turn on threshold.
			If the voltage on this pin is brought below 0.23 V the IC is shut down. To restart the IC the
			voltage on the pin must go above 0.27 V. This can be used as a remote on/off control input.
			Output pin for fault signaling. During normal operation this pin features high impedance. If a
			feedback failure is detected (PFC_OK > 2.5 V and INV< 1.66V) the pin is asserted high.
8	PWM_LATCH		Normally, this pin is used to stop the operation of the dc-dc converter supplied by the PFC pre-
			regulator by invoking a latched disable of its PWM controller. If not used, the pin will be left
			floating.
			Output pin for fault signaling. During normal operation this pin features high impedance. If the
			IC is disabled by a voltage below 0.8 V on pin RUN (#10) the voltage on the pin is pulled to
9	PWM_STOP		ground. Normally, this pin is used to temporarily stop the operation of the dc-dc converter
			supplied by the PFC pre-regulator by disabling its PWM controller. A typical usage of this
			function is brownout protection in systems where the PFC pre-regulator is the master stage. If
			not used, the pin will be left floating.
			Remote ON/OFF control. A voltage below 0.8V shuts down (not latched) the IC and brings its
10		RUN	consumption to a considerably lower level. PWM_STOP is asserted low. The IC restarts as the
			voltage at the pin goes above 0.88 V. Connect this pin to pin VFF (#5) either directly or through
			a resistor divider to use this function as brownout (AC mains undervoltage) protection.
11		ZCD	Boost inductor’s demagnetization sensing input for transition-mode operation. A negative-going
			edge triggers MOSFET’s turn-on.
12		GND	Ground. Current return for both the signal part of the IC and the gate driver.
			Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s
13		GD	with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is
			clamped at about 12 V to avoid excessive gate voltages.
			Supply voltage of both the signal part of the IC and the gate driver. Sometimes a small bypass
14		Vcc	capacitor (0.1 µF typ.) to GND might be useful to get a clean bias voltage for the signal part of
			the IC.

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Pin connection	L6563S
Figure 3. Typical system block diagram
0 02% 2%'5,!4/2	$# $# #/.6%24%2
6INAC	6OUTDC

07IS TURNEDDOFF IN CASE OF 0gS ANOMALOUS OPERATION FOR SAFETY

07OR , 3( 2ESONANT

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0&CAN BE TURNED OFF ATTLIGHT

LOAD TO EASE COMPLIANCECWITH

ENERGYYSAVING REGULATIONS

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10/43

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L6563S	Electrical characteristics

4 Electrical characteristics

TJ = -25 to 125 °C, VCC = 12 V, CO = 1 nF between pin GD and GND, CFF = 1 µF and RFF = 1 MΩ between pin VFF and GND; unless otherwise specified.

Table 4.

Electrical characteristics

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

Supply voltage

Vcc

Operating range

After turn-on

10.3

22.5

V

VccOn

Turn-on threshold

(1)

11

12

13

V

VccOff

Turn-off threshold

(1)

8.7

9.5

10.3

V

Vccrestart

Vcc for resuming from latch

OVP latched

5

6

7

V

Hys

Hysteresis

2.3

2.7

V

VZ

Zener voltage

Icc = 20 mA

22.5

25

28

V

Supply current

Istart-up

Start-up current

Before turn-on, Vcc = 10 V

90

150

µA

Iq

Quiescent current

After turn-on, VMULT = 1 V

4

5

mA

ICC

Operating supply current

@ 70 kHz

5

6.0

mA

VPFC_OK > VPFC_OK_S AND

180

280

µA

Iqdis

Idle state quiescent current

VINV < VPFC_OK – VFFD

VPFC_OK < VPFC_OK_D OR

1.5

2.2

mA

VRUN < VDIS

Iq

Quiescent current

VPFC_OK > VPFC_OK_S OR

2.2

3

mA

VCOMP < 2.3 V

Multiplier input

IMULT

Input bias current

VMULT = 0 to 3 V

-0.2

-1

µA

VMULT

Linear operation range

0 to 3

V

VCLAMP

Internal clamp level

IMULT = 1 mA

9

9.5

V

Vcs

Output max. slope

VMULT =0 to 0.4 V, VVFF = 0.8 V

2.2

2.34

V/V

VMULT

VCOMP = Upper clamp

K

M

Gain (2)

V

MULT

= 1 V, V

COMP

= 4 V

0.375

0.45

0.525

1/V

Error amplifier

VINV

Voltage feedback input threshold

TJ = 25 °C

2.475

2.5

2.525

V

10.3 V < Vcc < 22.5 V (3)

2.455

2.545

Line regulation

Vcc = 10.3 V to 22.5 V

2

5

mV

IINV

Input bias current

TBO open, VINV = 0 to 4 V

-0.2

-1

µA

VINVCLAMP

Internal clamp level

IINV = 1 mA

8

9

V

Doc ID 16116 Rev 4

11/43

Electrical characteristics							L6563S
Table 4.	Electrical characteristics	(continued)
Symbol	Parameter			Test condition	Min.	Typ.	Max.	Unit
Gv	Voltage gain		Open loop		60	80		dB
GB	Gain-bandwidth product					1		MHz
ICOMP	Source current		VCOMP = 4 V, VINV = 2.4 V		2	4		mA
	Sink current		VCOMP = 4 V, VINV = 2.6 V		2.5	4.5		mA
	Upper clamp voltage		ISOURCE = 0.5 mA		5.7	6.2	6.7
VCOMP	Burst-mode voltage		(3)		2.3	2.4	2.5	V
	Lower clamp voltage		I	= 0.5 mA (3)	2.1	2.25	2.4
			SINK
Current sense comparator
ICS	Input bias current		VCS = 0				1	µA
tLEB	Leading edge blanking				100	150	250	ns
td(H-L)	Delay to output				100	200	300	ns
VCSclamp	Current sense reference clamp		VCOMP = Upper clamp,		1.0	1.08	1.16	V
			VMULT =1 V VVFF = 1 V
Vcsofst	Current sense offset		VMULT = 0, VVFF = 3 V			40	70	mV
			VMULT = 3 V, VVFF = 3 V			20
Boost inductor saturation detector
VCS_th	Threshold on current sense		(3)		1.6	1.7	1.8	V
IINV	E/A input pull-up current		After VCS > VCS_th, before restarting		5	10	13	µA
PFC_OK functions
IPFC_OK	Input bias current		VPFC_OK = 0 to 2.6 V			-0.1	-1	µA
VPFC_OK_C	Clamp voltage		IPFC_OK = 1 mA		9	9.5		V
VPFC_OK_S	OVP threshold		(1) voltage rising		2.435	2.5	2.565	V
VPFC_OK_R	Restart threshold after OVP		(1) voltage falling		2.34	2.4	2.46	V
VPFC_OK_D	Disable threshold		(1) voltage falling		0.12		0.35	V
VPFC_OK_D	Disable threshold		(1) voltage falling TJ = 25 °C		0.17	0.23	0.29	V
VPFC_OK_E	Enable threshold		(1) voltage rising		0.15		0.38	V
VPFC_OK_E	Enable threshold		(1) voltage rising Tj = 25 °C		0.21	0.27	0.32	V
VFFD	Feedback failure detection		VPFC_OK > VPFC_OK_S		1.61	1.66	1.71	mV
	threshold (VINV falling)
Zero current detector
VZCDH	Upper clamp voltage		IZCD = 2.5 mA		5.0	5.7		V
VZCDL	Lower clamp voltage		IZCD = - 2.5 mA		-0.3	0	0.3	V
VZCDA	Arming voltage				1.1	1.4	1.9	V
	(positive-going edge)

12/43

Doc ID 16116 Rev 4

L6563S				Electrical characteristics
Table 4.	Electrical characteristics	(continued)
Symbol	Parameter		Test condition		Min.	Typ.	Max.	Unit
VZCDT	Triggering voltage				0.5	0.7	0.9	V
	(negative-going edge)
IZCDb	Input bias current		VZCD = 1 to 4.5 V				1	µA
IZCDsrc	Source current capability				-2.5	-4		mA
IZCDsnk	Sink current capability				2.5	5		mA
Tracking boost function
V	Dropout voltage VVFF-VTBO		ITBO = 0.2 mA		-20		20	mV
ITBO	Linear operation				0		0.2	mA
	IINV-ITBO current mismatch		ITBO = 25 µA to 0.2mA		-5.5		+1.0	%
	IINV-ITBO current mismatch		ITBO = 25 µA to 0.2mA		-4.0		+0	%
			TJ = 25 °C
VTBOclamp	Clamp voltage		(3) VVFF = 4 V		2.9	3	3.1	V
ITBO_Pull	Pull-up current		VTBO = 1 V				2	μA
			VFF = VMULT = 0 V
PWM_STOP
Ileak	High level leakage current		VPWM_STOP = Vcc				1	µA
VL	Low level		IPWM_STOP = 0.5 mA				1	V
RUN function
IRUN	Input bias current		VRUN = 0 to 3 V				-1	µA
VDIS	Disable threshold		(3) voltage falling		0.745	0.8	0.855	V
VEN	Enable threshold		(3) voltage rising		0.845	0.88	0.915	V
Start-up timer
tSTART_DEL	Start-up delay		First cycle after wake-up		25	50	75	µs
tSTART	Timer period				75	150	300	µs
			Restart after VCS > VCS_th		150	300	600
Voltage feedforward
VVFF	Linear operation range				0.8		3	V
V	Dropout VMULTpk-VVFF		Vcc < VccOn				800	mV
			Vcc > or = to VccOn				20
VVFF	Line drop detection threshold		Below peak value		40	70	100	mV
VVFF	Line drop detection threshold		Below peak value		50	70	90	mV
			TJ = 25 °C
RDISCH	Internal discharge resistor		TJ = 25 °C		7.5	10	12.5	kΩ
					5		20

Doc ID 16116 Rev 4

13/43