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L6563
L6563A
Advanced transition-mode PFC controller
Features
■Very precise adjustable output overvoltage protection
■Tracking boost function
■Protection against feedback loop failure (Latched shutdown)
■Interface for cascaded converter's PWM controller
■Input voltage feedforward (1/V2)
■Inductor saturation detection (L6563 only)
■Remote ON/OFF control
■Low (≤ 90µA) start-up current
■5mA max. quiescent current
■1.5% (@ TJ = 25°C) internal reference voltage
■-600/+800 mA totem pole gate driver with active pull-down during UVLO
■SO14 package
Figure 1. Block diagram
SO-14
Applications
PFC pre-regulators for:
■HI-END AC-DC adapter/charger
■Desktop PC, server, WEB server
■IEC61000-3-2 OR JEIDA-MITI compliant SMPS, in excess of 350W
Table 1. Device summary
Part number |
Package |
Packaging |
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L6563 |
SO-14 |
Tube |
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L6563TR |
SO-14 |
Tape & Reel |
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L6563A |
SO-14 |
Tube |
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L6563ATR |
SO-14 |
Tape & Reel |
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INV |
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COMP |
MULT |
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VFF |
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1 |
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2 |
3 |
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5 |
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TRACKING |
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Ideal diode |
1 / V 2 |
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BOOST |
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LINE VOLTAGE |
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- |
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TBO |
6 |
1:1 |
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MULTIPLIER |
FEEDFORWARD |
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+ |
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CURRENT |
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2.5V |
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4 |
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MIRROR |
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LEADING-EDGE |
CS |
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1.7V |
BLANKING |
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1:1 |
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Voltage |
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VOLTAGE |
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references |
- |
+ |
- |
+ |
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BUFFER |
from |
REGULATOR |
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3V |
VFF |
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Vbias |
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INDUCTOR |
Q |
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VCC |
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(INTERNAL SUPPLY BUS) |
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SATURATION |
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14 |
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DETECTION |
SAT |
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VCC |
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( not in L6563A) |
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15 V |
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R |
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Q |
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R1 |
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UVLO |
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COMPARATOR |
S |
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13 |
GD |
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GND |
12 |
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+ |
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Driver |
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R2 |
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- |
UVLO |
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VREF2 |
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Starter |
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11 |
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ZERO CURRENT |
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OFF |
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1.4V |
- |
DETECTOR |
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STARTER |
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0.2V |
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ZCD |
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+ |
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0.7V |
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0.26V |
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+ |
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10 |
- |
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PFC_OK |
RUN |
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- |
7 |
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DISABLE |
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SAT |
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LATCH |
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+ |
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+ |
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0.52V |
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0.6V |
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Vbias |
FEEDBACK |
- |
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ON/OFF CONTROL |
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FAILURE |
2.5V |
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(BROWNOUT DETECTION) |
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9 |
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8 |
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PROTECTION |
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PWM_STOP |
PWM_LATCH |
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March 2007 |
Rev 4 |
1/39 |
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www.st.com
Contents |
L6563 - L6563A |
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Contents
1 |
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 3 |
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1.1 |
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
4 |
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1.2 |
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
4 |
2 |
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
6 |
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3 |
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
6 |
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4 |
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
7 |
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5 |
Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
11 |
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6 |
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
16 |
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6.1 |
Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
16 |
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6.2 |
Feedback Failure Protection (FFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
18 |
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6.3 |
Voltage Feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
18 |
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6.4 |
THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
21 |
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6.5 |
Tracking Boost function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
23 |
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6.6 |
Inductor saturation detection (L6563 only) . . . . . . . . . . . . . . . . . . . . . . . . |
27 |
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6.7 |
Power management/housekeeping functions . . . . . . . . . . . . . . . . . . . . . . |
28 |
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6.8 |
Summary of L6563/A idle states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
31 |
7 |
Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
32 |
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8 |
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
37 |
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9 |
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
38 |
2/39
L6563 - L6563A |
Description |
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1 Description
The device is a current-mode PFC controller operating in Transition Mode (TM). Based on the core of a standard TM PFC controller, it offers improved performance and additional functions.
The highly linear multiplier, along with a special correction circuit that reduces crossover distortion of the mains current, allows wide-range-mains operation with an extremely low THD even over a large load range.
The output voltage is controlled by means of a voltage-mode error amplifier and a precise (1.5% @TJ = 25°C) internal voltage reference. The stability of the loop and the transient response to sudden mains voltage changes are improved by the voltage feedforward function (1/V2 correction).
Additionally, the IC provides the option for tracking boost operation (where the output voltage is changed tracking the mains voltage). The device features extremely low consumption (≤ 90 µA before start-up and ≤ 5 mA running).
In addition to an effective two-step OVP that handles normal operation overvoltages, the IC provides also a protection against feedback loop failures or erroneous output voltage setting.
In the L6563 a protection is added to stop the PFC stage in case the boost inductor saturates. This function is not included in the L6563A. This is the only difference between the two part numbers.
An interface with the PWM controller of the DC-DC converter supplied by the PFC preregulator is provided: the purpose is to stop the operation of the converter in case of anomalous conditions for the PFC stage (feedback loop failure, boost inductor's core saturation) in the L6563 only and to disable the PFC stage in case of light load for the DCDC converter, so as to make it easier to comply with energy saving norms (Blue Angel, EnergyStar, Energy2000, etc.). The device includes disable functions suitable for remote ON/OFF control both in systems where the PFC pre-regulator works as a master and in those where it works as a slave.
The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable to drive high current MOSFETs or IGBTs. This, combined with the other features and the possibility to operate with the proprietary Fixed-Off-Time control, makes the device an excellent low-cost solution for EN61000-3-2 compliant SMPS in excess of 350W.
Figure 2. Typical system block diagram
PFC PRE-REGULATOR |
Vinac |
DC-DC CONVERTER |
Voutdc |
PWM is turned off in case of PFC’s anomalous operation for safety
L6563 L6563A
PWM or Resonant CONTROLLER
PFC can be turned off at light load to ease compliance with energy saving regulations.
3/39
Description |
L6563 - L6563A |
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1.1Pin connection
Figure 3. Pin connection (top view)
INV |
1 |
14 |
Vcc |
COMP |
2 |
13 |
GD |
MULT |
3 |
12 |
GND |
CS |
4 |
11 |
ZCD |
VFF |
5 |
10 |
RUN |
TBO |
6 |
9 |
PWM_STOP |
PFC_OK |
7 |
8 |
PWM_LATCH |
1.2Pin description
Table 2. Pin description
Pin N° |
Name |
Description |
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Inverting input of the error amplifier. The information on the output voltage of the PFC pre- |
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regulator is fed into the pin through a resistor divider. |
1 |
INV |
The pin normally features high impedance but, if the tracking boost function is used, an |
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internal current generator programmed by TBO (pin 6) is activated. It sinks current from the |
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pin to change the output voltage so that it tracks the mains voltage. |
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Output of the error amplifier. A compensation network is placed between this pin and INV |
2 |
COMP |
(pin 1) to achieve stability of the voltage control loop and ensure high power factor and low |
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THD. |
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Main input to the multiplier. This pin is connected to the rectified mains voltage via a |
3 |
MULT |
resistor divider and provides the sinusoidal reference to the current loop. The voltage on |
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this pin is used also to derive the information on the RMS mains voltage. |
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Input to the PWM comparator. The current flowing in the MOSFET is sensed through a |
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resistor, the resulting voltage is applied to this pin and compared with an internal reference |
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to determine MOSFET’s turn-off. |
4 |
CS |
A second comparison level at 1.7V detects abnormal currents (e.g. due to boost inductor |
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saturation) and, on this occurrence, shuts down the IC, reduces its consumption almost to |
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the start-up level and asserts PWM_LATCH (pin 8) high. This function is not present in the |
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L6563A. |
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Second input to the multiplier for 1/V2 function. A capacitor and a parallel resistor must be |
5 |
VFF |
connected from the pin to GND. They complete the internal peak-holding circuit that |
derives the information on the RMS mains voltage. The voltage at this pin, a DC level equal |
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to the peak voltage at pin MULT (pin 3), compensates the control loop gain dependence on |
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the mains voltage. Never connect the pin directly to GND. |
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4/39
L6563 - L6563A |
Description |
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Table 2. Pin description (continued) |
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Pin N° |
Name |
Description |
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Tracking Boost function. This pin provides a buffered VFF voltage. A resistor connected |
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6 |
TBO |
between this pin and GND defines a current that is sunk from pin INV (pin 1). In this way, |
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the output voltage is changed proportionally to the mains voltage (tracking boost). If this |
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function is not used leave this pin open. |
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PFC pre-regulator output voltage monitoring/disable function. This pin senses the output |
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voltage of the PFC pre-regulator through a resistor divider and is used for protection |
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purposes. If the voltage at the pin exceeds 2.5V the IC is shut down, its consumption goes |
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almost to the start-up level and this condition is latched. PWM_LATCH pin is asserted high. |
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7 |
PFC_OK |
Normal operation can be resumed only by cycling the Vcc. This function is used for |
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protection in case the feedback loop fails. |
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If the voltage on this pin is brought below 0.2V the IC is shut down and its consumption is |
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considerably reduced. To restart the IC the voltage on the pin must go above 0.26V. If these |
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functions are not needed, tie the pin to a voltage between 0.26 and 2.5 V. |
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Output pin for fault signaling. During normal operation this pin features high impedance. If |
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either a voltage above 2.5V at PFC_OK (pin 7) or a voltage above 1.7V on CS (pin 4) of |
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8 |
PWM_LATCH |
L6563 is detected the pin is asserted high. Normally, this pin is used to stop the operation |
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of the DC-DC converter supplied by the PFC pre-regulator by invoking a latched disable of |
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its PWM controller. If not used, the pin will be left floating. |
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Output pin for fault signaling. During normal operation this pin features high impedance. If |
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the IC is disabled by a voltage below 0.5V on RUN (pin 10) the voltage at the pin is pulled |
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9 |
PWM_STOP |
to ground. Normally, this pin is used to temporarily stop the operation of the DC-DC |
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converter supplied by the PFC pre-regulator by disabling its PWM controller. If not used, |
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the pin will be left floating. |
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Remote ON/OFF control. A voltage below 0.52V shuts down (not latched) the IC and |
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brings its consumption to a considerably lower level. PWM_STOP is asserted low. The IC |
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10 |
RUN |
restarts as the voltage at the pin goes above 0.6V. Connect this pin to VFF (pin 5) either |
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directly or through a resistor divider to use this function as brownout (AC mains |
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undervoltage) protection, tie to INV (pin 1) if the function is not used. |
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11 |
ZCD |
Boost inductor’s demagnetization sensing input for transition-mode operation. A negative- |
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going edge triggers MOSFET’s turn-on. |
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12 |
GND |
Ground. Current return for both the signal part of the IC and the gate driver. |
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Gate driver output. The totem pole output stage is able to drive power MOSFET’s and |
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13 |
GD |
IGBT’s with a peak current of 600 mA source and 800 mA sink. The high-level voltage of |
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this pin is clamped at about 12V to avoid excessive gate voltages. |
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14 |
VCC |
Supply Voltage of both the signal part of the IC and the gate driver. |
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5/39
Absolute maximum ratings |
L6563 - L6563A |
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2 Absolute maximum ratings
Table 3. Absolute maximum ratings
Symbol |
Pin |
Parameter |
Value |
Unit |
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VCC |
14 |
IC supply voltage (Icc = 20mA) |
self-limited |
V |
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--- |
2, 4 to 6, 8 |
Analog inputs & outputs |
-0.3 to 8 |
V |
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to 10 |
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--- |
1, 3, 7 |
Max. pin voltage (Ipin = 1 mA) |
Self-limited |
V |
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IPWM_STOP |
10 |
Max. sink current |
3 |
mA |
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IZCD |
9 |
Zero current detector max. current |
-10 (source) |
mA |
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10 (sink) |
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PTOT |
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Power dissipation @TA = 50°C |
0.75 |
W |
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TJ |
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Junction temperature operating range |
-25 to 150 |
°C |
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TSTG |
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Storage temperature |
-55 to 150 |
°C |
3 Thermal data
Table 4. Thermal data
Symbol |
Parameter |
Value |
Unit |
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RthJA |
Maximum thermal resistance junction-ambient |
120 |
°C/W |
6/39
L6563 - L6563A |
Electrical characteristics |
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4 Electrical characteristics
Table 5. Electrical characteristics
( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF between pin GD and GND, CFF =1µF between pin VFF and GND; unless otherwise specified)
Symbol |
Parameter |
Test condition |
Min |
Typ |
Max |
Unit |
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Supply voltage |
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Vcc |
Operating range |
After turn-on |
10.3 |
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22 |
V |
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VccOn |
Turn-on threshold |
(1) |
11 |
12 |
13 |
V |
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VccOff |
Turn-off threshold |
(1) |
8.7 |
9.5 |
10.3 |
V |
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Hys |
Hysteresis |
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2.3 |
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2.7 |
V |
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VZ |
Zener Voltage |
Icc = 20 mA |
22 |
25 |
28 |
V |
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Supply current |
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Istart-up |
Start-up current |
Before turn-on, Vcc = 10V |
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50 |
90 |
µA |
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Iq |
Quiescent current |
After turn-on |
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3 |
5 |
mA |
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ICC |
Operating supply current |
@ 70kHz |
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3.8 |
5.5 |
mA |
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Latched by PFC_OK > Vthl or |
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180 |
250 |
µA |
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Idle state quiescent |
Vcs > VCSdis |
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Iqdis |
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Current |
Disabled by PFC_OK < Vth or |
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1.5 |
2.2 |
mA |
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RUN < VDIS |
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Iq |
Quiescent current |
During static/dynamic OVP |
|
2 |
3 |
mA |
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Multiplier input |
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IMULT |
Input bias current |
VMULT = 0 to 3 V |
|
-0.2 |
-1 |
µA |
|
VMULT |
Linear operation range |
|
0 to 3 |
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V |
|
VCLAMP |
Internal clamp level |
IMULT = 1 mA |
9 |
9.5 |
|
V |
|
∆Vcs |
Output max. slope |
VMULT=0 to 0.5V, VFF=0.8V |
2.2 |
2.34 |
|
V/V |
|
--------------------- |
VCOMP = Upper clamp |
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∆VMULT |
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KM |
Gain (3) |
VMULT = 1 V, VCOMP= 4 V, |
0.375 |
0.45 |
0.525 |
V |
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VVFF = VMULT |
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Error amplifier |
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VINV |
Voltage feedback input |
TJ = 25 °C |
2.465 |
2.5 |
2.535 |
V |
|
threshold |
10.3 V < Vcc < 22 V (2) |
2.44 |
|
2.56 |
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Line regulation |
Vcc = 10.3 V to 22V |
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2 |
5 |
mV |
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IINV |
Input bias current |
TBO open, VINV = 0 to 4 V |
|
-0.2 |
-1 |
µA |
7/39
Electrical characteristics |
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L6563 - L6563A |
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Table 5. Electrical characteristics |
(continued) |
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( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF between pin GD and GND, CFF =1µF between pin VFF |
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and GND; unless otherwise specified) |
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Symbol |
Parameter |
Test condition |
Min |
Typ |
|
Max |
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Unit |
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VINVCLAMP |
Internal clamp level |
IINV = 1 mA |
9 |
9.5 |
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V |
Gv |
Voltage gain |
Open loop |
60 |
80 |
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dB |
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GB |
Gain-bandwidth product |
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1 |
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MHz |
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ICOMP |
Source current |
VCOMP = 4V, VINV = 2.4 V |
-2 |
-3.5 |
|
-5 |
|
mA |
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Sink current |
VCOMP = 4V, VINV = 2.6 V |
2.5 |
4.5 |
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mA |
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VCOMP |
Upper clamp voltage |
ISOURCE = 0.5 mA |
5.7 |
6.2 |
|
6.7 |
|
V |
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Lower clamp voltage |
ISINK = 0.5 mA (2) |
2.1 |
2.25 |
|
2.4 |
|
V |
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Current sense comparator |
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ICS |
Input bias current |
VCS = 0 |
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-1 |
|
µA |
tLEB |
Leading edge blanking |
|
100 |
200 |
|
300 |
|
ns |
td(H-L) |
Delay to output |
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120 |
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ns |
VCSclamp |
Current sense reference |
VCOMP = Upper clamp, |
1.0 |
1.08 |
|
1.16 |
|
V |
clamp |
VVFF = VMULT =0.5V |
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Vcsoffset |
Current sense offset |
VMULT = 0, VVFF = 3V |
|
25 |
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mV |
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VMULT = 3V, VVFF = 3V |
|
5 |
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VCSdis |
Ic latch-off level (L6563 |
(2) |
1.6 |
1.7 |
|
1.8 |
|
V |
only) |
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Output overvoltage |
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IOVP |
Dynamic OVP triggering |
|
17 |
20 |
|
23 |
|
µA |
current |
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Hys |
Hysteresis |
(4) |
|
15 |
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µA |
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Static OVP threshold |
(2) |
2 |
2.15 |
|
2.3 |
|
V |
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Voltage feedforward |
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VVFF |
Linear operation range |
RFF = 47 kΩ to GND |
0.5 |
|
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3 |
|
V |
∆V |
Dropout |
|
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|
20 |
|
mV |
VMULTpk-VVFF |
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|||
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|
8/39
L6563 - L6563A |
|
Electrical characteristics |
|||||
|
|
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|
|
|
|
|
Table 5. Electrical characteristics |
(continued) |
|
|
|
|
|
|
( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF between pin GD and GND, CFF =1µF between pin VFF |
|
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and GND; unless otherwise specified) |
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Symbol |
Parameter |
Test condition |
Min |
Typ |
Max |
|
Unit |
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|
Zero current detector |
|
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VZCDH |
Upper clamp voltage |
IZCD = 2.5 mA |
5.0 |
5.7 |
|
|
V |
VZCDL |
Lower clamp voltage |
IZCD = - 2.5 mA |
-0.3 |
0 |
0.3 |
|
V |
VZCDA |
Arming voltage |
(4) |
|
1.4 |
|
|
V |
(positive-going edge) |
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VZCDT |
Triggering voltage |
(4) |
|
0.7 |
|
|
V |
(negative-going edge) |
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IZCDb |
Input bias current |
VZCD = 1 to 4.5 V |
|
|
1 |
|
µA |
IZCDsrc |
Source current capability |
|
-2.5 |
|
|
|
mA |
IZCDsnk |
Sink current capability |
|
2.5 |
|
|
|
mA |
Tracking boost function |
|
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∆V |
Dropout voltage |
ITBO = 0.25 mA |
|
|
20 |
|
mV |
VVFF - VTBO |
|
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|
ITBO |
Linear operation |
|
0 |
|
0.25 |
|
mA |
|
IINV - ITBO current |
ITBO = 25 µA to 0.25 mA |
-3.5 |
|
3.5 |
|
% |
|
mismatch |
|
|
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|
VTBOclamp |
Clamp voltage |
VVFF = 4V (2) |
2.9 |
3 |
3.1 |
|
V |
PFC_OK |
|
|
|
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|
|
|
Vthl |
Latch-off threshold |
Voltage rising (2) |
2.4 |
2.5 |
2.6 |
|
V |
Vth |
Disable threshold |
Voltage falling (2) |
|
0.2 |
|
|
V |
VEN |
Enable threshold |
Voltage rising (2) |
|
0.26 |
|
|
V |
IPFC_OK |
Input bias current |
VPFC_OK = 0 to 2.5V |
|
-0.1 |
-1 |
|
µA |
Vclamp |
Clamp voltage |
IPFC_OK = 1 mA |
9 |
9.5 |
|
|
V |
PWM_LATCH |
|
|
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|
|
Ileak |
Low level leakage |
VPWM_LATCH=0 |
|
|
-1 |
|
µA |
current |
|
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|
||||
|
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VH |
High level |
IPWM_LATCH = -0.5 mA |
3.7 |
|
|
|
V |
PWM_STOP |
|
|
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|
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|
|
|
Ileak |
High level leakage |
VPWM_STOP = 6V |
|
|
1 |
|
µA |
current |
|
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|
||||
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|
VL |
Low level |
IPWM_STOP = 0.5 mA |
|
|
1 |
|
V |
Vclamp |
Clamp voltage |
IPFC_OK = 2 mA |
9 |
9.5 |
|
|
V |
9/39
Electrical characteristics |
|
|
|
|
|
L6563 - L6563A |
|||||||
|
|
|
|
|
|
|
|
|
|
|
|||
Table 5. Electrical characteristics |
(continued) |
|
|
|
|
|
|
|
|||||
( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF between pin GD and GND, CFF =1µF between pin VFF |
|
||||||||||||
and GND; unless otherwise specified) |
|
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|||||
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Symbol |
|
|
Parameter |
|
|
Test condition |
Min |
Typ |
|
Max |
|
Unit |
|
|
|
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|
Run function |
|
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|||
IRUN |
|
Input bias current |
|
VRUN = 0 to 3 V |
|
|
|
|
-1 |
|
µA |
||
VDIS |
|
Disable threshold |
|
Voltage falling (2) |
|
0.5 |
0.52 |
|
0.54 |
|
V |
||
VEN |
|
Enable threshold |
|
Voltage rising (2) |
|
0.56 |
0.6 |
|
0.64 |
|
V |
||
Start timer |
|
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tSTART |
|
Start timer period |
|
|
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|
75 |
150 |
|
300 |
|
µs |
|
Gate driver |
|
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VOHdrop |
|
Dropout voltage |
|
IGDsource = 20 mA |
|
|
2 |
|
2.6 |
|
V |
||
|
|
IGDsource = 200 mA |
|
|
2.5 |
|
3 |
|
V |
||||
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|||||
VOLdrop |
|
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IGDsink = 200 mA |
|
|
1 |
|
2 |
|
V |
|
tf |
|
Current fall time |
|
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30 |
|
70 |
|
ns |
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|
tr |
|
Current rise time |
|
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|
40 |
|
80 |
|
ns |
|
VOclamp |
|
Output clamp voltage |
|
IGDsource = 5mA; Vcc = 20V |
10 |
12 |
|
15 |
|
V |
|||
|
|
UVLO saturation |
|
Vcc=0 to VccOn, Isink=10mA |
|
|
|
1.1 |
|
V |
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|
|
(1), (2) Parameters tracking each other |
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(3) |
The multiplier output is given by: |
VCS = KM |
VMULT (VCOMP – 2.5) |
|
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|||
|
|
------------------------V----VFF2--------------- |
----------------- |
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(4) |
Parameters guaranteed by design, functionality tested in production. |
|
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|
|
10/39
L6563 - L6563A |
Typical electrical performance |
|
|
5 Typical electrical performance
Figure 4. Supply current vs supply voltage |
Figure 5. VCC Zener voltage vs TJ |
Icc (mA)
10
5
1
0.5
0.1
0.05
0.01
0.005
0
Co = 1nF f = 70 kHz Tj = 25°C
0 |
5 |
10 |
15 |
20 |
25 |
Vcc(V)
Vccz (pin 14)
(V) 28 |
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27 |
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26 |
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25 |
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24 |
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23 |
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22 |
0 |
50 |
100 |
150 |
-50 |
Tj (°C)
Figure 6. IC consumption vs TJ |
Figure 7. |
Feedback reference vs TJ |
|
|||||||
Icc |
10 |
|
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|
VREF (pin 1) |
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(V) |
2.6 |
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(mA) |
|
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Operating |
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5 |
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Quiescent |
|
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Vcc = 12 V |
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2 |
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2.55 |
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|
1 |
|
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Disabled or |
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Vcc = 12 V |
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0.5 |
|
during OVP |
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||
Co = 1 nF |
|
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2.5 |
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|||
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f = 70 kHz |
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0.2 |
|
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Latched off |
|
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0.1 |
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2.45 |
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0.05 |
|
|
Before start-up |
|
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|
0.02 |
0 |
50 |
100 |
150 |
2.4 |
0 |
50 |
100 |
150 |
|
|
-50 |
-50 |
||||||||
|
|
|
Tj (°C) |
|
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|
|
Tj (°C) |
|
|
Figure 8. Start-up & UVLO vs TJ |
Figure 9. |
E/A output clamp levels vs TJ |
||||||||
12.5 |
|
|
|
VCOMP (pin 2) |
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||
VCC-ON |
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7 |
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(V) |
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(V)12
|
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6 |
Upper clamp |
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11.5 |
|
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Vcc = 12 V |
|
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11 |
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5 |
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10.5 |
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4 |
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10 |
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3 |
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VCC-OFF 9.5 |
|
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2 |
Lower clamp |
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(V) |
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||
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9 |
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1 |
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-50 |
0 |
50 |
100 |
150 |
|
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||
-50 |
0 |
50 |
100 |
150 |
||||||
|
Tj |
(°C) |
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|
||||||
|
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|
|
Tj (°C) |
|
|
|||
|
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|
|
|
|
|
|
|
11/39
Typical electrical performance |
|
|
|
|
|
|
L6563 - L6563A |
||||
Figure 10. Static OVP level vs TJ |
|
Figure 11. Vcs clamp vs TJ |
|
|
|||||||
VCOMP (pin 2) |
|
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|
VCSx (pin 4) |
|
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|
2.5 |
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|
(V) 1.5 |
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(V) |
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|
2.4 |
|
|
Vcc = 12 V |
|
1.4 |
|
|
Vcc = 12 V |
|
||
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|
VCOMP = Upper clamp |
|
|||
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2.3 |
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1.3 |
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2.2 |
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1.2 |
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2.1 |
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1.1 |
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2 |
0 |
50 |
100 |
150 |
1 |
0 |
50 |
100 |
150 |
|
|
-50 |
-50 |
|||||||||
|
|
|
Tj (°C) |
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Tj |
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Figure 12. Dynamic OVP current vs TJ |
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Figure 13. Current-sense offset vs |
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(normalized value) |
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mains voltage phase angle |
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IOVP120% |
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VCSoffset (pin 4) |
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30 |
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Vcc = 12 V |
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(mV) |
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Vcc = 12 V |
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25 |
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Tj = 25 ° |
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110% |
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20 |
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VMULT = 0 to 3V |
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VFF = 3V |
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100% |
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15 |
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VMULT = 0 to 0.7V |
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VFF = 0.7V |
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10 |
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90% |
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5 |
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80% |
0 |
50 |
100 |
150 |
0 |
0.628 |
1.256 |
1.884 |
2.512 |
3.14 |
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-50 |
0 |
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Tj (°C) |
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θ(°) |
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Figure 14. Delay-to-output vs TJ |
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Figure 15. Ic latch-off level on current sense vs |
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TJ (L6563 only) |
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tD(H-L) |
300 |
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Vpin4 |
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(ns) |
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2.0 |
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Vcc = 12 V |
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(V) |
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Vcc = 12 V |
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250 |
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1.8 |
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200 |
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1.6 |
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150 |
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1.4 |
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100 |
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1.2 |
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50 |
0 |
50 |
100 |
150 |
1.0 |
0 |
50 |
100 |
150 |
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-50 |
-50 |
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Tj (°C) |
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Tj |
(°C) |
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12/39