ST L6563, L6563A User Manual

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L6563

L6563A

Advanced transition-mode PFC controller

Features

■Very precise adjustable output overvoltage protection

■Tracking boost function

■Protection against feedback loop failure (Latched shutdown)

■Interface for cascaded converter's PWM controller

■Input voltage feedforward (1/V2)

■Inductor saturation detection (L6563 only)

■Remote ON/OFF control

■Low (≤ 90µA) start-up current

■5mA max. quiescent current

■1.5% (@ TJ = 25°C) internal reference voltage

■-600/+800 mA totem pole gate driver with active pull-down during UVLO

■SO14 package

Figure 1. Block diagram

SO-14

Applications

PFC pre-regulators for:

■HI-END AC-DC adapter/charger

■Desktop PC, server, WEB server

■IEC61000-3-2 OR JEIDA-MITI compliant SMPS, in excess of 350W

Table 1. Device summary

Part number	Package	Packaging
L6563	SO-14	Tube
L6563TR	SO-14	Tape & Reel
L6563A	SO-14	Tube
L6563ATR	SO-14	Tape & Reel

INV

COMP

MULT

VFF

1

2

3

5

TRACKING

Ideal diode

1 / V 2

BOOST

LINE VOLTAGE

-

TBO

6

1:1

MULTIPLIER

FEEDFORWARD

+

CURRENT

2.5V

4

MIRROR

LEADING-EDGE

CS

1.7V

BLANKING

1:1

Voltage

VOLTAGE

references

-

+

-

+

BUFFER

from

REGULATOR

3V

VFF

Vbias

INDUCTOR

Q

VCC

(INTERNAL SUPPLY BUS)

SATURATION

14

DETECTION

SAT

VCC

( not in L6563A)

15 V

R

Q

R1

UVLO

COMPARATOR

S

13

GD

GND

12

+

Driver

R2

-

UVLO

VREF2

Starter

11

ZERO CURRENT

OFF

1.4V

-

DETECTOR

STARTER

0.2V

ZCD

+

0.7V

0.26V

+

10

-

PFC_OK

RUN

-

7

DISABLE

SAT

LATCH

+

+

0.52V

0.6V

Vbias

FEEDBACK

-

ON/OFF CONTROL

FAILURE

2.5V

(BROWNOUT DETECTION)

9

8

PROTECTION

	PWM_STOP	PWM_LATCH
March 2007	Rev 4	1/39

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Contents	L6563 - L6563A

Contents

1	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 3
	1.1	Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4
	1.2	Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4
2	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
3	Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
4	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		7
5	Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
6	Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
	6.1	Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
	6.2	Feedback Failure Protection (FFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	6.3	Voltage Feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	6.4	THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
	6.5	Tracking Boost function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
	6.6	Inductor saturation detection (L6563 only) . . . . . . . . . . . . . . . . . . . . . . . .	27
	6.7	Power management/housekeeping functions . . . . . . . . . . . . . . . . . . . . . .	28
	6.8	Summary of L6563/A idle states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
7	Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		32
8	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		37
9	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		38

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L6563 - L6563A	Description

1 Description

The device is a current-mode PFC controller operating in Transition Mode (TM). Based on the core of a standard TM PFC controller, it offers improved performance and additional functions.

The highly linear multiplier, along with a special correction circuit that reduces crossover distortion of the mains current, allows wide-range-mains operation with an extremely low THD even over a large load range.

The output voltage is controlled by means of a voltage-mode error amplifier and a precise (1.5% @TJ = 25°C) internal voltage reference. The stability of the loop and the transient response to sudden mains voltage changes are improved by the voltage feedforward function (1/V2 correction).

Additionally, the IC provides the option for tracking boost operation (where the output voltage is changed tracking the mains voltage). The device features extremely low consumption (≤ 90 µA before start-up and ≤ 5 mA running).

In addition to an effective two-step OVP that handles normal operation overvoltages, the IC provides also a protection against feedback loop failures or erroneous output voltage setting.

In the L6563 a protection is added to stop the PFC stage in case the boost inductor saturates. This function is not included in the L6563A. This is the only difference between the two part numbers.

An interface with the PWM controller of the DC-DC converter supplied by the PFC preregulator is provided: the purpose is to stop the operation of the converter in case of anomalous conditions for the PFC stage (feedback loop failure, boost inductor's core saturation) in the L6563 only and to disable the PFC stage in case of light load for the DCDC converter, so as to make it easier to comply with energy saving norms (Blue Angel, EnergyStar, Energy2000, etc.). The device includes disable functions suitable for remote ON/OFF control both in systems where the PFC pre-regulator works as a master and in those where it works as a slave.

The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable to drive high current MOSFETs or IGBTs. This, combined with the other features and the possibility to operate with the proprietary Fixed-Off-Time control, makes the device an excellent low-cost solution for EN61000-3-2 compliant SMPS in excess of 350W.

Figure 2. Typical system block diagram

PFC PRE-REGULATOR

Vinac

DC-DC CONVERTER

Voutdc

PWM is turned off in case of PFC’s anomalous operation for safety

L6563 L6563A

PWM or Resonant CONTROLLER

PFC can be turned off at light load to ease compliance with energy saving regulations.

3/39

Description	L6563 - L6563A

1.1Pin connection

Figure 3. Pin connection (top view)

INV	1	14	Vcc
COMP	2	13	GD
MULT	3	12	GND
CS	4	11	ZCD
VFF	5	10	RUN
TBO	6	9	PWM_STOP
PFC_OK	7	8	PWM_LATCH

1.2Pin description

Table 2. Pin description

Pin N°	Name	Description
		Inverting input of the error amplifier. The information on the output voltage of the PFC pre-
		regulator is fed into the pin through a resistor divider.
1	INV	The pin normally features high impedance but, if the tracking boost function is used, an
		internal current generator programmed by TBO (pin 6) is activated. It sinks current from the
		pin to change the output voltage so that it tracks the mains voltage.
		Output of the error amplifier. A compensation network is placed between this pin and INV
2	COMP	(pin 1) to achieve stability of the voltage control loop and ensure high power factor and low
		THD.
		Main input to the multiplier. This pin is connected to the rectified mains voltage via a
3	MULT	resistor divider and provides the sinusoidal reference to the current loop. The voltage on
		this pin is used also to derive the information on the RMS mains voltage.
		Input to the PWM comparator. The current flowing in the MOSFET is sensed through a
		resistor, the resulting voltage is applied to this pin and compared with an internal reference
		to determine MOSFET’s turn-off.
4	CS	A second comparison level at 1.7V detects abnormal currents (e.g. due to boost inductor
		saturation) and, on this occurrence, shuts down the IC, reduces its consumption almost to
		the start-up level and asserts PWM_LATCH (pin 8) high. This function is not present in the
		L6563A.
		Second input to the multiplier for 1/V2 function. A capacitor and a parallel resistor must be
5	VFF	connected from the pin to GND. They complete the internal peak-holding circuit that
		derives the information on the RMS mains voltage. The voltage at this pin, a DC level equal
		to the peak voltage at pin MULT (pin 3), compensates the control loop gain dependence on
		the mains voltage. Never connect the pin directly to GND.

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	L6563 - L6563A		Description
	Table 2. Pin description (continued)
	Pin N°	Name	Description
			Tracking Boost function. This pin provides a buffered VFF voltage. A resistor connected
	6	TBO	between this pin and GND defines a current that is sunk from pin INV (pin 1). In this way,
			the output voltage is changed proportionally to the mains voltage (tracking boost). If this
			function is not used leave this pin open.
			PFC pre-regulator output voltage monitoring/disable function. This pin senses the output
			voltage of the PFC pre-regulator through a resistor divider and is used for protection
			purposes. If the voltage at the pin exceeds 2.5V the IC is shut down, its consumption goes
			almost to the start-up level and this condition is latched. PWM_LATCH pin is asserted high.
	7	PFC_OK	Normal operation can be resumed only by cycling the Vcc. This function is used for
			protection in case the feedback loop fails.
			If the voltage on this pin is brought below 0.2V the IC is shut down and its consumption is
			considerably reduced. To restart the IC the voltage on the pin must go above 0.26V. If these
			functions are not needed, tie the pin to a voltage between 0.26 and 2.5 V.
			Output pin for fault signaling. During normal operation this pin features high impedance. If
			either a voltage above 2.5V at PFC_OK (pin 7) or a voltage above 1.7V on CS (pin 4) of
	8	PWM_LATCH	L6563 is detected the pin is asserted high. Normally, this pin is used to stop the operation
			of the DC-DC converter supplied by the PFC pre-regulator by invoking a latched disable of
			its PWM controller. If not used, the pin will be left floating.
			Output pin for fault signaling. During normal operation this pin features high impedance. If
			the IC is disabled by a voltage below 0.5V on RUN (pin 10) the voltage at the pin is pulled
	9	PWM_STOP	to ground. Normally, this pin is used to temporarily stop the operation of the DC-DC
			converter supplied by the PFC pre-regulator by disabling its PWM controller. If not used,
			the pin will be left floating.
			Remote ON/OFF control. A voltage below 0.52V shuts down (not latched) the IC and
			brings its consumption to a considerably lower level. PWM_STOP is asserted low. The IC
	10	RUN	restarts as the voltage at the pin goes above 0.6V. Connect this pin to VFF (pin 5) either
			directly or through a resistor divider to use this function as brownout (AC mains
			undervoltage) protection, tie to INV (pin 1) if the function is not used.
	11	ZCD	Boost inductor’s demagnetization sensing input for transition-mode operation. A negative-
			going edge triggers MOSFET’s turn-on.
	12	GND	Ground. Current return for both the signal part of the IC and the gate driver.
			Gate driver output. The totem pole output stage is able to drive power MOSFET’s and
	13	GD	IGBT’s with a peak current of 600 mA source and 800 mA sink. The high-level voltage of
			this pin is clamped at about 12V to avoid excessive gate voltages.
	14	VCC	Supply Voltage of both the signal part of the IC and the gate driver.

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Absolute maximum ratings	L6563 - L6563A

2 Absolute maximum ratings

Table 3. Absolute maximum ratings

	Symbol	Pin	Parameter	Value	Unit
	VCC	14	IC supply voltage (Icc = 20mA)	self-limited	V
	---	2, 4 to 6, 8	Analog inputs & outputs	-0.3 to 8	V
		to 10
	---	1, 3, 7	Max. pin voltage (Ipin = 1 mA)	Self-limited	V
	IPWM_STOP	10	Max. sink current	3	mA
	IZCD	9	Zero current detector max. current	-10 (source)	mA
				10 (sink)
	PTOT		Power dissipation @TA = 50°C	0.75	W
	TJ		Junction temperature operating range	-25 to 150	°C
	TSTG		Storage temperature	-55 to 150	°C

3 Thermal data

Table 4. Thermal data

Symbol	Parameter	Value	Unit
RthJA	Maximum thermal resistance junction-ambient	120	°C/W

6/39

L6563 - L6563A	Electrical characteristics

4 Electrical characteristics

Table 5. Electrical characteristics

( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF between pin GD and GND, CFF =1µF between pin VFF and GND; unless otherwise specified)

	Symbol	Parameter	Test condition	Min	Typ	Max	Unit
	Supply voltage
	Vcc	Operating range	After turn-on	10.3		22	V
	VccOn	Turn-on threshold	(1)	11	12	13	V
	VccOff	Turn-off threshold	(1)	8.7	9.5	10.3	V
	Hys	Hysteresis		2.3		2.7	V
	VZ	Zener Voltage	Icc = 20 mA	22	25	28	V
	Supply current
	Istart-up	Start-up current	Before turn-on, Vcc = 10V		50	90	µA
	Iq	Quiescent current	After turn-on		3	5	mA
	ICC	Operating supply current	@ 70kHz		3.8	5.5	mA
			Latched by PFC_OK > Vthl or		180	250	µA
		Idle state quiescent	Vcs > VCSdis
	Iqdis
		Current	Disabled by PFC_OK < Vth or		1.5	2.2	mA
			RUN < VDIS
	Iq	Quiescent current	During static/dynamic OVP		2	3	mA
	Multiplier input
	IMULT	Input bias current	VMULT = 0 to 3 V		-0.2	-1	µA
	VMULT	Linear operation range		0 to 3			V
	VCLAMP	Internal clamp level	IMULT = 1 mA	9	9.5		V
	∆Vcs	Output max. slope	VMULT=0 to 0.5V, VFF=0.8V	2.2	2.34		V/V
	---------------------		VCOMP = Upper clamp
	∆VMULT
	KM	Gain (3)	VMULT = 1 V, VCOMP= 4 V,	0.375	0.45	0.525	V
			VVFF = VMULT
	Error amplifier
	VINV	Voltage feedback input	TJ = 25 °C	2.465	2.5	2.535	V
		threshold	10.3 V < Vcc < 22 V (2)	2.44		2.56
		Line regulation	Vcc = 10.3 V to 22V		2	5	mV
	IINV	Input bias current	TBO open, VINV = 0 to 4 V		-0.2	-1	µA

7/39

Electrical characteristics					L6563 - L6563A
Table 5. Electrical characteristics		(continued)
( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF between pin GD and GND, CFF =1µF between pin VFF
and GND; unless otherwise specified)
Symbol	Parameter	Test condition	Min	Typ		Max		Unit
VINVCLAMP	Internal clamp level	IINV = 1 mA	9	9.5				V
Gv	Voltage gain	Open loop	60	80				dB
GB	Gain-bandwidth product			1				MHz
ICOMP	Source current	VCOMP = 4V, VINV = 2.4 V	-2	-3.5		-5		mA
	Sink current	VCOMP = 4V, VINV = 2.6 V	2.5	4.5				mA
VCOMP	Upper clamp voltage	ISOURCE = 0.5 mA	5.7	6.2		6.7		V
	Lower clamp voltage	ISINK = 0.5 mA (2)	2.1	2.25		2.4		V
Current sense comparator
ICS	Input bias current	VCS = 0				-1		µA
tLEB	Leading edge blanking		100	200		300		ns
td(H-L)	Delay to output			120				ns
VCSclamp	Current sense reference	VCOMP = Upper clamp,	1.0	1.08		1.16		V
	clamp	VVFF = VMULT =0.5V
Vcsoffset	Current sense offset	VMULT = 0, VVFF = 3V		25				mV
		VMULT = 3V, VVFF = 3V		5
VCSdis	Ic latch-off level (L6563	(2)	1.6	1.7		1.8		V
	only)
Output overvoltage
IOVP	Dynamic OVP triggering		17	20		23		µA
	current
Hys	Hysteresis	(4)		15				µA
	Static OVP threshold	(2)	2	2.15		2.3		V
Voltage feedforward
VVFF	Linear operation range	RFF = 47 kΩ to GND	0.5			3		V
∆V	Dropout					20		mV
	VMULTpk-VVFF

8/39

L6563 - L6563A			Electrical characteristics
Table 5. Electrical characteristics		(continued)
( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF between pin GD and GND, CFF =1µF between pin VFF
and GND; unless otherwise specified)
Symbol	Parameter	Test condition	Min	Typ	Max		Unit
Zero current detector
VZCDH	Upper clamp voltage	IZCD = 2.5 mA	5.0	5.7			V
VZCDL	Lower clamp voltage	IZCD = - 2.5 mA	-0.3	0	0.3		V
VZCDA	Arming voltage	(4)		1.4			V
	(positive-going edge)
VZCDT	Triggering voltage	(4)		0.7			V
	(negative-going edge)
IZCDb	Input bias current	VZCD = 1 to 4.5 V			1		µA
IZCDsrc	Source current capability		-2.5				mA
IZCDsnk	Sink current capability		2.5				mA
Tracking boost function
∆V	Dropout voltage	ITBO = 0.25 mA			20		mV
	VVFF - VTBO
ITBO	Linear operation		0		0.25		mA
	IINV - ITBO current	ITBO = 25 µA to 0.25 mA	-3.5		3.5		%
	mismatch
VTBOclamp	Clamp voltage	VVFF = 4V (2)	2.9	3	3.1		V
PFC_OK
Vthl	Latch-off threshold	Voltage rising (2)	2.4	2.5	2.6		V
Vth	Disable threshold	Voltage falling (2)		0.2			V
VEN	Enable threshold	Voltage rising (2)		0.26			V
IPFC_OK	Input bias current	VPFC_OK = 0 to 2.5V		-0.1	-1		µA
Vclamp	Clamp voltage	IPFC_OK = 1 mA	9	9.5			V
PWM_LATCH
Ileak	Low level leakage	VPWM_LATCH=0			-1		µA
	current
VH	High level	IPWM_LATCH = -0.5 mA	3.7				V
PWM_STOP
Ileak	High level leakage	VPWM_STOP = 6V			1		µA
	current
VL	Low level	IPWM_STOP = 0.5 mA			1		V
Vclamp	Clamp voltage	IPFC_OK = 2 mA	9	9.5			V

9/39

Electrical characteristics

L6563 - L6563A

Table 5. Electrical characteristics

(continued)

( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF between pin GD and GND, CFF =1µF between pin VFF

and GND; unless otherwise specified)

Symbol

Parameter

Test condition

Min

Typ

Max

Unit

Run function

IRUN

Input bias current

VRUN = 0 to 3 V

-1

µA

VDIS

Disable threshold

Voltage falling (2)

0.5

0.52

0.54

V

VEN

Enable threshold

Voltage rising (2)

0.56

0.6

0.64

V

Start timer

tSTART

Start timer period

75

150

300

µs

Gate driver

VOHdrop

Dropout voltage

IGDsource = 20 mA

2

2.6

V

IGDsource = 200 mA

2.5

3

V

VOLdrop

IGDsink = 200 mA

1

2

V

tf

Current fall time

30

70

ns

tr

Current rise time

40

80

ns

VOclamp

Output clamp voltage

IGDsource = 5mA; Vcc = 20V

10

12

15

V

UVLO saturation

Vcc=0 to VccOn, Isink=10mA

1.1

V

(1), (2) Parameters tracking each other

(3)

The multiplier output is given by:

VCS = KM

VMULT (VCOMP – 2.5)

------------------------V----VFF2---------------

-----------------

(4)

Parameters guaranteed by design, functionality tested in production.

10/39

L6563 - L6563A	Typical electrical performance

5 Typical electrical performance

Figure 4. Supply current vs supply voltage

Figure 5. VCC Zener voltage vs TJ

Icc (mA)

10

5

1

0.5

0.1

0.05

0.01

0.005

0

Co = 1nF f = 70 kHz Tj = 25°C

0

5

10

15

20

25

Vcc(V)

Vccz (pin 14)

(V) 28
27
26
25
24
23
22	0	50	100	150
-50

Tj (°C)

Figure 6. IC consumption vs TJ					Figure 7.	Feedback reference vs TJ
Icc	10				VREF (pin 1)
					(V)	2.6
(mA)				Operating
	5
				Quiescent					Vcc = 12 V
	2				2.55
	1			Disabled or
		Vcc = 12 V
0.5				during OVP
		Co = 1 nF				2.5
		f = 70 kHz
0.2				Latched off
0.1					2.45
0.05				Before start-up
0.02		0	50	100	150	2.4	0	50	100	150
	-50					-50
			Tj (°C)					Tj (°C)
Figure 8. Start-up & UVLO vs TJ					Figure 9.	E/A output clamp levels vs TJ
12.5					VCOMP (pin 2)
VCC-ON					7
					(V)

(V)12

						6	Upper clamp
	11.5								Vcc = 12 V
	11					5
	10.5					4
	10					3
	VCC-OFF 9.5					2	Lower clamp
	(V)
	9					1
	-50	0	50	100	150
						-50	0	50	100	150
		Tj	(°C)
								Tj (°C)

11/39

Typical electrical performance										L6563 - L6563A
Figure 10. Static OVP level vs TJ						Figure 11. Vcs clamp vs TJ
VCOMP (pin 2)						VCSx (pin 4)
2.5						(V) 1.5
(V)
2.4				Vcc = 12 V		1.4			Vcc = 12 V
								VCOMP = Upper clamp
2.3						1.3
2.2						1.2
2.1						1.1
	2	0	50	100	150	1	0	50		100	150
	-50					-50
			Tj (°C)					Tj	(°C)
Figure 12. Dynamic OVP current vs TJ						Figure 13. Current-sense offset vs
	(normalized value)					mains voltage phase angle
IOVP120%						VCSoffset (pin 4)
						30
				Vcc = 12 V		(mV)		Vcc = 12 V
						25		Tj = 25 °
110%
						20			VMULT = 0 to 3V
									VFF = 3V
100%						15		VMULT = 0 to 0.7V
								VFF = 0.7V
						10
	90%
						5
	80%	0	50	100	150	0	0.628	1.256	1.884	2.512	3.14
	-50					0
			Tj (°C)					θ(°)
Figure 14. Delay-to-output vs TJ						Figure 15. Ic latch-off level on current sense vs
						TJ (L6563 only)
tD(H-L)	300					Vpin4
(ns)						2.0
				Vcc = 12 V		(V)				Vcc = 12 V
	250					1.8
	200					1.6
	150					1.4
	100					1.2
	50	0	50	100	150	1.0	0	50		100	150
	-50					-50
			Tj (°C)					Tj	(°C)

12/39