ST L6562 User Manual
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Fi
TRANSITION-MODE PFC CONTROLLER
L6562
1Features
■ REALISED IN BCD TECHNOLOGY
■ TRANSITION-MODE CONTROL OF PFC PRE-
REGULATORS
■ PROPRIETARY MULTIPLIER DESIGN FOR
MINIMUM THD OF AC INPUT CURRENT
■ VERY PRECISE ADJUSTABLE OUTPUT
OVERVOLTAGE PROTECTION
■ ULTRA-LOW (≤70µA) START-UP CURRENT
■ LOW (≤4 mA) QUIESCENT CURRENT
■ EXTENDED IC SUPPLY VOLTAGE RANGE
■ ON-CHIP FILTER ON CURRENT SENSE
■ DISABLE FUNCTION
■ 1% (@ Tj = 25 °C) INTERNAL REFERENCE
VOLTAGE
■
-600/+800mA TOTEM POLE GATE DRIVER WITH
UVLO PULL-DOWN AND VOLTAGE CLAMP
■ DIP-8/SO-8 PACKAGES ECOPACK
1.1 APPLICATIONS
■ PFC PRE-REGULATORS FOR:
– IEC61000-3-2 COMPLIANT SMPS (TV,
Figure 2. Block Diagram
1
INV
VOLTAGE
REGULATOR
®
-
+
2.5V
OVERVOLTAGE
DETECTION
gure 1. Packages
DIP-8
SO-8
Table 1. Order Codes
Part Number Package
L6562N DIP-8
L6562D SO-8
L6562DTR Tape & Reel
DESKTOP PC, MONITOR) UP TO 300W
– HI-END AC-DC ADAPTER/CHARGER
– ENTRY LEVEL SERVER & WEB SERVER
2 Description
The L6562 is a current-mode PFC controller operating in Transition Mode (TM). Pin-to-pin compatible with the predecessor L6561, it offers improved
performance.
COMP MULT CS
23 4
MULTIPLIER AND
THD OPTIMIZ ER
+
-
40K
5pF
VCC
November 2005
8
V
CC
25 V
R2
6
2.1 V
1.6 V
GND
R1
INTERNAL
SUPPLY 7V
REF2
V
DRIVER
15 V
7
GD
RSQ
+
UVLO
-
ZERO CURRENT
DETECTOR
+
-
5
ZCD
DISABLE
Starter
stop
STARTER
Rev. 8
1/16
L6562
2 Description (continued)
The highly linear multiplier includes a special circuit, able to reduce AC input current distortion, that allows
wide-range-mains operation with an extremely low THD, even over a large load range.
The output voltage is controlled by means of a voltage-mode error amplifier and a precise (1% @Tj =
25°C) internal voltage reference.
The device features extremely low consumption (≤70 µA before start-up and <4 mA running) and includes
a disable function suitable for IC remote ON/OFF, which makes it easier to comply with energy saving
norms (Blue Angel, EnergyStar, Energy2000, etc.).
An effective two-step OVP enables to safely handle overvoltages either occurring at start-up or resulting
from load disconnection.
The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable for big MOSFET or IGBT drive which, combined with the other features, makes the device an excellent low-cost solution for EN61000-3-2 compliant SMPS's up to 300W.
Table 2. Absolute Maximum Ratings
Symbol Pin Parameter Value Unit
V
CC
--- 1 to 4 Analog Inputs & Outputs -0.3 to 8 V
IZCD 5 Zero Current Detector Max. Current -50 (source)
P
tot
T
j
T
stg
8 IC Supply voltage (Icc = 20 mA) self-limited V
10 (sink)
Power Dissipation @Tamb = 50°C (DIP-8)
(SO-8)
Junction Temperature Operating range -40 to 150 °C
Storage Temperature -55 to 150 °C
1
0.65
Figure 3. Pin Connection (Top view)
INV
COMP
MULT
CS
1
2
3
4
Vcc
8
7
GD
GND
6
ZCD
5
Table 3. Thermal Data
mA
W
Symbol Parameter SO8 Minidip Unit
2/16
R
th j-amb
Max. Thermal Resistance, Junction-to-ambient 150 100 °C/W
Table 4. Pin Description
N° Pin Function
1 INV Inverting input of the error amplifier. The information on the output voltage of the PFC pre-
regulator is fed into the pin through a resistor divider.
2 COMP Output of the error amplifier. A compensation network is placed between this pin and INV (pin
#1) to achieve stability of the voltage control loop and ensure high power factor and low THD.
3 MULT Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor
divider and provides the sinusoidal reference to the current loop.
4 CS Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor,
the resulting voltage is applied to this pin and compared with an internal sinusoidal-shaped
reference, generated by the multiplier, to determine MOSFET’s turn-off.
5 ZCD Boost inductor’s demagnetization sensing input for transition-mode operation. A negative-going
edge triggers MOSFET’s turn-on.
6 GND Ground. Current return for both the signal part of the IC and the gate driver.
7 GD Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s
with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is
clamped at about 12V to avoid excessive gate voltages in case the pin is supplied with a high
Vcc.
8 Vcc Supply Voltage of both the signal part of the IC and the gate driver. The supply voltage upper
limit is extended to 22V min. to provide more headroom for supply voltage changes.
L6562
Table 5. Electrical Characteristics
= -25 to 125°C, VCC = 12, CO = 1 nF; unless otherwise specified)
(T
j
Symbol Parameter Test Condition Min. Typ. Max. Unit
SUPPLY VOLTAGE
V
V
CCon
V
CCOff
Hys Hysteresis 2.2 2.8 V
V
SUPPLY CURRENT
I
start-up
I
MULTIPLIER INPUT
I
MULT
V
MULT
VCS∆
---------------------
V
∆
MULT
ERROR AMPLIFIER
V
I
Operating range After turn-on 10.3 22 V
CC
Turn-on threshold
Turn-off threshold
Zener Voltage ICC = 20 mA 22 25 28 V
Z
(1)
(1)
11 12 13 V
8.7 9.5 10.3 V
Start-up Current Before turn-on, VCC =11V 40 70 µA
Quiescent Current After turn-on 2.5 3.75 mA
I
q
Operating Supply Current @ 70 kHz 3.5 5 mA
CC
I
Quiescent Current During OVP (either static or
q
Input Bias Current V
dynamic) or V
= 0 to 4 V -1 µA
VFF
=150 mV
ZCD
Linear Operation Range 0 to 3 V
Output Max. Slope V
K
INV
(2)
Gain
Voltage Feedback Input
Threshold
= 0 to 0.5V
MULT
= Upper clamp
V
COMP
V
MULT
= 1 V, V
= 4 V 0.5 0.6 0.7 1/V
COMP
Tj = 25 °C 2.465 2.5 2.535 V
10.3 V < Vcc < 22 V
(1)
1.65 1.9 V/V
2.44 2.56
Line Regulation Vcc = 10.3 V to 22V 2 5 mV
Input Bias Current V
INV
= 0 to 3 V -1 µA
INV
2.2 mA
3/16
L6562
Table 5. Electrical Characteristics (continued)
(T
= -25 to 125°C, VCC = 12, CO = 1 nF; unless otherwise specified)
j
Symbol Parameter Test Condition Min. Typ. Max. Unit
G
GB Gain-Bandwidth Product 1 MHz
I
COMP
V
COMP
CURRENT SENSE COMPARATOR
I
t
d(H-L)
V
CS clamp
V
CSoffset
ZERO CURRENT DETECTOR
V
ZCDH
V
ZCDL
V
ZCDA
V
ZCDT
I
ZCDb
I
ZCDsrc
I
ZCDsnk
V
ZCDdis
V
ZCDen
I
ZCDres
STARTER
t
START
OUTPUT OVERVOLTAGE
I
OVP
Hys Hysteresis
GATE DRIVER
V
V
V
Oclamp
(1) All parameters are in tracking
(2) The multiplier output is given by:
(3) Parameters guaranteed by design, functionality tested in production.
Voltage Gain Open loop 60 80 dB
v
Source Current V
Sink Current V
Upper Clamp Voltage I
Lower Clamp Voltage
Input Bias Current VCS = 0 -1 µA
CS
Delay to Output
Current sense reference clamp V
Current sense offset V
Upper Clamp Voltage I
Lower Clamp Voltage I
Arming Voltage
COMP
COMP
SOURCE
I
= 0.5 mA
SINK
= 4V, V
= 4V, V
= 0.5 mA 5.3 5.7 6 V
= 2.4 V -2 -3.5 -5 mA
INV
= 2.6 V 2.5 4.5 mA
INV
(1)
2.12.252.4 V
200 350 ns
= Upper clamp 1.6 1.7 1.8 V
COMP
= 0 30 mV
MULT
V
= 2.5V 5
MULT
= 2.5 mA 5.0 5.7 6.5 V
ZCD
= -2.5 mA 0.3 0.65 1 V
ZCD
(3)
2.1 V
(positive-going edge)
Triggering Voltage
(3)
1.6 V
(negative-going edge)
Input Bias Current
= 1 to 4.5 V
V
ZCD
2µA
Source Current Capability -2.5 -5.5 mA
Sink Current Capability 2.5 mA
Disable threshold 150 200 250 mV
Restart threshold 350 mV
Restart Current after Disable 30 75 µA
Start Timer period
75 130 300 µs
Dynamic OVP triggering current 35 40 45 µA
(3)
Static OVP threshold
OH
Dropout Voltage
OL
Voltage Fall Time 30 70 ns
t
f
Voltage Rise Time 40 80 ns
t
r
Output clamp voltage I
UVLO saturation V
VcsKV
(1)
I
GDsource
I
GDsource
I
= 200 mA
GDsink
GDsource
= 0 to V
CC
MULTVCOMP
= 20 mA
= 200 mA
= 5mA; Vcc = 20V
, I
CCon
2.5–()⋅⋅=
=10mA 1.1 V
sink
2.12.252.4 V
10 12 15 V
30 µA
22.6
2.5 3 V
0.9 1.9 V
4/16
3 Typical Electrical Characteristics
L6562
Figure 4. Supply current vs. Supply voltage
I
CC
(mA)
10
5
1
0.5
0.1
0.05
0.01
0.005
0
0 5 10 15 20
V
cc(V)
Figure 5. Start-up & UVLO vs. T
12.5
V
CC-ON
12
(V)
Co = 1nF
f = 70 kHz
T
= 25°C
j
j
25
Figure 6. IC consumption vs. T
Icc
10
[mA]
5
j
2
1
0.5
Vcc = 12 V
Co = 1 nF
f = 70 kHz
0.2
0.1
0.05
0.02
-50 0 50 100 150
Before start-up
Tj (°C)
Figure 7. Vcc Zener voltage vs. Tj
Vcc
Z
28
(V)
27
Operating
Quiescent
Disabled or
durin g O VP
CC-OFF
V
(V)
11.5
11
10.5
10
9.5
9
-50 0 50 100 150
Tj (
°C)
26
25
24
23
22
-50 0 50 100 150
Tj (°C)
5/16
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