All application commands and data registers,
including those used to set analog values (i.e.
current control value, current protection trip point,
dead time, etc.) are sent through a standard 5Mbit/s SPI.
A very rich set of protections (thermal, low bus
voltage, overcurrent) makes the L6472 “bullet
proof”, as required by the most demanding motor
control applications.
Table 1.Device summary
Order codes Package Packing
HTSSOP28
Description
L6472H HTSSOP28Tube
L6472HTR HTSSOP28Tape and reel
The L6472, realized in analog mixed signal
technology, is an advanced fully integrated
solution suitable for driving two-phase bipolar
stepper motors with microstepping. It integrates a
dual low R
DMOS full bridge with all of the
DS(on)
power switches equipped with an accurate onchip current sensing circuitry suitable for nondissipative current control and overcurrent
protection. Thanks to a new current control, a
1/16 microstepping is achieved through an
adaptive decay mode which outperforms
traditional implementations. The digital control
core can generate user defined motion profiles
with acceleration, deceleration, speed or target
position, easily programmed through a dedicated
register set.
1. Maximum output current limit is related to metal connection and bonding characteristics. Actual limit must satisfy maximum
thermal dissipation constraints.
2. HTSSOP28 mounted on EVAL6472H Rev 1.0.
GND, diff
V
boot
V
REG
ADCIN
V
OSC
out_diff
LOGIC
I
out
T
OP
T
P
tot
PGND and DGND
Bootstrap peak voltage 55 V
Internal voltage regulator output pin
and logic supply voltage
Integrated ADC input voltage range
(ADCIN pin)
OSCIN and OSCOUT pin voltage
range
Differential voltage between V
, OUT2A, PGND and VSB,
OUT1
A
OUT1
, OUT2B, PGND pins
B
SA
,
= VSB = VS 48 V
V
SA
Logic inputs voltage range -0.3 to +5.5 V
(1)
R.m.s. output current 3 A
(1)
Pulsed output current T
< 1 ms 7 A
PULSE
Operating junction temperature 150 °C
Storage temperature range -55 to 150 °C
s
Total power dissipation (TA = 25 °C)
(2)
±0.3 V
3.6 V
-0.3 to +3.6 V
-0.3 to +3.6 V
5W
Doc ID 022729 Rev 19/69
Electrical dataL6472
2.2 Recommended operating conditions
Table 3.Recommended operating conditions
Symbol Parameter Test condition Value Unit
V
Logic interface supply voltage
DD
V
Motor supply voltage VSA = VSB = VS 8 45 V
S
Differential voltage between
, OUT1A, OUT2A, PGND
V
V
out_diff
SA
and V
, OUT1B, OUT2B,
SB
PGND pins
V
Logic supply voltage
REG,in
Integrated ADC input voltage
V
ADC
(ADCIN pin)
Operating junction temperature -25 125 °C
T
j
2.3 Thermal data
Table 4.Thermal data
SymbolParameterPackageTypUnit
R
thJA
1. HTSSOP28 mounted on EVAL6472H Rev 1.0 board: four-layer FR4 PCB with a dissipating copper surface
of about 40 cm
2. POWERSO36 mounted on EVAL6472PD Rev 1.0 board: four-layer FR4 PCB with a dissipating copper
surface of about 40 cm
Thermal resistance junction-ambient
2
on each layer and 15 via holes below the IC.
3.3 V logic outputs 3.3 V
5 V logic outputs 5
V
= V
= VS 45 V
SB
voltage imposed by
V
SA
REG
external source
2
on each layer and 22 via holes below the IC.
3.2 3.3 V
HTSSOP28
POWERSO36
0 V
(1)
(2)
22
12
REG
V
°C/W
10/69Doc ID 022729 Rev 1
L6472Electrical characteristics
3 Electrical characteristics
VSA = VSB = 36 V; VDD = 3.3 V; internal 3 V regulator; TJ = 25 °C, unless otherwise
specified.
Table 5.Electrical characteristics
Symbol Parameter Test condition Min. Typ. Max. Unit
General
V
SthOn VS
V
SthOff
V
SthHyst
Iq
T
j(WRN)
T
j(SD)
UVLO turn-on threshold 7.5 8.2 8.9 V
VS UVLO turn-off threshold 6.6 7.2 7.8 V
VS UVLO threshold
hysteresis
Quiescent motor supply
current
Thermal warning temperature 130 °C
Thermal shutdown
temperature
Charge pump
pump
f
pump,min
f
pump,max
I
boot
pump oscillator
Minimum charge pump
oscillator frequency
Maximum charge pump
oscillator frequency
Average boot current
Voltage swing for charge
V
Output DMOS transistor
High-side switch onresistance
R
DS(on)
Low-side switch onresistance
I
DSS
Leakage current
(1)
(1)
0.7 1 1.3 V
Internal oscillator selected;
= 3.3V ext; CP floating
V
REG
= f
f
sw,A
= 15.6kHz
sw,B
POW_SR = ‘10’
T
= 25°C, I
j
Tj = 125°C,
= 25°C, I
T
j
T
= 125°C,
j
OUT = V
= 3A 0.37
out
(2)
I
= 3A 0.51
out
= 3A 0.18
out
(2)
I
= 3A 0.23
out
S
OUT = GND -0.3
0.5 0.65 mA
160 °C
10 V
660 kHz
800 kHz
1.1 1.4 mA
Ω
3.1
mA
Rise time
t
r
(3)
POW_SR = '00', I
POW_SR = '00', I
POW_SR = ‘11’, I
POW_SR = ‘10’, I
POW_SR = ‘01’, I
= +1A 100
out
= -1A 80
out
= ±1A 100
out
= ±1A 200
out
= ±1A 300
out
ns
Doc ID 022729 Rev 111/69
Electrical characteristicsL6472
Table 5.Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
(3)
SR
SR
t
Fall time
f
Output rising slew rate
out_r
Output falling slew rate
out_f
Dead time and blanking
POW_SR = '00'; I
POW_SR = '00'; I
POW_SR = ‘11’, I
POW_SR = ‘10’, I
POW_SR = ‘01’, I
POW_SR = '00', I
POW_SR = '00', I
POW_SR = ‘11’, I
POW_SR = ‘10’, I
POW_SR = ‘01’, I
POW_SR = '00', I
POW_SR = '00', I
POW_SR = ‘11’, I
POW_SR = ‘10’, I
POW_SR = ‘01’, I
= +1A 90
out
= -1A 110
out
= ±1A 110
out
= ±1A 260
out
= ±1A 375
load
= +1A 285
out
= -1A 360
out
= ±1A 285
out
= ±1A 150
out
= ±1A 95
out
= +1A 320
out
= -1A 260
out
= ±1A 260
out
= ±1A 110
out
= ±1A 75
out
POW_SR = '00' 250
ns
V/µs
V/µs
t
t
blank Blanking time
DT
Dead time
Source-drain diodes
High-side diode forward ON
V
SD,HS
V
SD,LS
t
rrHS
voltage
Low-side diode forward ON
voltage
High-side diode reverse
recovery time
(1)
(1)
POW_SR = ‘11’,
= 16MHz
f
OSC
POW_SR = ‘10’,
f
= 16MHz
OSC
POW_SR = ‘01’,
= 16MHz
f
OSC
375
625
875
POW_SR = '00' 250
POW_SR = ‘11’,
= 16MHz
f
OSC
POW_SR = ‘10’,
= 16MHz
f
OSC
POW_SR = ‘01’,
f
= 16MHz
OSC
= 1A 1 1.1 V
I
out
I
= 1A 1 1.1 V
out
= 1A 30 ns
I
out
375
625
875
ns
ns
12/69Doc ID 022729 Rev 1
L6472Electrical characteristics
Table 5.Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
t
rrLS
Low-side diode reverse
recovery time
= 1A 100 ns
I
out
Logic inputs and outputs
Low logic level input voltage 0.8 V
V
IL
V
High logic level input voltage 2 V
IH
I
IIL
VOL
VOH High logic level output voltage
High logic level input current
(4)
IH
Low logic level input current
(5)
Low logic level output voltage
(6)
VIN = 5V 1 µA
V
= 0V -1 µA
IN
VDD = 3.3V, IOL = 4mA 0.3
= 5V, IOL = 4mA 0.3
V
DD
V
= 3.3V, IOH = 4mA 2.4
DD
VDD = 5V, IOH = 4mA 4.7
R
R
I
logic
I
logic,STBY
CS pull-up and STBY pull-
PU
down resistors
PD
Internal logic supply current
Standby mode internal logic
supply current
CS
= GND;
STBY/RST
3.3V V
= 5V
externally
REG
supplied, internal oscillator
3.3V V
externally supplied 2 2.5 µA
REG
335 430 565 kΩ
3.7 4.3 mA
V
V
f
Step-clock input frequency 2 MHz
STCK
Internal oscillator and external oscillator driver
Internal oscillator frequency T
f
osc,i
f
osc,e
V
OSCOUT
V
OSCOUTL
t
rOSCOUT
t
fOSCOUT
t
extosc
t
intosc
Programmable external
oscillator frequency
OSCOUT clock source high
level voltage
H
OSCOUT clock source low
level voltage
OSCOUT clock source rise
and fall time
Internal to external oscillator
switching delay
External to internal oscillator
switching delay
= 25°C, V
j
Internal oscillator 3.3V V
externally supplied; I
= 4mA
Internal oscillator 3.3V V
externally supplied; I
= 4mA
Internal oscillator 20 ns
SPI
Maximum SPI clock
f
CK,MAX
frequency
(7)
= 3.3V -3% 16 +3% MHz
REG
8 32 MHz
REG
OSCOUT
REG
OSCOUT
2.4 V
0.3 V
3 ms
1.5 µs
5 MHz
Doc ID 022729 Rev 113/69
Electrical characteristicsL6472
Table 5.Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
Symbol Parameter Test condition Min. Typ. Max. Unit
t
cpwu
Charge pump power-on and
wake-up time
Power bridges disabled, Cp =
10nF, C
= 220nF
boot
Internal voltage regulator
REG
I
REG
V
REG, drop
I
REG,STBY
voltage
Voltage regulator output
current
Voltage regulator output
voltage drop
Voltage regulator standby
output current
= 40mA 50 mV
I
REG
Voltage regulator output
V
Integrated analog-to-digital converter
Analog-to-digital converter
N
ADC
V
ADC,ref
1. Accuracy depends on oscillator frequency accuracy.
2. Tested at 25 °C in a restricted range and guaranteed by characterization.
3. Rise and fall time depends on motor supply voltage value. Refer to SR
actual rise and fall time.
4. Not valid for the STBY/RST
5. Not valid for the SW and CS pins which have an internal pull-up resistor.
6. FLAG
7. See Figure 20 – SPI timings diagram for details.
resolution
Analog-to-digital converter
reference voltage
Analog-to-digital converter
f
S
sampling frequency
pin which has an internal pull-down resistor.
, BUSY and SYNC open drain outputs included.
out
650 µs
2.9 3 3.2 V
40 mA
10 mA
5 bit
V
V
REG
f
/
OSC
512
values in order to evaluate the
kHz
Doc ID 022729 Rev 115/69
Pin connectionL6472
4 Pin connection
Figure 2.HTSSOP28 pin connection (top view)
345
Figure 3.POWERSO36 pin connection (top view)
74"
74"
48
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065"
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74#
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065"
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74"
74"
45$,
'-"(
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74#
74#
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065#
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16/69Doc ID 022729 Rev 1
L6472Pin connection
4.1 Pin list
Table 6.Pin description
No. Name Type Function
17 VDD Power Logic output supply voltage (pull-up reference)
6 VREG Power
7 OSCIN Analog input
Internal 3 V voltage regulator output and 3.3 V external logic
supply
Oscillator pin 1. To connect an external oscillator or clock source.
If this pin is unused, it should be left floating.
Oscillator pin 2. To connect an external oscillator. When the
8 OSCOUT Analog output
internal oscillator is used this pin can supply 2/4/8/16 MHz. If this
pin is unused, it should be left floating.
10 CP Output Charge pump oscillator output
11 Vboot Supply voltage
Bootstrap voltage needed for driving the high-side power DMOS of
both bridges (A and B)
5 ADCIN Analog input Internal analog-to-digital converter input
2
VSA Power supply Full bridge A power supply pin. It must be connected to VSB
26
12
VSB Power supply Full bridge B power supply pin. It must be connected to VSA
16
27
PGND Ground Power ground pin
13
1 OUT1A Power output Full bridge A output 1
28 OUT2A Power output Full bridge A output 2
14 OUT1B Power output Full bridge B output 1
15 OUT2B Power output Full bridge B output 2
9 AGND Ground Analog ground.
4 SW Logical input
External switch input pin. If not used the pin should be connected
to VDD.
21 DGND Ground Digital ground
By default, this BUSY pin is forced low when the device is
22 BUSY
\SYNC Open drain output
performing a command. Otherwise the pin can be configured to
generate a synchronization signal.
18 SDO Logic output Data output pin for serial interface
20 SDI Logic input Data input pin for serial interface
19 CK Logic input Serial interface clock
23 CS
Logic input Chip select input pin for serial interface
Status flag pin. An internal open drain transistor can pull the pin to
24 FLAG Open drain output
GND when a programmed alarm condition occurs (step loss,
OCD, thermal pre-warning or shutdown, UVLO, wrong command,
non-performable command)
Doc ID 022729 Rev 117/69
Pin connectionL6472
Table 6.Pin description (continued)
No. Name Type Function
Standby and reset pin. LOW logic level resets the logic and puts
3 STBY\RST Logic input
25 STCK Logic input Step-clock input
EPAD Exposed pad Ground Internally connected to PGND, AGND and DGND pins
the device into standby mode. If not used, it should be connected
to VDD
18/69Doc ID 022729 Rev 1
L6472Typical applications
5 Typical applications
Table 7.Typical application values
Name Value
220 nF
C
VS
C
C
C
100 µF
VSPOL
C
100 nF
REG
REGPOL
47 µF
C
100 nF
DD
10 µF
DDPOL
D1 Charge pump diodes
C
220 nF
BOOT
C
10 nF
FLY
R
39 kΩ
PU
R
100 Ω
SW
CSW 10 nF
Figure 4.Bipolar stepper motor control application using the L6472
Doc ID 022729 Rev 119/69
Functional descriptionL6472
6 Functional description
6.1 Device power-up
At the end of power-up, the device state is the following:
●Registers are set to default,
●Internal logic is driven by the internal oscillator and a 2 MHz clock is provided by the
OSCOUT pin,
●Bridges are disabled (High Z),
●UVLO bit in the STATUS register is forced low (fail condition),
●FLAG output is forced low.
During power-up the device is under reset (all logic IO disabled and power bridges in highimpedance state) until the following conditions are satisfied:
●V
●
●Internal oscillator is operative.
Any motion command causes the device to exit from High Z state (HardStop and SoftStop
included).
is greater than V
S
V
is greater than V
REG
SthOn
REGth
= 2.8 V (typ.)
6.2 Logic I/O
Pins CS, CK, SDI, STCK, SW and STBY\RST are TTL/CMOS 3.3 V-5 V compatible logic
inputs.
Pin SDO is a TTL/CMOS compatible logic output. The VDD pin voltage sets the logic output
pin voltage range; when it is connected to VREG or a 3.3 V external supply voltage, the
output is 3.3 V compatible. When VDD is connected to a 5 V supply voltage, SDO is 5 V
compatible.
VDD is not internally connected to V
A 10 µF capacitor should be connected to the VDD pin in order to obtain a proper operation.
Pins FLAG
and BUSY\SYNC are open drain outputs.
6.3 Charge pump
To ensure the correct driving of the high-side integrated MOSFETs, a voltage higher than
the motor power supply voltage needs to be applied to the Vboot pin. The high-side gate
driver supply voltage Vboot is obtained through an oscillator and a few external components
realizing a charge pump (see Figure 5).
, an external connection is always needed.
REG
20/69Doc ID 022729 Rev 1
L6472Functional description
Figure 5.Charge pump circuitry
6.4 Microstepping
The driver is able to divide the single step into up to 16 microsteps. Step mode can be
programmed by the STEP_SEL parameter in the STEP_MODE register (see Ta b le 1 9 ).
Step mode can only be changed when bridges are disabled. Every time step mode is
changed, the electrical position (i.e. the point of microstepping sinewave that is generated)
is reset to the first microstep, and the absolute position counter value (see Section 6.5)
becomes meaningless.
Figure 6.Normal mode and microstepping (16 microsteps)
Doc ID 022729 Rev 121/69
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