ST L6460 User Manual

L6460

SPI configurable stepper and DC multi motor driver

Features

■Operating supply voltage from 13 V to 38 V

■4 full bridge driver configurable in multi-motor application to drive:

–2 DC and 1 stepper motor

–4 DC motor

■Bridge 1 and 2 (RDSon = 0.60 Ω) can be configured to work as:

–Dual full bridge driver

–Super DC driver

–2 half bridge driver

–1 super half bridge

–2 power switches

–1 super power switch

■Bridge 3 and 4 (RDSon = 0.85 Ω) can be configured to work as:

–Same as bridges 1 and 2, listed above

–Stepper motor driver: up to 1/16 microstepping

–2 buck regulators (bridge 3)

–1 super buck regulator

–Battery charger (bridge 4)

■Power supply management

–One switching buck regulator

–One switching regulator controller

–One linear regulator

–One battery charger

■Fully protected through

–Thermal warning and shutdown

–Overcurrent protection

–Undervoltage lock-out

■SPI interface

■Programmable watchdog function

■Integrated power sequencing and supervisory functions with fault signaling through serial interface and external reset pin

■Very low power dissipation in shut-down mode (~35 mW)

TQFP64 exposed pad

■Auxiliary features

–Multi-channels 9 bit ADC

–2 operational amplifiers

–Digital comparator

–2 low voltage power switches

–3 general purpose PWM generators

–14 GPIOs

Description

The L6460 is optimized to control and drive multimotor system providing a unique level of integration in term of control, power and auxiliary features. Thanks to the high configurability L6460 can be customized to drive different motor architectures and to optimize the number of embedded features, such as the voltage regulators, the high precision A/D converter, the operational amplifier and the voltage comparators. The possibility to drive simultaneously stepper and DC motor makes L6460 the ideal solution for all the application featuring multi motors.

Table 1.	Device summary
Order code		Package	Packing
L6460		TQFP64	Tray
L6460TR			Tape and reel

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Contents	L6460

Contents

1	General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		10
	1.1	Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
	1.2	Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	1.3	Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
2	L6460’s main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14
3	Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
	3.1	Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
	3.2	Operating ratings specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
	3.3	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
4	Internal supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		30
	4.1	VSupplyInt regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
	4.2	Charge pump regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
	4.3	V3v3 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
5	Supervisory system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		32
	5.1	Power on reset (POR) circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
	5.2	nRESET generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
	5.3	Thermal shut down generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .	35
6	Watchdog circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		36
7	Internal clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		38
8	Start-up configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		39
	8.1	Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
	8.2	Basic device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40
	8.3	Slave device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	41
	8.4	Master device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	41
	8.5	Single device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	41
	8.6	Sub-configurations for slave, master or single device modes . . . . . . . . .	41

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8.6.1 Bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.6.2 Primary regulator mode (KP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.6.3 Regulators mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.6.4 Simple regulator mode (KT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.6.5 Bridge + VEXT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.6.6 Secondary regulators mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9	Power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		44
10	Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		45
	10.1	Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	45
	10.2	Hibernate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	46
	10.3	Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	46
	10.4	nAWAKE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	46
11	Linear main regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		48
12	Main switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		50
	12.1	Pulse skipping operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	50
13	Switching regulator controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		52
	13.1	Pulse skipping operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	53
	13.2	Output equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	54
	13.3	Switching regulator controller application considerations . . . . . . . . . . . . .	54
14	Power bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		56
	14.1	Possible configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	59

14.1.1 Full bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 14.1.2 Parallel configuration (super bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 14.1.3 Half bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 14.1.4 Switch configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 14.1.5 Bipolar stepper configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 14.1.6 Synchronous buck regulator configuration (Bridge 3) . . . . . . . . . . . . . . 73 14.1.7 Regulation loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 14.1.8 Battery charger or switching regulator (Bridge 4) . . . . . . . . . . . . . . . . . 76

15

AD converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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15.1 Voltage divider specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

16	Current DAC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 85
17	Operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		87
18	Low voltage power switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		89
19	General purpose PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		90
	19.1	General purpose PWM generators 1 and 2 (AuxPwm1 and AuxPwm2)	. 90
	19.2	Programmable PWM generator (GpPwm) . . . . . . . . . . . . . . . . . . . . . . . .	90
20	Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		91
21	Digital comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		93
22	GPIO pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		95
	22.1	GPIO[0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	99
	22.2	GPIO[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	101
	22.3	GPIO[2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	103
	22.4	GPIO[3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	105
	22.5	GPIO[4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	107
	22.6	GPIO[5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	109
	22.7	GPIO[6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	111
	22.8	GPIO[7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	113
	22.9	GPIO[8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	115
	22.10	GPIO[9] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	117
	22.11	GPIO[10] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	119
	22.12	GPIO[11] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	121
	22.13	GPIO[12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	123
	22.14	GPIO[13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	125
	22.15	GPIO[14] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	127
23	Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		129
	23.1	Read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	129
	23.2	Write transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	130

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24	Registers list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 132
25	Schematic examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 135
26	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 137
27	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 138

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List of tables	L6460

List of tables

Table 1.	Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . 1
Table 2.	Pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
Table 3.	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
Table 4.	IC operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
Table 5.	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
Table 6.	Stretch time selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
Table 7.	Watchdog timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	37
Table 8.	Possible start-up pins state symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
Table 9.	Start-up correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40
Table 10.	Main switching regulator PWM specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	51
Table 11.	Main switching regulator current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	51
Table 12.	Switching regulator controller PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	53
Table 13.	Switching regulator controller application: feedback reference. . . . . . . . . . . . . . . . . . . . . .	54
Table 14.	PWM selection truth table for bridge 1 or 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	57
Table 15.	PWM selection truth table for bridge 3 or 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	57
Table 16.	Bridge selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	59
Table 17.	Bridge 3 and 4 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	59
Table 18.	Full bridge truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	60
Table 19.	Half bridge truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	62
Table 20.	Switch truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	63
Table 21.	Sequencer driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	66
Table 22.	Stepper driving mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	66
Table 23.	Stepper sequencer direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	67
Table 24.	DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	68
Table 25.	Internal sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	69
Table 26.	Stepper off time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	71
Table 27.	Stepper fast decay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	73
Table 28.	PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	75
Table 29.	Battery charger regulator controller PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . .	79
Table 30.	ADC truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	81
Table 31.	Channel addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	82
Table 32.	ADC sample times when working as a 8-bit ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	83
Table 33.	ADC sample time when working as a 9-bit ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	83
Table 34.	Voltage divider specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	84
Table 35.	Current DAC truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	86
Table 36.	Interrupt controller event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	91
Table 37.	Comparison type truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	94
Table 38.	DataX selection truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	94
Table 39.	GPIO functions description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	95
Table 40.	Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	97
Table 41.	GPIO[0] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	99
Table 42.	GPIO[1] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	101
Table 43.	GPIO[2] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	103
Table 44.	GPIO[3] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	105
Table 45.	GPIO[4] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	107
Table 46.	GPIO[5] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	109
Table 47.	GPIO[6] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	111
Table 48.	GPIO[7] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	113
Table 49.	GPIO[8] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	115

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Table 50. GPIO[9] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 51. GPIO[10] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 52. GPIO[11] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 53. GPIO[12] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Table 54. GPIO[13] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 55. GPIO[14] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 56. Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Table 57. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

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List of figures	L6460

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 3. VSupplyInt pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 4. Charge pump block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 5. nReset generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 6. Watchdog circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 7. Standby mode function description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 8. nAWAKE function block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 9. Linear main regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 10. Linear main regulator with external bipolar for high current . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 11. Main switching regulator functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 12. Switching regulator controller functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 13. Switching regulator controller output driving: equivalent circuit . . . . . . . . . . . . . . . . . . . . . 54 Figure 14. H Bridge block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 15. Bridge 1 and 2 PWM selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 16. Super bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 17. Half bridge configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 18. Bipolar stepper configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 19. Regulator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 20. Internal comparator functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 21. Battery charger control loop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 22. Li-ion battery charge profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 23. Simple buck regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 24. A2D block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 25. Current DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 26. Configurable 3.3 V operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 27. Low power switch block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 28. Interrupt controller diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 29. Digital comparator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 30. GPIO[0] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 31. GPIO[1] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Figure 32. GPIO[2] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Figure 33. GPIO[3] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 34. GPIO[4] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 35. GPIO[5] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 36. GPIO[6] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 37. GPIO[7] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure 38. GPIO[8] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Figure 39. GPIO[9] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Figure 40. GPIO[10] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Figure 41. GPIO[11] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Figure 42. GPIO[12] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

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Figure 43. GPIO[13] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Figure 44. GPIO[14] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Figure 45. SPI read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Figure 46. SPI write transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Figure 47. SPI input timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 48. SPI output timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 49. Application with 2 DC motors, 1 stepper motor and 3 power supplies . . . . . . . . . . . . . . . 135 Figure 50. Application with 2 DC motors, a battery charger and 5 power supplies . . . . . . . . . . . . . . 136 Figure 51. TQFP64 mechanical data an package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

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General description	L6460

1 General description

1.1Overview

L6460 offers the possibility to control and power multi motor systems, through the management of simultaneous driving of stepper and DC motor. A number of features can be configured through the digital interface (SPI), including 3 voltage regulators, 1 high precision A/D converter, 2 operational amplifiers and 14 configurable GPIOs.

The high flexibility allows the possibility to configure two, one full or half bridge to work as power stage featuring additional voltage buck regulators.

Figure 1. Block diagram

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Note:

See following Chapter 2 for a detailed description of possible configurations.

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L6460	General description

1.2Pin connection

Figure 2. Pin connection

				DC1 PLUS				VSupply				CPL				CPH				VPump				VSWDRV GATE				VSWDRV SW				GPIO6				VGPIO SPI				GPIO7				VSupplyInt				V3V3				nRESET				VSupply				DC3 PLUS				N.C.
				64				63				62				61				60				59				58				57				56				55				54				53				52				51				50				49
DC1_PLUS																																																																			DC3_SENSE
	1																																																																	48
VSWDRV_SNS						GND_PAD																																																													GPIO5
	2																																																																	47
																																																																			GPIO9
VSWDRV_FB	3																																																																	46
																																																																			GPIO10
GPIO4	4																																																																	45
																																																																			GPIO11
GPIO3	5																																																																	44
																																																																			N.C.
DC1_MINUS	6																																																																	43
																																																																			DC3_MINUS
DC1_MINUS	7																																																																	42
																																																																			DC3_SENSE
GND1	8																																																																	41
GND2																																																																			DC4_SENSE
	9																																																																	40
DC2_MINUS																																																																			DC4_MINUS
	10																																																																	39
DC2_MINUS																																																																			N.C.
	11																																																																	38
GPIO2																																																																			GPIO14
	12																																																																	37
GPIO1																																																																			GPIO13
	13																																																																	36
GPIO0																																																																			GPIO12
	14																																																																	35
nSS																																																																			nAWAKE
	15																																																																	34
DC2_PLUS																																																																			DC4_SENSE
	16																																																																	33
			17				18				19				20				21				22				23				24				25				26				27				28				29				30				31				32
			DC2 PLUS				VSupply				MISO				MOSI				VLINmain FB				VLINmain OUT				GPIO8				VSWmain SW				VSupply				VSWmain FB				VREF FB				IREF FB				SCLK				VSupply				DC4 PLUS				N.C.

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General description	L6460

1.3Pin list

Table 2.		Pins configuration
Pin #		Pin name	Description	Type
1		DC1_PLUS	Bridge 1 phase “plus” output	Output
2		VSWDRV_SNS	Switching regulator controller sense	Analog input
3		VSWDRV_FB	Switching regulator controller feedback	Analog input
4		GPIO4	General purpose I/O	Analog In/Out - CMOS bi-dir
5		GPIO3	General purpose I/O	Analog In/Out - CMOS bi-dir
6		DC1_MINUS	Bridge 1 phase “minus” output	Output
7		DC1_MINUS	Bridge 1 phase “minus” output	Output
8		GND1	Ground pin for bridge1(1)(2)(3)	Power/digital
9		GND2	Ground pin for bridge2(1)(2)(3)	Power/digital
10		DC2_MINUS	Bridge 2 phase “minus” output	Output
11		DC2_MINUS	Bridge 2 phase “minus” output	Output
12		GPIO2	General purpose I/O	Analog In/Out - CMOS bi-dir
13		GPIO1	General purpose I/O	Analog In/Out - CMOS bi-dir
14		GPIO0	General purpose I/O	Analog Input - CMOS input
15		nSS	SPI chip select pin	CMOS input
16		DC2_PLUS	Bridge 2 phase “plus” output	Output
17		DC2_PLUS	Bridge 2 phase “plus” output	Output
18		VSupply	Main voltage supply	Power input
19		MISO	SPI serial data output	CMOS output
20		MOSI	SPI serial data input	CMOS input
21		VLINmain_FB	Linear main regulator feedback	Analog input
22		VLINmain_OUT	Linear main regulator output	Power output
23		GPIO 8	General purpose I/O	Analog In/Out - CMOS bi-dir
24		VSWmain_SW	Main switching regulator switching output	Power output
25		VSupply	Main voltage supply	Power Input
26		VSWmain_FB	Main switching regulator feedback pin	Analog input
27		VREF_FB	Regulator voltage feedback	Analog input
28		IREF_FB	Regulator current feedback	Analog input
29		SCLK	SPI input clock pin	CMOS input
30		VSupply	Main voltage supply	Power input
31		DC4_PLUS	Bridge 4 phase “plus” output	Output
32		N.C.	Not connected
33		DC4_SENSE	Bridge 4 sense output(4)	Output
34		nAWAKE	Device wake up	CMOS input

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L6460					General description
	Table 2.		Pins configuration (continued)
	Pin #		Pin name	Description	Type
	35		GPIO12	General purpose I/O	Analog In/Out - CMOS bi-dir
	36		GPIO13	General purpose I/O	Analog In/Out - CMOS bi-dir
	37		GPIO14	General purpose I/O	Analog In/Out - CMOS bi-dir
	38		N.C.	Not connected
	39		DC4_MINUS	Bridge 4 phase “minus” output	Output
	40		DC4_SENSE	Bridge 4 sense output(4)	Output
	41		DC3_SENSE	Bridge 3 sense output(4)	Output
	42		DC3_MINUS	Bridge 3 phase “minus” output	Output
	43		N.C.	Not connected
	44		GPIO11	General purpose I/O	Analog In/Out - CMOS bi-dir
	45		GPIO10	General purpose I/O	Analog In/Out - CMOS bi-dir
	46		GPIO9	General purpose I/O	Analog In/Out - CMOS bi-dir
	47		GPIO5	General purpose I/O	Analog In/Out - CMOS bi-dir
	48		DC3_SENSE	Bridge 3 sense output(4)	Output
	49		N.C.	Not connected
	50		DC3_PLUS	Bridge 3 phase “plus” output	Output
	51		VSupply	Main voltage supply	Power input
	52		nRESET	Open drain system reset pin	CMOS Input/output
	53		V3v3	Internal 3.3 volt regulator	Power Input/output
	54		VSupplyInt	Internal voltage supply	Power Input
	55		GPIO7	General purpose I/O	Analog In/Out - CMOS bi-dir
	56		VGPIO_SPI	Low voltage pins power supply	Power input
	57		GPIO6	General purpose I/O	Analog In/Out - CMOS bi-dir
	58		VSWDRV_SW	Switching regulator controller source input	Power input
	59		VSWDRV_GATE	Switching driver gate drive pin	Analog output
	60		VPump	Charge pump voltage	Power Input/output
	61		CPH	Charge pump high switch pin	Power Input/output
	62		CPL	Charge pump low switch pin	Power Input/output
	63		VSupply	Main voltage supply	Power input
	64		DC1_plus	Bridge 1 phase “plus” output	Output
	E_Pad		GND_PAD	(1)(2)(3)

1.These pins must be connected all together to a unique PCB ground.

2.Bridges1 and 2 have 2 ground pads: one is bonded to the relative ground pin (GND1 or GND2) and the other is connected to exposed pad (E_Pad) ground ring. This makes the bond wires testing possible by forcing a current between E-Pad and GND1 or GND2 pins and using the other pin as sense pin to measure the resistance of E-Pad bonding. (N.B: grounds of two bridges are internally connected together).

3.The analog ground is connected to exposed pad E-Pad.

4.The pin must be tied to ground if bridge is not used as a stepper motor.

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L6460’s main features	L6460

2 L6460’s main features

L6460 includes the following circuits:

●Four widely configurable full bridges:

–Bridges 1 and 2:

–Diagonal RDSon: 0.6 Ω typ.

–Max operative current = 2.5 A.

–Bridges 3 and 4:

–Diagonal RDSon: 0.85 Ω typ.

–Max operative current = 1.5 A.

●Possible configurations for each bridge are the following:

–Bridge 1:

–DC motor driver.

–Super DC (bridge 1 and 2 paralleled form superbridge1).

–2 independent half bridges.

–1 super half bridge (bridge 1 side A and bridge 1 side B paralleled form superhalfbridge1).

–2 independent switches (high or low side).

–1 super switch (high or low side).

–Bridge 2 has the same configurations of bridge 1.

–Bridge 3 has the same configurations of bridge 1 (bridge 3 and 4 paralleled form superbridge2) plus the following:

–½ stepper motor driver.

–2 buck regulators (VAUX1_SW, VAUX2_SW).

–1 Super buck regulator (VAUX1//2_SW).

–Bridge 4 has the same configurations of bridge 1 plus the following:

–½ stepper motor driver.

–1 super buck regulator (VAUX3_SW).

–Battery charger.

●One buck type switching regulator (VSWmain) with:

–Output regulated voltage range: 1-5 Volts.

–Output load current: 3.0 A.

–Internal output power DMOS.

–Internal soft start sequence.

–Internal PWM generation.

–Switching frequency: ~250 kHz.

–Pulse skipping strategy control.

●One switching regulator controller (VSWDRV) with:

–Output regulated voltage range: 1-30 Volts.

–Selectable current limitation.

–Internal PWM generation.

–Pulse skipping strategy control.

●One linear regulator (VLINmain) that can be used to generate low current/low ripple

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L6460	L6460’s main features

voltages. This regulator can be used to drive an external bipolar pass transistor to generate high current/low ripple output voltages.

●One bidirectional serial interface with address detection so that different ICs can share the same data bus.

●Integrated power sequencing and supervisory functions with fault signaling through serial interface and external reset pin.

●Fourteen general purpose I/Os that can be used to drive/read internal/external analog/logic signals.

●One 8-bit/9-bit A/D converter (100 kS/s @ 9-bit, 200 kS/s @8-bit). It can be used to measure most of the internal signals, of the input pins and a voltage proportional to IC temperature.

–Current sink DAC:

–Three output current ranges: up to 0.64/6.4/64 mA.

–64 (6-bit programmable) available current levels for each range.

–5 V output tolerant.

●Two operational amplifiers:

–3.3 V supply, rail to rail input compatibility, internally compensated.

–They can have all pins externally accessible or can be internally configured as a buffer o make internal reference voltages available outside of the chip.

–Unity gain bandwidth > 1 MHz.

–They can also be set as comparators with 3.3 V input compatibility and low offset.

●Two 3.3 V pass switches with 1 Ω RDSon and short circuit protected.

●Programmable watchdog function.

●Thermal shutdown protection with thermal warning capability.

●Very low power dissipation in “low power mode” (~35 mW)

L6460 is intended to maximize the use of its components, so when an internal circuit is not used it could be employed for other applications. Bridge 3, for example, can be used as a full bridge or to implement two switching regulators with synchronous rectification: to obtain this flexibility L6460 includes 2 separate regulation loops for these regulators; when the bridge is used as a motor driver, the 2 regulation loops can be redirected on general purpose I/Os to leave the possibility to assembly a switching regulator by only adding an external FET.

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Electrical specifications	L6460

3 Electrical specifications

3.1Absolute maximum rating

The following specifications define the maximum range of voltages or currents for L6460.

Stresses above these absolute maximum specifications may cause permanent damage to the device. Exposure to absolute maximum ratings for extended periods may affect device reliability.

	Table 3.	Absolute maximum ratings
	Parameter		Description	Test	Min	Max	Unit
				condition
	VSupply		VSupply voltage			40	V
	VGPIO_SPI		VGPIO_SPI voltage			3.9	V
	V3V3pin		V3V3 voltage		-0.3	3.9	V
	VSW		Switching regulators output pin voltage		-1	VSupply	V
			range
	VSW_pulse		Switching regulators min pulsed	tpulse <	-3		V
			voltage	500ns
	VPump		Charge pump voltage	(1)		15	V
	TJ		Junction temperature(2)	Storage	-40	190	°C
				Operating	-40	TSD	°C

1.This value is useful to define the voltage rating for external capacitor to be connected from VPump to VSupply. VPump is internally generated and can never be supplied by external voltage source nor is intended to provide voltage to external loads.

2.TSD is the thermal shut down temperature of the device.

3.2Operating ratings specifications

Table 4.	IC operating ratings
Parameter		Description	Test	Min	Max	Unit
			condition
VSupply		VSupply voltage range		13 (1)	38	V
ISupply		VSupply operative current	(2)		15	mA
IShut_down		VSupply shut down state current			1.5	mA
VGPIO_SPI		VGPIO_SPI voltage range		2.4	3.6	V
IVGPIO_SPI		VGPIO_SPI operative current	(3)		0.4	mA
V3v3		3.3V input pin voltage range			3.6	V
VLINmain_OUT		Output pin voltage range	(4)	0	VSupply	V
VLINmain_FB		Feedback pin voltage range		0	3.6	V
VSWmain_SW		Output pin voltage range	(4)	-1	Vsupply	V
VSWDRV_SW		VSWDRV_SW pin voltage range	(4)	-1	VSupply	V

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L6460						Electrical specifications
	Table 4.		IC operating ratings
	Parameter			Description	Test		Min	Max		Unit
					condition
	VSWDRV_GATE			Gate drive pin voltage			0	VPump		V
	V	SWDRV_SNS		Sense pin voltage			VSupply	V	Supply	V
							-3V
		TJ		Junction temperature	Operating		-40		125	°C

1.For Vsupply lower than 21 V an external resistor between Vsupply and Vsupply Int pins are required. For Vsupply lower than 15 V external diodes for charge pump are required.

2.Operating supply current is measured with system regulators operating but not loaded.

3.Operating VGPIO_SPI current is measured with all circuits supplied by VGPIO_SPI (GPIO’s, operational amplifiers and pass switches) enabled but not loaded.

4.The external components connected to the pin must be chosen to avoid that the voltage exceeds this operative range.

3.3Electrical characteristics

Table 5.	Electrical characteristics
Parameter		Description	Test condition	Min	Typ	Max	Unit
VSupplyInt regulator
VS_Int		VSupplyInt output voltage	(1)	18	19.5	21	V
IS_Int		VSupplyInt operative current	(2)		11		mA
Charge pump VPump
VPump		Charge pump voltage	VSupply=32V	VSupply	VSupply	VSupply	V
				+ 10.5	+12.5	+ 14.5
FPump		VPump clock frequency	FOSC = 16MHz typ		FOSC/6		kHz
					4
V3V3 regulator
V3V3		V3v3 output voltage	VSupply=32V	3.15	3.3	3.45	V
Power on reset
VSupply_POR_valid		VSupply voltage for POR valid	InRESET = 1mA	4			V
VSupply_POR_fall		VSupply POR falling threshold	VSupply falling	6		8	V
tSupply_POR_filt		VSupply POR filter Time			3		µs
V3V3_POR_fall		V3v3 POR falling threshold	V3V3 falling	1.9	2.2		V
V3V3_POR_rise		V3v3 POR rising threshold	V3V3 rising		2.7		V
V3V3_POR_hys		V3v3 POR hysteresis			0.5		V
t3V3_POR_filt		V3v3 POR filter time			1.5		µs
nRESET circuit
VnRST_L		nRESET low level output	I=10mA			0.4	V
		voltage

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Electrical specifications							L6460
Table 5.	Electrical characteristics (continued)
Parameter		Description	Test condition	Min	Typ	Max	Unit
tnRST_fall		nRESET fall time	I=1mA			15	ns
			(3)
			C=50pF
tnRST_del		nRESET delay time	(4)			150	ns
VSupply_UV_f		VSupply falling threshold		10.2	11	11.8	V
VSupply_UV_r		VSupply rising threshold		10.5	11.5	12.5	V
VSupply_UV_hys		VSupply hysteresis		0.3	0.5	0.7	V
tSupply_UV		VSupply UV filter time			3.5		µs
VS_Int_UV_f		VSupplyInt falling threshold		9.7	10.7	11.7	V
VS_Int_UV_r		VSupplyInt rising threshold		10.6	11.4	12.2	V
VS_Int_UV_hys		VSupplyInt hysteresis		0.4	0.7	1	V
tS_Int_UV		VSupplyInt UV filter time			3.5		µs
VPump_UV_f		VPump falling threshold		VSupply	VSupply	VSupply	V
				+7	+ 7.5	+ 8
VPump_UV_r		VPump rising threshold		VSupply	VSupply	VSupply	V
				+ 7.5	+ 8	+ 8.5
VPump_UV_hys		VPump hysteresis		0.3	0.5	0.7	V
tPump_UV		VPump UV filter time			3.5		µs
VGPIO_SPI_UV_f		VGPIO_SPI falling threshold		1.8	2		V
VGPIO_SPI_UV_r		VGPIO_SPI rising threshold			2.2	2.4	V
VGPIO_SPI_hys		VGPIO_SPI hysteresis		200	250	300	mV
tGPIO_SPI_UV		VGPIO_SPI UV filter time			3.5		µs
TSD circuit
TTSD		Thermal shut down			170		°C
		temperature
TWARM		Warming temperature			140		°C
TDIFF		Thermal shut down to warming			30		°C
		difference
tTSD_FILT		Thermal shut down filter time			8		µs
tWARM_FILT		Warming filter time			8		µs
Watchdog
WD_Tclk		Watchdog clock period			Tosc *		s
					22
					2
Internal clock
Fosc		Oscillator frequency	V3V3 = 3.3 V	14.1	16	17.6	MHz
nAWAKE function
VIL		nAWAKE low logic level				0.8	V
		voltage

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Doc ID 17713 Rev 1

L6460				Electrical specifications
Table 5.	Electrical characteristics (continued)
Parameter		Description	Test condition	Min	Typ	Max	Unit
VIH		nAWAKE high logic level		1.6			V
		voltage
VHYS		nAWAKE input hysteresis			0.25		V
IOUT		nAWAKE pin output current	nAWAKE=0V(5)	-0.72		-2	mA
IINP		nAWAKE pin input current	nAWAKE=0.8V(5)	0.2		0.4	mA
tAWAKEFILT		Filter time			1.2		μs
Main linear regulator
Vdrop		Drop out voltage	Vdrop=	2			V
			Vsupply-VLINmain_OUT
IPD		Internal switch pull down	Linear Main Regulator		3		mA
		current	disabled; VLINmain_OUT=1V
VLINmain_Ref		Feedback reference voltage		0.776	0.8	0.824	V
ILINmain_Ref		Feedback pin input current		-2		2	µA
IoutLINMax		Maximum output current	VLINmain_OUT= Vsupply-2V	10			mA
Ishort		Output short	VLINmain_OUT =0V,	12	24	32	mA
		circuit current	VLINmain_FB =0V
Vout/Vo		Load regulation	(6)			0.8	%
			0 ≤ Iload ≤ IoutLINMax
Vout/ VSupply		Line regulation	Iload =10mA(6)			0.2	%
Vloop_acc		Loop voltage accuracy			±2.5		%
VLIN_UV_f		Undervoltage falling threshold	(7)	84.5	87	89.5	%
VLIN_UV_r		Undervoltage rising threshold	(7)	90.5	93	95.5	%
VLIN_UV_hys		Undervoltage hysteresis			6		%
tprim_uv		Under voltage deglitch filter			5		µs
Main switching regulator
			SelFBref = ‘00’	0.776	0.8	0.824	V
VFBREF		Main switching regulator	SelFBref = ‘01’ (8)	0.97	1	1.03	V
		feedback reference voltage	SelFBref = ‘10’	2.425	2.5	2.575	V
			SelFBref = ‘11’	2.91	3	3.09	V
IQ		Output leakage current	Tjunction = 125°C	-40		+40	µA
IQ_LP		Output leakage current in	VSupply = 36V	-15		+15	µA
		“low power mode”	Tjunction = 125°C
ISWmain_FB		VSWmain_FB pin current	Tjunction = 125°C	-10		+10	µA
VSWmain_OUT		Output voltage range	(9)	0.8		5	V
Iload		Maximum output load current	VSupply = 36V	0.002		3	A
RDSonHS		Internal high side RDSon	Iload=1A		0.33	0.95	Ω
			Tjunction = 125°C

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Electrical specifications								L6460
Table 5.	Electrical characteristics (continued)
Parameter		Description	Test condition		Min	Typ	Max	Unit
Vloop		Loop voltage accuracy				±3%
VSW_UV_f		Under voltage falling threshold	(10)		84.5	87	89.5	%
VSW_UV_r		Under voltage rising threshold	(10)		90.5	93	95.5	%
VSW_UV_hys		Under voltage hysteresis				6		%
tprim_uv		Under voltage deglitch filter				5		µs
Ilimit		Current limit protection	SelIlimit =”0”		3.3	5		A
			SelIlimit =”1”		2.3	3.5		A
tdeglitch		Current limit deglitch time			50			ns
tI_lim		Current limit response time	Normal operating mode (no			450	650	ns
			(11)
			UV)
tI_limUV		Current limit response time in	UV condition (12)			200	400	ns
		UV condition
tr		Switching output rise time	VSupply = 36V,		5		30	ns
			R	= 422 Ω(13)
			LOAD
tf		Switching output fall time	VSupply = 36V,		5		30	ns
			R	= 10 Ω(13)
			LOAD
FSW_PWM		Operating frequency				Fosc/6		kHz
						4
Switching regulator controller
VGS_ext		Gate to source voltage for				VPump		V
		external FET
ISOURCE		Source current	VPump=VSupply+12V		25		50	mA
			VSWCTR_GATE=0V
ISINK		Sink current	VSWCTR_GATE = VSupply		20			mA
tSINK		Sink discharge pulse time				600		ns
RSUSTAIN		Gate-source sustain	(VSWCTR_GATE -			650		Ω
		resistance	VSWCTR_SRC) = 0.2V
IQ		Output	VSupply = 36V,		-40		+40	µA
		leakage current	Tjunction = 125°C
IQ_LP		Output leakage current in	VSupply = 36V,		-5		+5	µA
		“Low Power Mode”	Tjunction = 125°C
			SelFBref = ‘00’ (8)		0.776	0.8	0.824	V
		Switching regulator feedback
			SelFBref = ‘01’		0.97	1	1.03	V
VFBREF		controller feedback reference
			SelFBref = ‘10’		2.425	2.5	2.575	V
		voltage
			SelFBref = ‘11’		2.91	3	3.09	V
ISWDRV_FB		VSWDRV_FB pin current	VSupply = 36V,		-10		+10	µA
			Tjunction = 125°C
Vloop		Loop voltage accuracy				±3%

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Doc ID 17713 Rev 1

L6460					Electrical specifications
Table 5.	Electrical characteristics (continued)
Parameter		Description	Test condition		Min	Typ	Max	Unit
VSWD_UV_f		Under voltage falling threshold	(14)		84.5	87	89.5	%
VSWD_UV_r		Under voltage rising threshold	(14)		90.5	93	95.5	%
VSWD_UV_hys		Under voltage hysteresis				6		%
tprim_uv		Under voltage deglitch filter				5		µs
Vovc		Over current threshold voltage			250	300	350	mV
tdeglitch		Current limit deglitch time			50			ns
tI_lim		Current limit response time	Normal operating mode (no			500	900	ns
			UV) (11)
tI_limUV		Current Limit response time in	UV condition (12)			380	550	ns
		UV condition.
FSWD_PWM		Operating frequency				Fosc/64		kHz
Power bridges
RDSon1_2		Bridge 1 and 2 diagonal RDSon	I = 1.4A, VSupply = 36V,			0.6	1.1	Ω
			T	= 125°C
			junction
RDSon3_4		Bridge 3 and 4 diagonal RDSon	I = 1A, VSupply = 36V,			0.85	1.65	Ω
			T	= 125°C
			junction
IMAX1_2		Bridge 1 and 2 operative rms					2.5	A
		current
IMAX3_4		Bridge 3 and 4 operative rms					1.5	A
		current
Idss		Output leakage current.	Tjunction = 125°C		-50		+50	µA
IQ_LP		Output leakage current in “low	VSupply = 36V,		-10		+10	µA
		power mode”	Tjunction = 125°C
			MtrXSideYILimSel[1:0]=00		0.6	1	1.6
		Low side current protection for	MtrXSideYILimSel[1:0]=01		1.4	2	2.6
IOC_LS1_2			MtrXSideYILimSel[1:0]=10		2.4	3	3.6	A
		bridges 1 and 2(15)
			MtrXSideYILimSel[1:0]=11		2.4	3	3.6
			(16)
			MtrXSideYILimSel[1:0]=00		0.7	1	1.7
		High side current protection for	MtrXSideYILimSel[1:0]=01		1.5	2	2.7
IOC_HS1_2			MtrXSideYILimSel[1:0]=10		2.5	3	3.7	A
		bridges 1 and 2(15)
			MtrXSideYILimSel[1:0]=11(1		2.5	3	3.7
			6)
IOC_LS3_4		Low side current protection for	MtrXSideYILimSel[1:0]=11		1.55		2.5	A
		bridges 3 and 4(15)	(17)(18)
IOC_HS3_4		High side current protection for	MtrXSideYILimSel[1:0]=11(1		1.6		2.5	A
		bridges 3 and 4(15)	7)(18)
tfilter		Current limit			2		5	μs
		filter time

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Electrical specifications							L6460
Table 5.	Electrical characteristics (continued)
Parameter		Description	Test condition	Min	Typ	Max	Unit
tdelay		Current limit			5		μs
		delay time
			MtrXIlimitOffTimeY[1:0]=00		60		µs
			MtrXIlimitOffTimeY[1:0]=01
					120		µs
tOC_off		Over current Off time	MtrXIlimitOffTimeY[1:0]=10
					240		µs
			MtrXIlimitOffTimeY[1:0]=11
					480		µs
			(19)
tr1_2		Output rise time	VSupply = 36V, resistive load	100	180	250	ns
		bridges 1 and 2	between outputs:
			R= 25 Ω(20)
tr3_4		Output rise time	VSupply = 36V, resistive load	50	100	200	ns
		bridges 3 and 4	between outputs:
			R= 36 Ω(20)
		Output fall time	VSupply = 36V, resistive load
tf1_2			between outputs:	100	180	250	ns
		bridges 1 and 2
			R= 25 Ω(20)
		Output fall time	VSupply = 36V, resistive load
tf3_4			between outputs:	50	125	250	ns
		bridges 3 and 4
			R= 36 Ω(20)
tdeadRise		Anti crossover rising dead time		100	300	450	ns
tdeadFall		Anti crossover falling dead		100	300	450	ns
		time
FPWM		Operating frequency			Fosc/51		kHz
					2
tresp		Delay from PWM to output			500		ns
		transition
Bipolar stepper circuitry
VSTEPREF		Reference voltage	SelStepRef =0	0.48	0.50	0.52	V
			SelStepRef =1	0.72	0.75	0.78
Voffset		Sense comparator offset		-12		12	mV
			StepBlkTime = ‘00’ (8)	0.65	0.95	1.25	µs
tblk		Blanking time	StepBlkTime = ‘01’	1	1.45	1.9	µs
			StepBlkTime = ‘10’	1.5	2.25	3	µs
			StepBlkTime = ‘11’	3	4.25	5.5	µs
Synchronous buck regulator (bridge 3)
VAUX_SW		Output pin voltage range	(26)	-1		VSupply	V
		(DC3x)
IQ		Output leakage current	Tjunction = 125°C	-50		+50	µA
IQLP		Output leakage current in “Low	VSupply = 36V	-10		+10	µA
		Power Mode”	Tjunction = 125°C

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Doc ID 17713 Rev 1

L6460						Electrical specifications
Table 5.	Electrical characteristics (continued)
Parameter		Description	Test condition			Min	Typ	Max	Unit
			SelFBRef = ‘00’			0.776	0.8	0.824	V
VFBREF		Synchronous buck regulator	SelFBRef = ‘01’ (21)			0.97	1	1.03	V
		feedback reference voltage	SelFBRef = ‘10’		(22)	2.425	2.5	2.575	V
			SelFBRef = ‘11’			2.91	3	3.09	V
IGPIO_FB		GPIO feedback pin current	Tjunction = 125°C			-15		15	µA
			0V≤Feedback ≤ 3V
Vout		Output voltage range	VSupply = 36V(23)			0.8		30	V
Iload		Output load current	VSupply = 36V			0.002		1.5	A
RDSonHS		Internal high/low side RDSon	Tjunction = 125°C; Iload=1A				0.6	0.8	Ω
Vloop		Loop voltage accuracy					±3%
VREG_UV_f		Under voltage falling threshold	(24)			84.5	87	89.5	%
VREG_UV_r		Under voltage rising threshold	(24)			90.5	93	95.5	%
VREG_UV_hys		Under voltage hysteresis					6		%
taux_UV		Under voltage deglitch filter					5		µs
Ilimit		Current limit protection				1.6		2.5	A
tdeglitch		Current limit deglitch time				50			ns
tI_lim		Current limit response time	Normal operating mode				480	700	ns
			(no UV) (11)
tI_limUV		Current limit response time in	UV condition (12)				350	500	ns
		UV condition.
tr		Switching output rise time	VSupply = 36V,			5		30	ns
			R	= 422 Ω(25)
			LOAD
tf		Switching output fall time	VSupply = 36V,			10		50	ns
			R	= 10 Ω (23)
			LOAD
tdead		Crossover dead time					100		ns
FREGPWM		Operating frequency					Fosc/64		kHz
Battery charger (Bridge 4)
VAUX3_SW		Output pin voltage range	(26)			-1		VSupply	V
		(DC4x)
IQ		Output leakage current	Tjunction = 125°C			-100		+100	µA
			SelFBRef = ‘00’			1.37	1.412	1.455	V
VFBRef		Battery charger control loop	SelFBRef = ‘01’ (8)			1.746	1.8	1.854	V
		feedback reference voltage	SelFBRef = ‘10’			2.079	2.143	2.207	V
			SelFBRef = ‘11’			2.425	2.5	2.575	V

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Electrical specifications								L6460
Table 5.	Electrical characteristics (continued)
Parameter		Description	Test condition		Min	Typ	Max	Unit
			SelCurrRef = ‘00’ (8)		0.873	0.9	0.927	V
VCurrRef		Battery charger control loop	SelCurrRef = ‘01’		1.394	1.437	1.48	V
		feedback reference current	SelCurrRef = ‘10’		1.746	1.8	1.854	V
			SelCurrRef = ‘11’		2.182	2.25	2.318	V
V		Output voltage range	V	= 36V (27)	1.412		30	V
out			Supply
Iload		Output load current	VSupply = 36V		0.002		3	A
RDSon		Internal high/low side RDSon	Tjunction = 125°C;			0.3	0.4	Ω
			ILOAD = 1.5A
Vloop		Loop voltage accuracy				±3%
VBC_UV_f		Under voltage falling threshold	(28)		84.5	87	89.5	%
VBC_UV_r		Under voltage rising threshold	(28)		90.5	93	95.5	%
VBC_UV_hys		Under voltage hysteresis				6		%
taux_UV		Under voltage deglitch filter				5		µs
Ilimit		Current limit protection			3.2		5	A
tdeglitch		Current limit deglitch time			50			ns
tI_lim		Current limit response time	Normal operating mode			480	700	ns
			(no UV) (11)
tI_limUV		Current limit response time in	UV condition (12)			350	500	ns
		UV condition.
tr		Switching output rise time	VSupply = 36V,		5		30	ns
			R	= 422 Ω (25)
			LOAD
tf		Switching output fall time	VSupply = 36V,		10		50	ns
			R	= 10 Ω (25)
			LOAD
tdead		Crossover dead time				100		ns
FBCPWM		Operating frequency				Fosc/64		kHz
ADC with A2DType=0 (29)
IMR		Measurement range	A2dType = 0		0		V3v3	V
INL		Integral non-linearity	A2dType = 0(30)(31)				±2	LSB
DNL		Differential non-linearity	A2dType = 0(32)(31)				±2	LSB
OE		Offset error	A2dType = 0(33)				±4	LSB
OEDrift		Offset error drift	A2dType = 0 over time				±3	LSB
			and temperature
GE		Gain error	A2dType = 0(34)				±4	LSB
GEDrift		Gain error drift	A2dType = 0 over time				±4	LSB
			and temperature
tconv		Minimum conversion time					55	µs
		Resolution	(35)			8		bits

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Doc ID 17713 Rev 1

L6460				Electrical specifications
Table 5.	Electrical characteristics (continued)
Parameter		Description	Test condition	Min	Typ	Max	Unit
Cin		Input sampling capacitance	(36)			4	pF
ADC with A2DType=1 (37)
IMR		Measurement range	A2dType = 1	0		V3v3	V
INL		Integral non-linearity	A2dType = 1 (30)(31)			±1	LSB
DNL		Differential Non-Linearity	A2dType = 1 (32)(31)			±1	LSB
OE		Offset error	A2dType = 1 (33)			±4	LSB
OEDrift		Offset error drift	A2dType = 1 over time and			±3	LSB
			temperature
GE		Gain error	A2dType = 1 (34)			±4	LSB
GEDrift		Gain error drift	A2dType = 1			±4	LSB
			over time and temperature
tconv		Minimum conversion time				10	µs
		Resolution			9		bits
Cin		Input sampling capacitance	(36)			4	pF
Current DAC
VR		Pin voltage operative range	(38)	0.7		5.5	V
		(GPIO8)
IOUT_OFF		Output off leakage current	DacValue[5:0] = 000000	-1		+1	µA
			DacRange[1:0] =xx				% of
IFULL_ERR		Full scale current error		-15		+15	IFULL
			DacValue[5:0] = 111111
							typ
INL10_11		Integral non-linearity for 10				±2	LSB
		and 11 ranges
DNL10_11		Differential non-linearity for 10				±2	LSB
		and 11 ranges
INL01		Integral non-linearity for 01				±1	LSB
		range
DNL01		Differential non-linearity for 01				±1	LSB
		range
RCurrDac_res		Gpio[8] divider total resistance			45		kΩ
RCurrDac_ratio		Gpio[8] divider ratio			3/5
tset		Settling time	(39)			5	µs
Operational amplifier (40)
VGPIO_SPI		Operational amplifier supply		3.15	3.3	3.45	V
		voltage range
VICM		Input common mode voltage		0		VGPIO_	V
		range				SPI
VOUT_MAX		Output voltage	ILOAD =± 1mA	0.1		3.2	V

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Electrical specifications								L6460
Table 5.	Electrical characteristics (continued)
Parameter		Description		Test condition	Min	Typ	Max	Unit
			OpxRef[1:0]=00		0.97	1	1.03
					1.6	1.65	1.7
VOp1PlusRef		Operational amplifier 1 and 2	OpxRef[1:0]=01					V
		reference voltage	OpxRef[1:0]=10		1.94	2	2.06
VOp2PlusRef
			OpxRef[1:0]=11		2.425	2.5	2.575
Avd		Open loop gain	VICM=1.65V		90			dB
			ILOAD= 0mA
CMRR		Common mode rejection ratio			80	110		dB
PSRR		Power supply rejection ratio	ILOAD= ±6mA			90		dB
			VICM=1.65V
I in _offs		Input offset current			-150		150	nA
I in _bias		Input bias current			-500		500	nA
V in _offs		Input offset voltage			-5		5	mV
GBWP		Gain bandwidth product	Cload=100pF VICM=1.65V		2			MHz
			Rload=330 Ω to VGPIO_SPI
Iout		Output current	Vout=1.65V				10	mA
Ishort_max		Short circuit current			12	20		mA
SR		Slew rate	Iload= 0		1.3	1.75		V/µs
			CLOAD=100pF
Operational amplifier used as comparator (40) (41)
VOUT_MAX		Output voltage	Iload =± 10mA		0.3		2.9	V
tOFF			VCM = 1.65V
		Turn off propagation delay		Vi = -/+ 20mV		0.6	1	µs
			C	=100pF (42)(43)
				LOAD
tFALL		Fall time	VCM = 1.65V			0.15	0.4	µs
				Vi = -/+ 20mV
			C	=100pF (42)(43)
				LOAD
tON		Turn on propagation delay	VCM = 1.65V			0.25	0.5	µs
				Vi = -/+ 20mV
			C	=100pF (42)(43)
				LOAD
tRISE		Rise time	VCM = 1.65V			0.2	0.4	µs
				Vi = -/+ 20mV
			C	=100pF (42)(43)
				LOAD
Low power switch
VPSW		Input voltage range			2.4		3.6	V
VOUT_MAX		Output voltage					VGPIO_	V
							SPI
RDSon		Switch RDSon resistance	Iload=100mA			0.6	1	Ω
ILIMIT		Current limit			150	250	350	mA
tdeglitch		Current limit deglitch time			50			ns

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L6460							Electrical specifications
Table 5.		Electrical characteristics (continued)
Parameter			Description		Test condition		Min	Typ	Max	Unit
	tI_lim		Current limit response time						650	ns
CLOAD			Max load capacitance						2.5	µF
	tON		Turn on propagation delay	VGPIO_SPI=3.3V ILOAD=1mA				450	650	ns
				C	LOAD	=100pF(44)
				VGPIO_SPI=3.3V
	tOFF		Turn off propagation delay	ILOAD=1mA				250	450	ns
				C	LOAD	=100pF(44)
Interrupt controller
tPULSE			Pulse duration					16*Tosc		µs
tINTFILT			Filter time					200		ns
GPIO[0], GPIO[1], GPIO[2], GPIO[3], GPIO[4], GPIO[6]
	VIH		High level input voltage				1.6			V
	VIL		Low level input voltage						0.8	V
VHYS			Input voltage hysteresis				0.15	0.22		V
	VOL		Low level output voltage	IOUT = 15mA					0.5	V
ILEAKAGE			Leakage current	0 ≤ Vout ≤ V3v3			-1		1	µA
t	DELAY		Delay from serial write to pin	C	LOAD	=50 pF(45)			500	ns
			Low
GPIO[5], GPIO[7], GPIO[9], GPIO[10], GPIO[11], GPIO[12], GPIO[13], GPIO[14]
	VIH		High level input voltage				1.6			V
	VIL		Low level input voltage						0.8	V
VHYS			Input voltage hysteresis				0.15	0.22		V
	VOL		Low level output voltage	IOUT = 15mA					0.5	V
	VOH		High level output voltage	IOUT = 5mA			2.75			V
ILEAKAGE			Leakage current	0 ≤Vout ≤ V3v3			-1		1	µA
t	DELAY		Delay from serial write to pin	C	LOAD	=50 pF(45)			500	ns
			low
GPIO[8]
	VIH		High level input voltage				1.6			V
	VIL		Low level input voltage						0.8	V
VHYS			Input voltage hysteresis				0.13	0.22		V
	VOL		Low level output voltage	IOUT = 15mA,					0.4	V
ILEAK_0			Leakage current	EnGpio8DigIn=0,			-1		1	µA
				0 ≤ Vout ≤ 5V
ILEAK_1			Leakage current	EnGpio8DigIn=1,			-1		5	µA
				0 ≤ Vout ≤ 5V

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Electrical specifications											L6460
Table 5.			Electrical characteristics (continued)
Parameter				Description		Test condition		Min	Typ	Max	Unit
					ADChannelX[4:0]
		IAD		A/D path absorbed current	=10001 and			-1		1	µA
					bit EnDacScale=0
	t	DELAY		Delay from serial write to pin	C		=50 pF(45)			500	ns
				low
					LOAD
SPI interface (40)
		VIH		High level input voltage	(46)			1.6			V
		VIL		Low level input voltage	(46)					0.8	V
	VHYS			Input voltage hysteresis	(46)			0.15	0.22		V
		V		High level output voltage	I	= -10mA,(47)		2.75			V
		OH			OUT
		V		Low level output voltage	I	= 10mA,(47)				0.4	V
		OL			OUT
	tSCLK			SCLK period				62.5			ns
tSCLK_rise				SCLK rise time						2	ns
tSCLK_fall				SCLK fall time						2	ns
tSCLK_high				SCLK high time				20			ns
tSCLK_low				SCLK low time				20			ns
tnSS_setup				nSS setup time				10			ns
tnSS_hold				nSS hold time				10			ns
	tnSS_min			nSS high minimum time				30			ns
tMOSI_setup				MOSI setup time				10			ns
tMOSI_hold				MOSI hold time				10			ns
t	MISO_rise			MISO rise time	C		=50pF(48)			9	ns
					LOAD
t				MISO fall time	C		=50pF (48)			9	ns
	MISO_fall				LOAD
tMISO_valid				MISO valid from clock low				0		15	ns
tMISO_disable				MISO disable time				0		15	ns
	CLOAD			MOSI maximum load						200	pF

1.This value is useful to define the voltage rating for external capacitor to be connected from VSupply to VSupplyInt.

2.This typical value is only intended to give an estimation of the current consumption when L6460 is configured in simple regulators mode (see following Chapter 8.6.4) at the end of the start up sequence and with no load on regulators. This typical value allows a raw choose of the external resistor but the definitive choose must be done according to the recommendations on Chapter 4.1).

3.Measured between 10% and 90% of output voltage transition.

4.Measured from a fault detection to 50% of output voltage transition.

5.Current is defined to be positive when flowing into the pin.

6.Load regulation is calculated at a fixed junction temperature using short load pulses covering all the load current range. This is to avoid change on output voltage due to heating effect.

7.Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VLINmain_FB).

8.Default state.

9.The regulated voltage can be calculated using the formula: VSWmain_OUT = VFBREF *(Ra+Rb)/Rb.

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L6460	Electrical specifications

10.Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VSW_main_FB).

11.This condition is intended to simulate an extra current on output.

12.This condition is intended to simulate a short circuit on output.

13.Rise and fall time are measured between 10% and 90% VSWmain output voltage.

14.Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VSWDRV_FB).

15.The current protection values must be intended as a protection for the chip and not as a continuous current limitation. The

protection is performed by switching off the output bridge when current reaches values higher than the IOC max. No protection could be guaranteed for values in the middle range between IMAX and IOC

16.In this cell X stands for 1 or 2, Y stands for A or B

17.In this cell X stands for 3 or 4, Y stands for A or B

18.The current protection thresholds for Bridge 3 and 4 are not selectable so only the max current value (MtrXSideYILimSel[1:0]= 11) is available.

19.Overcurrent Off time can be configured using SPI.

20.Rise and fall time are measured between 10% and 90% of DC output voltage. With device in full bridge configuration (resistive load between outputs).

21.Default state for Aux1

22.Default state for Aux2

23.The regulated voltage can be calculated using the formula: VAUX_SW = VFBREF *(Ra+Rb)/Rb.

24.Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (GPIO1 and/or GPIO2)

25.Rise and fall time is measured between 10% and 90% of output voltage.

26.The external components connected to the pin must be chosen to avoid that the voltage exceeds this operative range.

27.The regulated voltage can be calculated using the formula: VAUX3_SW = VFBREF *(Ra+Rb)/Rb.

28.Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VREF_FB).

29.The definition of LSB for this table is LSB=IMRmax/(27.5-1).

30.Integral Non Linearity error (INL) is defined as the maximum distance between any point of the ADC characteristic and the “best straight line” approximating the ADC transfer curve.

31.The ADC ensures monotonic characteristic and no missing codes.

32.Differential nonlinearity error (DNL) is defined as the difference between an actual step width and the ideal width value of 1 LSB.

33.Offset error (OE) is the deviation of the first code transition (000...000 to 000...001) from the ideal (i.e. GND + 0.5 LSB).

34.Gain error (GE) is the deviation of the last code transition (111...110 to 111...111) from the ideal (V3v3 - 0.5 LSB), after adjusting for offset error.

35.Please note that the result of the conversion will always be a 9-bit word: to speed up the conversion, the resolution is reduced when the ADC is used in the 8- bit resolution mode.

36.Actual input capacitance depends on the pin that must be converted.

37.The definition of LSB for this table is LSB=IMRmax/(29-1).

38.All parameters are guaranteed in the range between VOL and VR Max.

39.Measured from DacValue[5:0] change in SPI interface.

40.VGPIO_SPI = 3.3 V unless otherwise specified

41.In this section reports the operational amplifier parameters that change when used as comparator.

42.Vi is the differential voltage applied to input pins across the common voltage VCM.

43.Measured between 50% of input and output signal.

44.Time measured from change in SPI interface to 50% of external pin transition.

45.Measured between nSS rising edge and 50% of Vout.

46.Specification applies to nSS, SCLK and MOSI pins.

47.Current is considered to be positive when flowing towards the IC

48.These times are measured at the pin output between specified VOH and VOL.

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Internal supplies	L6460

4 Internal supplies

L6460 includes three internal regulators used to provide a regulated voltage to internal circuits.

The internal regulators are the following:

-VSupplyInt regulator.

-Charge pump regulator.

-V3v3 regulator.

4.1VSupplyInt regulator

VSupplyInt is the output of an internal regulator used to supply some internal circuits. This regulator is not intended to provide external current so it must not be used to supply external

loads. An external capacitor must always be connected to this pin (preferably towards VSupply pin), recommended value is in the range 80 ÷ 120 nF.

Figure 3. VSupplyInt pin

Vsupply

VsupplyInt

IS_Int_TYP

L6460 internal circuits

L6460

GND

The VSupplyInt pin may also be externally connected to VSupply pin by means of an external resistor REXT: this allows REXT, particularly when VSupply is at the max values of the operative supply range, to dissipate power that otherwise would be dissipated inside the

chip. The choice of the optimal resistor depends on the application since it is strictly

depending on both VSupply and the current used inside the chip (that is changing with the chosen configuration).

REXT could be chosen by applying this formula: REXT = (VSupply min - VS_Int max)/(IS_Int max).

IS_Int max is depending from the chosen configuration and represents the total current needed by the circuits connected to this pin.

For example, with VSupply = 32 V and IS_Int = 12 mA a typical resistor value is 1 kΩ.

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