ST L6460 User Manual

SPI configurable stepper and DC multi motor driver

Features

■ Operating supply voltage from 13 V to 38 V

■ 4 full bridge driver configurable in multi-motor

application to drive: – 2 DC and 1 stepper motor –4 DC motor

■ Bridge 1 and 2 (R

configured to work as: – Dual full bridge driver – Super DC driver – 2 half bridge driver – 1 super half bridge –2 power switches – 1 super power switch

■ Bridge 3 and 4 (R

configured to work as: – Same as bridges 1 and 2, listed above – Stepper motor driver: up to 1/16

microstepping – 2 buck regulators (bridge 3) – 1 super buck regulator – Battery charger (bridge 4)

■ Power supply management

– One switching buck regulator – One switching regulator controller – One linear regulator – One battery charger

■ Fully protected through

– Thermal warning and shutdown – Overcurrent protection – Undervoltage lock-out

■ SPI interface

■ Programmable watchdog function

■ Integrated power sequencing and supervisory

functions with fault signaling through serial interface and external reset pin

■ Very low power dissipation in shut-down mode

(~35 mW)

= 0.60 Ω) can be

DSon

= 0.85 Ω) can be

DSon

L6460

TQFP64 exposed pad

■ Auxiliary features

– Multi-channels 9 bit ADC

– 2 operational amplifiers

– Digital comparator – 2 low voltage power switches – 3 general purpose PWM generators –14 GPIOs

Description

The L6460 is optimized to control and drive multimotor system providing a unique level of integration in term of control, power and auxiliary features. Thanks to the high configurability L6460 can be customized to drive different motor architectures and to optimize the number of embedded features, such as the voltage regulators, the high precision A/D converter, the operational amplifier and the voltage comparators. The possibility to drive simultaneously stepper and DC motor makes L6460 the ideal solution for all the application featuring multi motors.

Table 1. Device summary

Order code Package Packing

L6460

TQFP64

L6460TR Tape and reel

Tr ay

July 2010 Doc ID 17713 Rev 1 1/139

www.st.com

139

Contents L6460

Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.3 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2 L6460’s main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2 Operating ratings specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4 Internal supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.1 V

SupplyInt

regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.2 Charge pump regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.3 V3v3 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5 Supervisory system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.1 Power on reset (POR) circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.2 nRESET generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.3 Thermal shut down generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6 Watchdog circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7 Internal clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8 Start-up configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.1 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.2 Basic device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.3 Slave device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.4 Master device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.5 Single device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.6 Sub-configurations for slave, master or single device modes . . . . . . . . . 41

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8.6.1 Bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.6.2 Primary regulator mode (KP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.6.3 Regulators mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.6.4 Simple regulator mode (KT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.6.5 Bridge + V

mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

EXT

8.6.6 Secondary regulators mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9 Power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

10 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10.1 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10.2 Hibernate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10.3 Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10.4 nAWAKE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

11 Linear main regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

12 Main switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

12.1 Pulse skipping operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

13 Switching regulator controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

13.1 Pulse skipping operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

13.2 Output equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

13.3 Switching regulator controller application considerations . . . . . . . . . . . . . 54

14 Power bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

14.1 Possible configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

14.1.1 Full bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

14.1.2 Parallel configuration (super bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

14.1.3 Half bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

14.1.4 Switch configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

14.1.5 Bipolar stepper configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

14.1.6 Synchronous buck regulator configuration (Bridge 3) . . . . . . . . . . . . . . 73

14.1.7 Regulation loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

14.1.8 Battery charger or switching regulator (Bridge 4) . . . . . . . . . . . . . . . . . 76

15 AD converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

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Contents L6460

15.1 Voltage divider specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

16 Current DAC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

17 Operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

18 Low voltage power switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

19 General purpose PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

19.1 General purpose PWM generators 1 and 2 (AuxPwm1 and AuxPwm2) . 90

19.2 Programmable PWM generator (GpPwm) . . . . . . . . . . . . . . . . . . . . . . . . 90

20 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

21 Digital comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

22 GPIO pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

22.1 GPIO[0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

22.2 GPIO[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

22.3 GPIO[2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

22.4 GPIO[3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

22.5 GPIO[4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

22.6 GPIO[5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

22.7 GPIO[6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

22.8 GPIO[7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

22.9 GPIO[8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

22.10 GPIO[9] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

22.11 GPIO[10] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

22.12 GPIO[11] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

22.13 GPIO[12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

22.14 GPIO[13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

22.15 GPIO[14] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

23 Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

23.1 Read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

23.2 Write transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

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24 Registers list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

25 Schematic examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

26 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Doc ID 17713 Rev 1 5/139

List of tables L6460

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. IC operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 6. Stretch time selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 7. Watchdog timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 8. Possible start-up pins state symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 9. Start-up correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 10. Main switching regulator PWM specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 11. Main switching regulator current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 12. Switching regulator controller PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 13. Switching regulator controller application: feedback reference. . . . . . . . . . . . . . . . . . . . . . 54

Table 14. PWM selection truth table for bridge 1 or 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 15. PWM selection truth table for bridge 3 or 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 16. Bridge selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 17. Bridge 3 and 4 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 18. Full bridge truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 19. Half bridge truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 20. Switch truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 21. Sequencer driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 22. Stepper driving mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 23. Stepper sequencer direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 24. DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 25. Internal sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 26. Stepper off time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 27. Stepper fast decay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 28. PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 29. Battery charger regulator controller PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 30. ADC truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 31. Channel addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 32. ADC sample times when working as a 8-bit ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 33. ADC sample time when working as a 9-bit ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 34. Voltage divider specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 35. Current DAC truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 36. Interrupt controller event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 37. Comparison type truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 38. DataX selection truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 39. GPIO functions description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 40. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 41. GPIO[0] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 42. GPIO[1] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 43. GPIO[2] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 44. GPIO[3] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 45. GPIO[4] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 46. GPIO[5] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 47. GPIO[6] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 48. GPIO[7] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 49. GPIO[8] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

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Table 50. GPIO[9] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 51. GPIO[10] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 52. GPIO[11] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 53. GPIO[12] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 54. GPIO[13] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 55. GPIO[14] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 56. Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 57. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Doc ID 17713 Rev 1 7/139

List of figures L6460

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 3. V

SupplyInt

Figure 4. Charge pump block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 5. nReset generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 6. Watchdog circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 7. Standby mode function description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 8. nAWAKE function block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 9. Linear main regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 10. Linear main regulator with external bipolar for high current . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 11. Main switching regulator functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 12. Switching regulator controller functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 13. Switching regulator controller output driving: equivalent circuit . . . . . . . . . . . . . . . . . . . . . 54

Figure 14. H Bridge block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 15. Bridge 1 and 2 PWM selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 16. Super bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 17. Half bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 18. Bipolar stepper configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 19. Regulator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 20. Internal comparator functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 21. Battery charger control loop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 22. Li-ion battery charge profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 23. Simple buck regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 24. A2D block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 25. Current DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 26. Configurable 3.3 V operational amplifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 27. Low power switch block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 28. Interrupt controller diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 29. Digital comparator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 30. GPIO[0] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 31. GPIO[1] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 32. GPIO[2] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 33. GPIO[3] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 34. GPIO[4] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 35. GPIO[5] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 36. GPIO[6] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 37. GPIO[7] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 38. GPIO[8] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 39. GPIO[9] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 40. GPIO[10] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 41. GPIO[11] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 42. GPIO[12] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8/139 Doc ID 17713 Rev 1

L6460 List of figures

Figure 43. GPIO[13] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 44. GPIO[14] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 45. SPI read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 46. SPI write transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 47. SPI input timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 48. SPI output timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 49. Application with 2 DC motors, 1 stepper motor and 3 power supplies . . . . . . . . . . . . . . . 135

Figure 50. Application with 2 DC motors, a battery charger and 5 power supplies . . . . . . . . . . . . . . 136

Figure 51. TQFP64 mechanical data an package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Doc ID 17713 Rev 1 9/139

General description L6460

1 General description

1.1 Overview

L6460 offers the possibility to control and power multi motor systems, through the management of simultaneous driving of stepper and DC motor. A number of features can be configured through the digital interface (SPI), including 3 voltage regulators, 1 high precision A/D converter, 2 operational amplifiers and 14 configurable GPIOs.

The high flexibility allows the possibility to configure two, one full or half bridge to work as power stage featuring additional voltage buck regulators.

Figure 1. Block diagram

N2%3%4

N33

3#,+

-)3/

-/3)

N!7!+%

66

6'0)/?30)

4HERMAL

-ANAGER

3UPERVISORY

2ESET

-ANAGER

2EGISTERS

30)

)NTERNAL

2EGULATOR

'0)/

/P!MP

'0)/

'0)/

X

3TEPPER-OTOR

-ANAGER

$#$#

-AIN 3WITCHING 2EGULATOR

'0)/

'0)/

'0)/

#URRENT

$!#

)NT6OLTAGE2EFERENCE

63UPPLY

'0)/

'0)/

'0)/

'0)/S

#ONTROL

,OGIC

60UMP60UMP

-AIN

,INEAR

2EGULATOR

'0)/

'0)/

'0)/

'0)/

07-

'ENERATORS

63UPPLY 63UPPLY

!$#-58

3WITCH

"ATTERY

#HARGER

-ANAGER

3WITCHING 2EGULATOR #ONTROLLER

'0)/

X

'0)/

63UPPLY)NT

$IGITAL

#OMP

#0(

#HARGE

(3 $#X?-).53

,3 $#X?-).53

(3 $#X?0,53

,3 $#X?0,53

2EGOLATION

,OOP

$#

PUMP

#0,

60UMP

63UPPLY

60UMP

$#?-).53

$#?0,53

'.$

60UMP

$#?-).53

$#?0,53

'.$

60UMP

$#?-).53

$#?0,53

$#?3%.3%

60UMP

$#?-).53

$#?0,53

$#?3%.3%

%?0!$

)2%&?&"

62%&?&"

637MAIN?&"

637MAIN?37

Note: See following Chapter 2 for a detailed description of possible configurations.

6,).MAIN?/54

6,).MAIN?&"

637$26?3.3

637$26?&"

637$26?37

637$26?'!4%

10/139 Doc ID 17713 Rev 1

L6460 General description

1.2 Pin connection

Figure 2. Pin connection

VSupply

DC1_PLUS

64 63 62 61 60 59 58 57

DC1_PLUS

SWDRV_SNS

VSWDRV_FB

DC1_MINUS

DC2_MINUS

DC2_PLUS

GND_PAD

GPIO4

GPIO3

GND1

GND2 DC4_SENSE

9 40

GPIO2

GPIO1

GPIO0

nSS

17 18 19 20 21 22 23 24

Supply

MISO

DC2_PLUS

CPL

CPH

MOSI

VPump

VLINmain_FB

VSWDRV_GATE

GPIO8

LINmain_OUT

VSWDRV_SW

GPIO6

56 55 54 53 52 51 50 49

25 26 27 28 29 30 31 32

Supply

SWmain_SW

VGPIO_SPI

GPIO7

SWmain_FB

VSupplyInt

REF_FB

V3V3

IREF_FB

nRESET

SCLK

VSupply

Supply

DC3_PLUS

N.C.

DC4_PLUS

DC3_SENSE

GPIO5

GPIO9

GPIO10

GPIO11

N.C.

DC3_MINUS

DC3_SENSE

DC4_MINUS

N.C.

GPIO14

GPIO13

GPIO12

nAWAKE

DC4_SENSE

Doc ID 17713 Rev 1 11/139

General description L6460

1.3 Pin list

Table 2. Pins configuration

Pin # Pin name Description Type

1 DC1_PLUS Bridge 1 phase “plus” output Output

SWDRV_SNS

SWDRV_FB

4 GPIO4 General purpose I/O Analog In/Out - CMOS bi-dir

5 GPIO3 General purpose I/O Analog In/Out - CMOS bi-dir

6 DC1_MINUS Bridge 1 phase “minus” output Output

7 DC1_MINUS Bridge 1 phase “minus” output Output

8 GND1 Ground pin for bridge1

9 GND2 Ground pin for bridge2

10 DC2_MINUS Bridge 2 phase “minus” output Output

11 DC2_MINUS Bridge 2 phase “minus” output Output

12 GPIO2 General purpose I/O Analog In/Out - CMOS bi-dir

13 GPIO1 General purpose I/O Analog In/Out - CMOS bi-dir

Switching regulator controller sense Analog input

Switching regulator controller feedback Analog input

(1)(2)(3)

Power/digital

14 GPIO0 General purpose I/O Analog Input - CMOS input

15 nSS SPI chip select pin CMOS input

16 DC2_PLUS Bridge 2 phase “plus” output Output

17 DC2_PLUS Bridge 2 phase “plus” output Output

18 V

Supply

Main voltage supply Power input

19 MISO SPI serial data output CMOS output

20 MOSI SPI serial data input CMOS input

21 V

22 V

LINmain_FB

LINmain_OUT

Linear main regulator feedback Analog input

Linear main regulator output Power output

23 GPIO 8 General purpose I/O Analog In/Out - CMOS bi-dir

24 V

SWmain_SW

25 V

26 V

SWmain_FB

27 V

28 I

Supply

REF_FB

Main switching regulator switching output Power output

Main voltage supply Power Input

Main switching regulator feedback pin Analog input

Regulator voltage feedback Analog input

Regulator current feedback Analog input

29 SCLK SPI input clock pin CMOS input

30 V

31 DC4_PLUS Bridge 4 phase “plus” output Output

Supply

Main voltage supply Power input

32 N.C. Not connected

33 DC4_SENSE Bridge 4 sense output

(4)

34 nAWAKE Device wake up CMOS input

12/139 Doc ID 17713 Rev 1

Output

L6460 General description

Table 2. Pins configuration (continued)

Pin # Pin name Description Type

35 GPIO12 General purpose I/O Analog In/Out - CMOS bi-dir

36 GPIO13 General purpose I/O Analog In/Out - CMOS bi-dir

37 GPIO14 General purpose I/O Analog In/Out - CMOS bi-dir

38 N.C. Not connected

39 DC4_MINUS Bridge 4 phase “minus” output Output

40 DC4_SENSE Bridge 4 sense output

41 DC3_SENSE Bridge 3 sense output

(4)

42 DC3_MINUS Bridge 3 phase “minus” output Output

43 N.C. Not connected

44 GPIO11 General purpose I/O Analog In/Out - CMOS bi-dir

45 GPIO10 General purpose I/O Analog In/Out - CMOS bi-dir

46 GPIO9 General purpose I/O Analog In/Out - CMOS bi-dir

47 GPIO5 General purpose I/O Analog In/Out - CMOS bi-dir

(4)

48 DC3_SENSE Bridge 3 sense output

Output

49 N.C. Not connected

Output

50 DC3_PLUS Bridge 3 phase “plus” output Output

51 V

Supply

Main voltage supply Power input

52 nRESET Open drain system reset pin CMOS Input/output

53 V

54 V

SupplyInt

3v3

Internal 3.3 volt regulator Power Input/output

Internal voltage supply Power Input

55 GPIO7 General purpose I/O Analog In/Out - CMOS bi-dir

56 V

GPIO_SPI

Low voltage pins power supply Power input

57 GPIO6 General purpose I/O Analog In/Out - CMOS bi-dir

58 V

59 V

SWDRV_SW

SWDRV_GATE

60 V

Pump

Switching regulator controller source input Power input

Switching driver gate drive pin Analog output

Charge pump voltage Power Input/output

61 CPH Charge pump high switch pin Power Input/output

62 CPL Charge pump low switch pin Power Input/output

63 V

Supply

Main voltage supply Power input

64 DC1_plus Bridge 1 phase “plus” output Output

E_Pad GND_PAD

1. These pins must be connected all together to a unique PCB ground.

2. Bridges1 and 2 have 2 ground pads: one is bonded to the relative ground pin (GND1 or GND2) and the other is connected to exposed pad (E_Pad) ground ring. This makes the bond wires testing possible by forcing a current between E-Pad and GND1 or GND2 pins and using the other pin as sense pin to measure the resistance of E-Pad bonding. (N.B: grounds of two bridges are internally connected together).

3. The analog ground is connected to exposed pad E-Pad.

4. The pin must be tied to ground if bridge is not used as a stepper motor.

(1)(2)(3)

Doc ID 17713 Rev 1 13/139

L6460’s main features L6460

2 L6460’s main features

L6460 includes the following circuits:

● Four widely configurable full bridges:

– Bridges 1 and 2:

– Diagonal R – Max operative current = 2.5 A.

– Bridges 3 and 4:

– Diagonal R – Max operative current = 1.5 A.

● Possible configurations for each bridge are the following:

– Bridge 1:

– DC motor driver. – Super DC (bridge 1 and 2 paralleled form superbridge1). – 2 independent half bridges. – 1 super half bridge (bridge 1 side A and bridge 1 side B paralleled form

superhalfbridge1). – 2 independent switches (high or low side). – 1 super switch (high or low side).

– Bridge 2 has the same configurations of bridge 1. – Bridge 3 has the same configurations of bridge 1 (bridge 3 and 4 paralleled form

superbridge2) plus the following: – ½ stepper motor driver. – 2 buck regulators (V – 1 Super buck regulator (V

– Bridge 4 has the same configurations of bridge 1 plus the following:

– ½ stepper motor driver. – 1 super buck regulator (V – Battery charger.

● One buck type switching regulator (V

– Output regulated voltage range: 1-5 Volts. – Output load current: 3.0 A. – Internal output power DMOS. – Internal soft start sequence. – Internal PWM generation. – Switching frequency: ~250 kHz. – Pulse skipping strategy control.

● One switching regulator controller (V

– Output regulated voltage range: 1-30 Volts. – Selectable current limitation. – Internal PWM generation. – Pulse skipping strategy control.

● One linear regulator (V

14/139 Doc ID 17713 Rev 1

: 0.6 Ω typ.

DSon

: 0.85 Ω typ.

DSon

LINmain

AUX1_SW

AUX1//2_SW

AUX3_SW

, V

AUX2_SW

SWmain

SWDRV

) with:

) that can be used to generate low current/low ripple

L6460 L6460’s main features

voltages. This regulator can be used to drive an external bipolar pass transistor to generate high current/low ripple output voltages.

● One bidirectional serial interface with address detection so that different ICs can share

the same data bus.

● Integrated power sequencing and supervisory functions with fault signaling through

serial interface and external reset pin.

● Fourteen general purpose I/Os that can be used to drive/read internal/external

analog/logic signals.

● One 8-bit/9-bit A/D converter (100 kS/s @ 9-bit, 200 kS/s @8-bit). It can be used to

measure most of the internal signals, of the input pins and a voltage proportional to IC temperature.

– Current sink DAC: – Three output current ranges: up to 0.64/6.4/64 mA. – 64 (6-bit programmable) available current levels for each range. – 5 V output tolerant.

● Two operational amplifiers:

– 3.3 V supply, rail to rail input compatibility, internally compensated. – They can have all pins externally accessible or can be internally configured as a

buffer o make internal reference voltages available outside of the chip.

– Unity gain bandwidth > 1 MHz. – They can also be set as comparators with 3.3 V input compatibility and low offset.

● Two 3.3 V pass switches with 1 Ω R

● Programmable watchdog function.

● Thermal shutdown protection with thermal warning capability.

● Very low power dissipation in “low power mode” (~35 mW)

and short circuit protected.

DSon

L6460 is intended to maximize the use of its components, so when an internal circuit is not used it could be employed for other applications. Bridge 3, for example, can be used as a full bridge or to implement two switching regulators with synchronous rectification: to obtain this flexibility L6460 includes 2 separate regulation loops for these regulators; when the bridge is used as a motor driver, the 2 regulation loops can be redirected on general purpose I/Os to leave the possibility to assembly a switching regulator by only adding an external FET.

Doc ID 17713 Rev 1 15/139

Electrical specifications L6460

3 Electrical specifications

3.1 Absolute maximum rating

The following specifications define the maximum range of voltages or currents for L6460.

Stresses above these absolute maximum specifications may cause permanent damage to the device. Exposure to absolute maximum ratings for extended periods may affect device reliability.

Table 3. Absolute maximum ratings

Parameter Description

Supply

GPIO_SPI

3V3pin

SW_pulse

Pump

1. This value is useful to define the voltage rating for external capacitor to be connected from V V

. V

Supply

to provide voltage to external loads.

2. TSD is the thermal shut down temperature of the device.

is internally generated and can never be supplied by external voltage source nor is intended

Pump

voltage 40 V

Supply

GPIO_SPI

3V3

voltage 3.9 V

voltage -0.3 3.9 V

Switching regulators output pin voltage range

Switching regulators min pulsed voltage

Charge pump voltage

Junction temperature

3.2 Operating ratings specifications

Table 4. IC operating ratings

Parameter Description

Supply

Shut_down

GPIO_SPI

VGPIO_SPI

3v3

LINmain_OUT

LINmain_FB

SWmain_SW

SWDRV_SWVSWDRV_SW

voltage range 13

Supply

operative current

Supply

shut down state current 1.5 mA

Supply

GPIO_SPI

voltage range 2.4 3.6 V

operative current

3.3V input pin voltage range 3.6 V

Output pin voltage range

Feedback pin voltage range 0 3.6 V

Output pin voltage range

pin voltage range

(2)

Test

condition

tpulse < 500ns

(1)

Min Max Unit

-1 V

Supply

-3 V

15 V

Storage -40 190 °C

Operating -40 TSD °C

Pump

Tes t

condition

(2)

(3)

(4)

-1 V

Min Max Unit

(1)

38 V

15 mA

0.4 mA

Supply

-1 V

supply

Supply

16/139 Doc ID 17713 Rev 1

L6460 Electrical specifications

Table 4. IC operating ratings

Parameter Description

Tes t

condition

Min Max Unit

SWDRV_GATE

SWDRV_SNS

1. For V

2. Operating supply current is measured with system regulators operating but not loaded.

3. Operating V

4. The external components connected to the pin must be chosen to avoid that the voltage exceeds this

supply

For V

supply

amplifiers and pass switches) enabled but not loaded.

operative range.

Gate drive pin voltage 0 V

Sense pin voltage

Supply

-3V

Junction temperature Operating -40 125 °C

lower than 21 V an external resistor between V lower than 15 V external diodes for charge pump are required.

current is measured with all circuits supplied by V

GPIO_SPI

supply

and V

supply Int

GPIO_SPI

pins are required.

(GPIO’s, operational

Pump

Supply

3.3 Electrical characteristics

Table 5. Electrical characteristics

Parameter Description Test condition Min Typ Max Unit

SupplyInt

Charge pump V

S_Int

Pump

S_Int

Pump

regulator

Pump

SupplyInt

output voltage

operative current

Charge pump voltage V

clock frequency F

Pump

(1)

(2)

Supply

= 16MHz typ

OSC

=32V

18 19.5 21 V

11 mA

Supply

+12.5

OSC

Supply

+ 14.5

+ 10.5

kHz

V3V3 regulator

Power on reset

nRESET circuit

3V3

Supply_POR_validVSupply

Supply_POR_fallVSupply

Supply_POR_filtVSupply

3V3_POR_fallV3v3

3V3_POR_riseV3v3

3V3_POR_hysV3v3

3V3_POR_filt

nRST_L

output voltage V

3v3

POR falling threshold V

POR rising threshold V

POR hysteresis 0.5 V

POR filter time 1.5 µs

3v3

nRESET low level output voltage

=32V 3.15 3.3 3.45 V

Supply

voltage for POR valid I

POR falling threshold V

= 1mA 4 V

nRESET

falling 6 8 V

Supply

POR filter Time 3 µs

falling 1.9 2.2 V

3V3

rising 2.7 V

3V3

I=10mA 0.4 V

Doc ID 17713 Rev 1 17/139

Electrical specifications L6460

Table 5. Electrical characteristics (continued)

Parameter Description Test condition Min Typ Max Unit

nRST_fall

nRST_del

Supply_UV_f

Supply_UV_r

Supply_UV_hysVSupply

Supply_UV

S_Int_UV_f

S_Int_UV_r

S_Int_UV_hysVSupplyInt

S_Int_UV

Pump_UV_f

Pump_UV_r

Pump_UV_hysVPump

Pump_UV

GPIO_SPI_UV_fVGPIO_SPI

GPIO_SPI_UV_rVGPIO_SPI

GPIO_SPI_hysVGPIO_SPI

GPIO_SPI_UV

nRESET fall time

nRESET delay time

Supply

SupplyInt

Pump

GPIO_SPI

TSD circuit

I=1mA C=50pF

(4)

(3)

15 ns

150 ns

falling threshold 10.2 11 11.8 V

rising threshold 10.5 11.5 12.5 V

hysteresis 0.3 0.5 0.7 V

UV filter time 3.5 µs

falling threshold 9.7 10.7 11.7 V

rising threshold 10.6 11.4 12.2 V

hysteresis 0.4 0.7 1 V

UV filter time 3.5 µs

falling threshold

rising threshold

Supply

+ 7.5

Supply

+ 7.5

Supply

+ 8

Supply

+ 8

Supply

+ 8.5

hysteresis 0.3 0.5 0.7 V

UV filter time 3.5 µs

falling threshold 1.8 2 V

rising threshold 2.2 2.4 V

hysteresis 200 250 300 mV

UV filter time 3.5 µs

TSD

WARM

DIFF

TSD_FILT

WARM_F ILT

Thermal shut down temperature

Warming temperature 140 °C

Thermal shut down to warming difference

Thermal shut down filter time 8 µs

Warming filter time 8 µs

Watchdog

WD_T

clk

Watchdog clock period

Internal clock

osc

Oscillator frequency V

3V3

nAWAKE function

nAWAKE low logic level voltage

18/139 Doc ID 17713 Rev 1

170 °C

30 °C

osc

= 3.3 V 14.1 16 17.6 MHz

0.8 V

L6460 Electrical specifications

Table 5. Electrical characteristics (continued)

Parameter Description Test condition Min Typ Max Unit

HYS

OUT

INP

AWAKEFILT

nAWAKE high logic level voltage

nAWAKE input hysteresis 0.25 V

nAWAKE pin output current nAWAKE=0V

nAWAKE pin input current nAWAKE=0.8V

Filter time 1.2 μs

Main linear regulator

drop

LINmain_Ref

outLINMax

short

ΔV

out/Vo

/ΔV

ΔV

out

loop_acc

LIN_UV_f

LIN_UV_r

LIN_UV_hys

prim_uv

Supply

Drop out voltage

Internal switch pull down current

Feedback reference voltage 0.776 0.8 0.824 V

Feedback pin input current -2 2 µA

Maximum output current V

Output short circuit current

Load regulation 0 ≤ I

Line regulation I

Loop voltage accuracy ±2.5 %

Undervoltage falling threshold

Undervoltage rising threshold

Undervoltage hysteresis 6 %

Under voltage deglitch filter 5 µs

Main switching regulator

(5)

drop

supply-VLINmain_OUT

Linear Main Regulator disabled; V

LINmain_OUT

LINmain_FB

load

(7)

≤ I

load

=10mA

LINmain_OUT

= V

supply

=0V,

=0V

outLINMax

(6)

1.6 V

-0.72 -2 mA

0.2 0.4 mA

=1V

3mA

-2V 10 mA

12 24 32 mA

0.8 %

0.2 %

84.5 87 89.5 %

90.5 93 95.5 %

SelFBref = ‘00’ 0.776 0.8 0.824 V

(8)

0.97 1 1.03 V

FBREF

Main switching regulator feedback reference voltage

SelFBref = ‘01’

SelFBref = ‘10’ 2.425 2.5 2.575 V

SelFBref = ‘11’ 2.91 3 3.09 V

Q_LP

SWmain_FB

SWmain_OUT

load

DSonHS

Output leakage current T

Output leakage current in “low power mode”

SWmain_FB

pin current T

Output voltage range

Maximum output load current V

Internal high side R

DSon

= 125°C -40 +40 µA

junction

= 36V

Supply

= 125°C

junction

= 125°C -10 +10 µA

junction

(9)

= 36V 0.002 3 A

Supply

=1A

load

= 125°C

junction

-15 +15 µA

0.8 5 V

0.33 0.95 Ω

Doc ID 17713 Rev 1 19/139

Electrical specifications L6460

Table 5. Electrical characteristics (continued)

Parameter Description Test condition Min Typ Max Unit

loop

SW_UV_f

SW_UV_r

SW_UV_hys

prim_uv

limit

deglitch

I_lim

I_limUV

SW_PWM

Loop voltage accuracy ±3%

Under voltage falling threshold

Under voltage rising threshold

Under voltage hysteresis 6 %

Under voltage deglitch filter 5 µs

Current limit protection

Current limit deglitch time 50 ns

Current limit response time

Current limit response time in UV condition

Switching output rise time

Switching output fall time

Operating frequency

Switching regulator controller

(10)

SelIlimit =”0” SelIlimit =”1”

Normal operating mode (no

(11)

UV)

UV condition

= 36V,

Supply

= 422 Ω

LOAD

= 36V,

Supply

= 10 Ω

LOAD

(12)

200 400 ns

(13)

84.5 87 89.5 %

90.5 93 95.5 %

3.3

2.3

3.5

A A

450 650 ns

530ns

Fosc/6

kHz

GS_ext

SOURCE

SINK

SUSTAIN

Q_LP

FBREF

SWDRV_FB

loop

Gate to source voltage for external FET

Source current

Sink current V

Pump=VSupply

SWCTR_GATE

+12V

=0V

= V

Supply

Pump

25 50 mA

20 mA

Sink discharge pulse time 600 ns

Gate-source sustain resistance

Output leakage current

Output leakage current in “Low Power Mode”

Switching regulator feedback

SWCTR_GATE

SWCTR_SRC

= 36V,

Supply

junction

= 36V,

Supply

junction

SelFBref = ‘00’

) = 0.2V

= 125°C

(8)

650 Ω

-40 +40 µA

-5 +5 µA

0.776 0.8 0.824 V

SelFBref = ‘01’ 0.97 1 1.03 V

controller feedback reference voltage

SelFBref = ‘10’ 2.425 2.5 2.575 V

SelFBref = ‘11’ 2.91 3 3.09 V

SWDRV_FB

pin current

Supply

junction

= 125°C

-10 +10 µA

= 36V,

Loop voltage accuracy ±3%

20/139 Doc ID 17713 Rev 1

L6460 Electrical specifications

Table 5. Electrical characteristics (continued)

Parameter Description Test condition Min Typ Max Unit

SWD_UV_f

SWD_UV_r

SWD_UV_hys

prim_uv

ovc

deglitch

I_lim

I_limUV

Under voltage falling threshold

Under voltage rising threshold

Under voltage hysteresis 6 %

Under voltage deglitch filter 5 µs

Over current threshold voltage 250 300 350 mV

Current limit deglitch time 50 ns

Current limit response time

Current Limit response time in UV condition.

(14)

Normal operating mode (no

(11)

UV)

UV condition

(12)

84.5 87 89.5 %

90.5 93 95.5 %

500 900 ns

380 550 ns

SWD_PWM

Power bridges

DSon1_2

DSon3_4

MAX1_2

MAX3_4

dss

Q_LP

OC_LS1_2

OC_HS1_2

Operating frequency F

Bridge 1 and 2 diagonal R

Bridge 3 and 4 diagonal R

DSon

I = 1.4A, V

= 125°C

junction

I = 1A, V

= 125°C

junction

Supply

= 36V,

Bridge 1 and 2 operative rms current

Bridge 3 and 4 operative rms current

Output leakage current. T

Output leakage current in “low power mode”

Low side current protection for bridges 1 and 2

High side current protection for bridges 1 and 2

(15)

= 125°C -50 +50 µA

junction

= 36V,

Supply

= 125°C

junction

MtrXSideYILimSel[1:0]=00 MtrXSideYILimSel[1:0]=01 MtrXSideYILimSel[1:0]=10 MtrXSideYILimSel[1:0]=11

(16)

MtrXSideYILimSel[1:0]=00 MtrXSideYILimSel[1:0]=01 MtrXSideYILimSel[1:0]=10 MtrXSideYILimSel[1:0]=11

-10 +10 µA

0.6

1.4

2.4

0.7

1.5

2.5

/64 kHz

osc

0.6 1.1

0.85 1.65

2.5 A

1.5 A

1 2 3 3

1.6

2.6

3.6

1.7

2.7

3.7

OC_LS3_4

OC_HS3_4

filter

Low side current protection for bridges 3 and 4

High side current protection for bridges 3 and 4

(15)

Current limit filter time

MtrXSideYILimSel[1:0]=11

(17)(18)

MtrXSideYILimSel[1:0]=11

7)(18)

1.55 2.5 A

1.6 2.5 A

25μs

Doc ID 17713 Rev 1 21/139

Electrical specifications L6460

Table 5. Electrical characteristics (continued)

Parameter Description Test condition Min Typ Max Unit

delay

OC_off

r1_2

r3_4

f1_2

f3_4

deadRise

deadFall

PWM

Current limit delay time

Over current Off time

Output rise time bridges 1 and 2

Output rise time bridges 3 and 4

Output fall time bridges 1 and 2

Output fall time bridges 3 and 4

MtrXIlimitOffTimeY[1:0]=00 MtrXIlimitOffTimeY[1:0]=01 MtrXIlimitOffTimeY[1:0]=10 MtrXIlimitOffTimeY[1:0]=11

(19)

= 36V, resistive load

Supply

between outputs: R= 25 Ω

V between outputs: R= 36 Ω

(20)

= 36V, resistive load

Supply

(20)

= 36V, resistive load

Supply

between outputs: R= 25 Ω

(20)

= 36V, resistive load

Supply

between outputs: R= 36 Ω

(20)

100 180 250 ns

50 100 200 ns

100 180 250 ns

50 125 250 ns

5 μs

60 120 240 480

µs µs µs µs

Anti crossover rising dead time 100 300 450 ns

Anti crossover falling dead time

Operating frequency

100 300 450 ns

/51

osc

kHz

resp

Delay from PWM to output transition

Bipolar stepper circuitry

STEPREF

offset

Reference voltage

Sense comparator offset -12 12 mV

SelStepRef =0 SelStepRef =1

StepBlkTime = ‘00’

StepBlkTime = ‘01’ 1 1.45 1.9 µs

blk

Blanking time

StepBlkTime = ‘10’ 1.5 2.25 3 µs

StepBlkTime = ‘11’ 3 4.25 5.5 µs

Synchronous buck regulator (bridge 3)

AUX_SW

QLP

Output pin voltage range (DC3x)

Output leakage current T

Output leakage current in “Low Power Mode”

(26)

junction

Supply

junction

22/139 Doc ID 17713 Rev 1

500 ns

(8)

0.48

0.72

0.65 0.95 1.25 µs

-1 V

0.50

0.75

0.52

0.78

Supply

= 125°C -50 +50 µA

= 36V

= 125°C

-10 +10 µA

L6460 Electrical specifications

Table 5. Electrical characteristics (continued)

Parameter Description Test condition Min Typ Max Unit

SelFBRef = ‘00’ 0.776 0.8 0.824 V

(21)

(22)

0.97 1 1.03 V

2.425 2.5 2.575 V

-15 15 µA

(23)

0.8 30 V

=1A 0.6 0.8 Ω

load

84.5 87 89.5 %

90.5 93 95.5 %

480 700 ns

FBREF

GPIO_FB

out

load

DSonHS

loop

REG_UV_f

REG_UV_r

REG_UV_hys

aux_UV

limit

deglitch

I_lim

Synchronous buck regulator feedback reference voltage

SelFBRef = ‘01’

SelFBRef = ‘10’

SelFBRef = ‘11’ 2.91 3 3.09 V

= 125°C

GPIO feedback pin current

Output voltage range V

Output load current V

Internal high/low side R

DSon

junction

0V≤Feedback ≤ 3V

= 36V

Supply

= 36V 0.002 1.5 A

Supply

= 125°C; I

junction

Loop voltage accuracy ±3%

Under voltage falling threshold

Under voltage rising threshold

(24)

Under voltage hysteresis 6 %

Under voltage deglitch filter 5 µs

Current limit protection 1.6 2.5 A

Current limit deglitch time 50 ns

Current limit response time

Normal operating mode (no UV)

(11)

I_limUV

dead

REGPWM

Battery charger (Bridge 4)

AUX3_SW

FBRef

Current limit response time in UV condition.

Switching output rise time

Switching output fall time

UV condition

Supply

LOAD

Supply

LOAD

(12)

= 36V,

= 422 Ω

= 36V,

= 10 Ω

(25)

(23)

350 500 ns

530ns

10 50 ns

Crossover dead time 100 ns

Operating frequency F

Output pin voltage range (DC4x)

Output leakage current T

(26)

-1 V

= 125°C -100 +100 µA

junction

/64 kHz

osc

Supply

SelFBRef = ‘00’ 1.37 1.412 1.455 V

Battery charger control loop feedback reference voltage

SelFBRef = ‘01’

(8)

SelFBRef = ‘10’ 2.079 2.143 2.207 V

1.746 1.8 1.854 V

SelFBRef = ‘11’ 2.425 2.5 2.575 V

Doc ID 17713 Rev 1 23/139

Electrical specifications L6460

Table 5. Electrical characteristics (continued)

Parameter Description Test condition Min Typ Max Unit

SelCurrRef = ‘00’

(8)

0.873 0.9 0.927 V

CurrRef

out

load

DSon

loop

BC_UV_f

BC_UV_r

BC_UV_hys

aux_UV

limit

deglitch

I_lim

I_limUV

dead

BCPWM

Battery charger control loop feedback reference current

Output voltage range V

Output load current V

Internal high/low side R

Loop voltage accuracy ±3%

Under voltage falling threshold

Under voltage rising threshold

Under voltage hysteresis 6 %

Under voltage deglitch filter 5 µs

Current limit protection 3.2 5 A

Current limit deglitch time 50 ns

Current limit response time

Current limit response time in UV condition.

Switching output rise time

Switching output fall time

Crossover dead time 100 ns

Operating frequency F

ADC with A2DType=0

(29)

DSon

SelCurrRef = ‘01’ 1.394 1.437 1.48 V

SelCurrRef = ‘10’ 1.746 1.8 1.854 V

SelCurrRef = ‘11’ 2.182 2.25 2.318 V

(27)

= 36V

Supply

= 36V 0.002 3 A

Supply

= 125°C;

junction

= 1.5A

LOAD

(28)

Normal operating mode (no UV)

UV condition

V R

Supply

LOAD

Supply

LOAD

(11)

(12)

= 36V,

= 422 Ω

= 36V,

= 10 Ω

(25)

1.412 30 V

0.3 0.4 Ω

84.5 87 89.5 %

90.5 93 95.5 %

480 700 ns

350 500 ns

530ns

10 50 ns

/64 kHz

osc

IMR Measurement range A2dType = 0 0 V

INL Integral non-linearity A2dType = 0

DNL Differential non-linearity A2dType = 0

OE Offset error A2dType = 0

Drift

Offset error drift

A2dType = 0 over time and temperature

GE Gain error A2dType = 0

Drift

conv

Gain error drift

Minimum conversion time 55 µs

Resolution

A2dType = 0 over time and temperature

(35)

24/139 Doc ID 17713 Rev 1

(30)(31)

(32)(31)

(33)

3v3

±2 LSB

±4 LSB

±3 LSB

(34)

±4 LSB

8bits

L6460 Electrical specifications

Table 5. Electrical characteristics (continued)

Parameter Description Test condition Min Typ Max Unit

Input sampling capacitance

ADC with A2DType=1

(37)

(36)

4pF

IMR Measurement range A2dType = 1 0 V

INL Integral non-linearity A2dType = 1

DNL Differential Non-Linearity A2dType = 1

OE Offset error A2dType = 1

Drift

Offset error drift

A2dType = 1 over time and temperature

GE Gain error A2dType = 1

Drift

conv

Gain error drift

Minimum conversion time 10 µs

A2dType = 1 over time and temperature

(30)(31)

(32)(31)

(33)

(34)

Resolution 9 bits

Input sampling capacitance

(36)

Current DAC

OUT_OFF

FULL_ERR

INL

10_11

DNL

10_11

Pin voltage operative range (GPIO8)

Output off leakage current DacValue[5:0] = 000000 -1 +1 µA

Full scale current error

Integral non-linearity for 10 and 11 ranges

Differential non-linearity for 10 and 11 ranges

(38)

DacRange[1:0] =xx DacValue[5:0] = 111111

0.7 5.5 V

-15 +15

3v3

±1 LSB

±4 LSB

±3 LSB

±4 LSB

4pF

% of

FULL

typ

±2 LSB

INL

DNL

CurrDac_res

CurrDac_ratio

set

Operational amplifier

GPIO_SPI

ICM

OUT_MAX

Integral non-linearity for 01 range

Differential non-linearity for 01 range

Gpio[8] divider total resistance 45

Gpio[8] divider ratio 3/5

Settling time

(40)

Operational amplifier supply voltage range

Input common mode voltage range

Output voltage I

(39)

3.15 3.3 3.45 V

=± 1mA 0.1 3.2 V

LOAD

Doc ID 17713 Rev 1 25/139

±1 LSB

kΩ

5µs

GPIO_

SPI

Electrical specifications L6460

Table 5. Electrical characteristics (continued)

Parameter Description Test condition Min Typ Max Unit

VOp1PlusRef

VOp2PlusRef

Operational amplifier 1 and 2 reference voltage

Avd Open loop gain

OpxRef[1:0]=00 OpxRef[1:0]=01 OpxRef[1:0]=10 OpxRef[1:0]=11

=1.65V

ICM

= 0mA

LOAD

0.97

1.6

1.94

2.425

90 dB

1.65 2

2.5

1.03

2.06

2.575

CMRR Common mode rejection ratio 80 110 dB

= ±6mA

(40) (41)

LOAD

=1.65V

ICM

=100pF V

load

=330 Ω to V

load

=1.65V 10 mA

out

= 0

load

=100pF

LOAD

=1.65V

ICM

GPIO_SPI

2MHz

1.3 1.75 V/µs

90 dB

PSRR Power supply rejection ratio

in _offs

in _bias

in _offs

Input offset current -150 150 nA

Input bias current -500 500 nA

Input offset voltage -5 5 mV

GBWP Gain bandwidth product

out

short_max

Output current V

Short circuit current 12 20 mA

SR Slew rate

Operational amplifier used as comparator

1.7 V

Low power switch

OUT_MAX

OFF

FAL L

RISE

PSW

OUT_MAX

DSon

LIMIT

deglitch

Output voltage I

=± 10mA 0.3 2.9 V

load

VCM = 1.65V

Turn off propagation delay

Fall time

Turn on propagation delay

Rise time

Δ Vi = -/+ 20mV C

=100pF

LOAD

= 1.65V

Δ Vi = -/+ 20mV

=100pF

LOAD

= 1.65V

Δ Vi = -/+ 20mV

=100pF

LOAD

= 1.65V

Δ Vi = -/+ 20mV

=100pF

LOAD

(42)(43)

0.6 1 µs

0.15 0.4 µs

0.25 0.5 µs

0.2 0.4 µs

Input voltage range 2.4 3.6 V

Output voltage

Switch R

DSon

resistance I

=100mA 0.6 1 Ω

load

GPIO_

SPI

Current limit 150 250 350 mA

Current limit deglitch time 50 ns

26/139 Doc ID 17713 Rev 1

L6460 Electrical specifications

Table 5. Electrical characteristics (continued)

Parameter Description Test condition Min Typ Max Unit

I_lim

LOAD

OFF

Current limit response time 650 ns

Max load capacitance 2.5 µF

Turn on propagation delay

Turn off propagation delay

GPIO_SPI

LOAD

GPIO_SPI

LOAD

Interrupt controller

PULSE

INTFILT

Pulse duration 16*T

Filter time 200 ns

GPIO[0], GPIO[1], GPIO[2], GPIO[3], GPIO[4], GPIO[6]

HYS

LEAKAGE

DELAY

High level input voltage 1.6 V

Low level input voltage 0.8 V

Input voltage hysteresis 0.15 0.22 V

Low level output voltage I

= 15mA 0.5 V

OUT

Leakage current 0 ≤ V

Delay from serial write to pin Low

LOAD

=100pF

=1mA

=100pF

≤ V

out

=50 pF

=3.3V I

(44)

=3.3V

(44)

3v3

(45)

LOAD

=1mA

450 650 ns

250 450 ns

osc

µs

-1 1 µA

500 ns

GPIO[5], GPIO[7], GPIO[9], GPIO[10], GPIO[11], GPIO[12], GPIO[13], GPIO[14]

HYS

LEAKAGE

DELAY

High level input voltage 1.6 V

Low level input voltage 0.8 V

Input voltage hysteresis 0.15 0.22 V

Low level output voltage I

High level output voltage I

Leakage current 0 ≤V

Delay from serial write to pin low

= 15mA 0.5 V

OUT

= 5mA 2.75 V

OUT

≤ V

out

3v3

LOAD

=50 pF

(45)

GPIO[8]

HYS

LEAK_0

LEAK_1

High level input voltage 1.6 V

Low level input voltage 0.8 V

Input voltage hysteresis 0.13 0.22 V

Low level output voltage I

Leakage current

= 15mA, 0.4 V

OUT

EnGpio8DigIn=0, 0 ≤ Vout ≤ 5V

EnGpio8DigIn=1, 0 ≤ Vout ≤ 5V

-1 1 µA

500 ns

-1 1 µA

-1 5 µA

Doc ID 17713 Rev 1 27/139

Electrical specifications L6460

Table 5. Electrical characteristics (continued)

Parameter Description Test condition Min Typ Max Unit

ADChannelX[4:0]

DELAY

SPI interface

HYS

SCLK

SCLK_rise

SCLK_fall

SCLK_high

SCLK_low

nSS_setup

nSS_hold

nSS_min

MOSI_setup

MOSI_hold

MISO_rise

MISO_fall

MISO_valid

MISO_disable

LOAD

1. This value is useful to define the voltage rating for external capacitor to be connected from V

2. This typical value is only intended to give an estimation of the current consumption when L6460 is configured in simple regulators mode (see following Chapter 8.6.4) at the end of the start up sequence and with no load on regulators. This typical value allows a raw choose of the external resistor but the definitive choose must be done according to the recommendations on Chapter 4.1).

3. Measured between 10% and 90% of output voltage transition.

4. Measured from a fault detection to 50% of output voltage transition.

5. Current is defined to be positive when flowing into the pin.

6. Load regulation is calculated at a fixed junction temperature using short load pulses covering all the load current range. This is to avoid change on output voltage due to heating effect.

7. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (V

8. Default state.

9. The regulated voltage can be calculated using the formula: V

A/D path absorbed current

=10001 and

-1 1 µA

bit EnDacScale=0

Delay from serial write to pin low

(40)

High level input voltage

Low level input voltage

Input voltage hysteresis

High level output voltage I

Low level output voltage I

(46)

OUT

LOAD

=50 pF

= -10mA,

= 10mA,

(45)

500 ns

1.6 V

0.8 V

0.15 0.22 V

(47)

2.75 V

0.4 V

SCLK period 62.5 ns

SCLK rise time 2 ns

SCLK fall time 2 ns

SCLK high time 20 ns

SCLK low time 20 ns

nSS setup time 10 ns

nSS hold time 10 ns

nSS high minimum time 30 ns

MOSI setup time 10 ns

MOSI hold time 10 ns

MISO rise time C

MISO fall time C

LOAD

=50pF

(48)

9ns

MISO valid from clock low 0 15 ns

MISO disable time 0 15 ns

MOSI maximum load 200 pF

SWmain_OUT = VFBREF

Supply

*(Ra+Rb)/Rb.

to V

LINmain_FB

SupplyInt

28/139 Doc ID 17713 Rev 1

L6460 Electrical specifications

10. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (V

SW_main_FB

11. This condition is intended to simulate an extra current on output.

12. This condition is intended to simulate a short circuit on output.

13. Rise and fall time are measured between 10% and 90% V

14. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (V

SWmain

output voltage.

SWDRV_FB

15. The current protection values must be intended as a protection for the chip and not as a continuous current limitation. The protection is performed by switching off the output bridge when current reaches values higher than the I protection could be guaranteed for values in the middle range between I

MAX

and I

max. No

16. In this cell X stands for 1 or 2, Y stands for A or B

17. In this cell X stands for 3 or 4, Y stands for A or B

18. The current protection thresholds for Bridge 3 and 4 are not selectable so only the max current value (MtrXSideYILimSel[1:0]= 11) is available.

19. Overcurrent Off time can be configured using SPI.

20. Rise and fall time are measured between 10% and 90% of DC output voltage. With device in full bridge configuration (resistive load between outputs).

21. Default state for Aux1

22. Default state for Aux2

23. The regulated voltage can be calculated using the formula: V

AUX_SW

= V

FBREF

*(Ra+Rb)/Rb.

24. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (GPIO1 and/or GPIO2)

25. Rise and fall time is measured between 10% and 90% of output voltage.

26. The external components connected to the pin must be chosen to avoid that the voltage exceeds this operative range.

27. The regulated voltage can be calculated using the formula: V

AUX3_SW

= V

28. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (V

7.5

29. The definition of LSB for this table is LSB=IMRmax/(2

30. Integral Non Linearity error (INL) is defined as the maximum distance between any point of the ADC characteristic and the “best straight line” approximating the ADC transfer curve.

-1).

FBREF

*(Ra+Rb)/Rb.

REF_FB

31. The ADC ensures monotonic characteristic and no missing codes.

32. Differential nonlinearity error (DNL) is defined as the difference between an actual step width and the ideal width value of 1 LSB.

33. Offset error (OE) is the deviation of the first code transition (000...000 to 000...001) from the ideal (i.e. GND + 0.5 LSB).

34. Gain error (GE) is the deviation of the last code transition (111...110 to 111...111) from the ideal (V3v3 - 0.5 LSB), after adjusting for offset error.

35. Please note that the result of the conversion will always be a 9-bit word: to speed up the conversion, the resolution is reduced when the ADC is used in the 8- bit resolution mode.

36. Actual input capacitance depends on the pin that must be converted.

37. The definition of LSB for this table is LSB=IMRmax/(2

38. All parameters are guaranteed in the range between V

-1).

and V

R Max

39. Measured from DacValue[5:0] change in SPI interface.

40. V

GPIO_SPI

= 3.3 V unless otherwise specified

41. In this section reports the operational amplifier parameters that change when used as comparator.

42. ΔVi is the differential voltage applied to input pins across the common voltage V

43. Measured between 50% of input and output signal.

44. Time measured from change in SPI interface to 50% of external pin transition.

45. Measured between nSS rising edge and 50% of V

46. Specification applies to nSS, SCLK and MOSI pins.

47. Current is considered to be positive when flowing towards the IC

48. These times are measured at the pin output between specified V

out

and VOL.

Doc ID 17713 Rev 1 29/139

Internal supplies L6460

4 Internal supplies

L6460 includes three internal regulators used to provide a regulated voltage to internal circuits.

The internal regulators are the following:

- V

- Charge pump regulator.

- V

4.1 V

V regulator is not intended to provide external current so it must not be used to supply external loads. An external capacitor must always be connected to this pin (preferably towards V

Figure 3. V

SupplyInt

3v3

SupplyInt

Supply

regulator.

regulator

is the output of an internal regulator used to supply some internal circuits. This

pin), recommended value is in the range 80 ÷ 120 nF.

SupplyInt

Vsupply

VsupplyInt

L6460

internal circuits

IS_Int_TYP

L6460

The V

SupplyInt

resistor R

pin may also be externally connected to V

: this allows R

EXT

, particularly when V

EXT

operative supply range, to dissipate power that otherwise would be dissipated inside the chip. The choice of the optimal resistor depends on the application since it is strictly depending on both V

and the current used inside the chip (that is changing with the

Supply

chosen configuration).

could be chosen by applying this formula: R

EXT

max is depending from the chosen configuration and represents the total current needed

S_Int

by the circuits connected to this pin.

For example, with V

30/139 Doc ID 17713 Rev 1

= 32 V and I

Supply

S_Int

GND

pin by means of an external

Supply

is at the max values of the

Supply

EXT

= (V

Supply

min - V

S_Int

max)/(I

S_Int

= 12 mA a typical resistor value is 1 kΩ.

max).

+ 109 hidden pages

ST L6460 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Table 1. Device summary

1 General description

1.1 Overview

Figure 1. Block diagram

1.2 Pin connection

Figure 2. Pin connection

1.3 Pin list

Table 2. Pins configuration

2 L6460’s main features

3 Electrical specifications

3.1 Absolute maximum rating

Table 3. Absolute maximum ratings

3.2 Operating ratings specifications

Table 4. IC operating ratings

3.3 Electrical characteristics

Table 5. Electrical characteristics

4 Internal supplies