ST L6327, L6332 User Manual

L6327 L6332
6 / 4 CHANNEL VOLTAGE SENSE GMR PREAMPLIFIER
PRODUCT PREVIEW
TSSOP38
ORDERING NUMBERS: L6327 L6332
head, including 100ns blanking period)
Head-to-head switch in READ mode - 10μs (nom)
Head and MR bias current switching transient current head protection
READ-to-WRITE switching 50ns (same head)
Programmable read bias during write and bank write operation
ESD diode for GMR head protection
DESCRIPTION
L6327/L6332 is a BICMOS monolithic integrated circuit GMR differential preamplifier designed for use with four-terminal magneto-resistive GMR read/inductive write heads. It is available as either a six (L6327) or four (L6332) channel device. The devices consist of a voltage-sense, current-bias or voltagebias (selectable), differential input and differential output, low-noise, high bandwidth read amplifier and include fast current switching write drivers which support data rates in excess of 550 Mb/s with 70nH write heads.
The GMR preamplifier provides programmable read current / voltage bias and write current (5 bit DAC for the read bias, 5 bit DAC for the write current), fault detection circuitry and servo writing features. Read amplifier gain, write current wave shape (overshoot, undershoot and damping) can be adjusted and a thermal asperity detection and correction circuit can be enabled and programmed with different thresholds (6 bit DAC) through a 16-bit bi-directional serial interface (SDEN, SDATA, SCLK). The device operates from a +5V supply and a -5V supply (nominal). No external components are required as a trimmed or untrimmed resistor for reference current setting is employed.
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L6327

Power Supplies +5Vdc, -5Vdc

Current bias or voltage bias (selectable) / Differential Voltage Sense architecture

6 or 4 channel versions

38-pin TSSOP package (for either 6 or 4 channels)

Internal reference Resistor for read and write currents

Read channel -3dB bandwidth > 400MHz (Rmr=50 ohm no interconnect)

Input equivalent preamplifier voltage noise 0.5nV/rtHz nominal

Input equivalent MR bias current noise 10 pA/ rtHz nominal

MR bias current programmable (5 bit DAC) 1.5- 7.0mA nominal MR bias voltage programmable (5 bit DAC) 65-335mV nominal

Programmable gain (100V/V, 150, 200 and 250V/V) and read bandwidth

Write frequency up to 300 MHz (Lh=70nH, Rh=20 ohms, Ch=2pF, VEE=-5V)

Rise/Fall time 0.6ns ( Iw =40mA 0-pk, Lh=70nH, Rh=20 ohms, Ch=2pF, VEE=-5V)

Write current programmable (5 bit DAC) 15-60mA

PECL write data input

Bi-directional 16-bit TTL Serial interface for head selection, read/write currents selection, chip parameters modification, chip enable, vendor code and fault status read back registers

2-pin mode selection (R/W, MRR)

Bank write feature for servo write

Digital buffered head voltage DBHV / Analog buffered head voltage ABHV pin (gain 5)

Thermal asperity detection & correction with adjustable sensitivity level (6 bit DAC)

Automatic successive approximation digital measurement of temperature and Rmr (7 bits)

Read and write head open/short detection, low low supply detect and temperature monitoring (high temperature warning and Analog Temperature Diode Voltage measurement)

Low write frequency detection.

WRITE to READ fast recovery 150ns (same

February 2001

This is preliminary information on a new product now in development. Details are subject to change without notice.

ST L6327, L6332 User Manual

L6327 - L6332

BLOCK DIAGRAM

 

VCC (+5V)

VGND (0V)

VEE (-5V)

 

WDP

 

 

 

 

 

HW0P

 

 

 

 

 

 

 

PREDRIVER

 

 

 

 

HW0N

 

 

 

 

 

 

WDN

 

 

 

 

 

 

 

 

 

 

WRITE

 

3v

FAULT PROCESSOR

 

DRIVERS

 

FLT

Low supply detection,

 

 

 

 

Open/short heads,

 

 

 

 

 

TA detection,

 

 

 

HW1/5P

 

low write frequency,

 

 

 

 

high temperature

 

 

 

 

3v

 

 

 

 

 

HW1/5N

 

 

 

 

 

 

SDATA

 

 

 

WRITE

Rdamp

Overshoot, Undershhot

 

SERIAL INTERFACE

 

SCLK

 

DAC

CONTROL

 

 

 

 

 

 

 

 

SEN

 

 

Imr, Iwr

 

 

 

 

 

 

 

 

 

3v

 

 

RW enable

 

current/voltage

 

 

 

head select

 

 

 

 

 

READ

 

R/W

 

 

A2D

low bias

HEAD SELECTION

DAC

 

RMR, temp

 

 

 

 

&

 

 

 

MODE CONTROL

ABHV,

 

 

 

MRR

 

 

MR meas

 

 

HR0P

 

 

 

 

 

 

 

 

Temperature

 

 

 

ABHV/

 

 

monitoring

 

 

 

 

 

 

MR

 

HR0N

ADTV

 

 

TA detection,

 

 

 

 

TA correction

READ

 

 

RDP

 

 

 

INPUT

HR1/5P

 

 

 

STAGES

 

 

 

 

 

 

 

 

 

RDN

 

 

 

 

 

HR1/5N

 

 

 

 

 

 

Gain boost,

High pass

VREF

 

 

 

Low pass filter

filter

 

 

 

 

 

L6327/L6332 6/4 CH

 

 

 

 

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