Datasheet L6258EA Datasheet (ST)

high current DMOS universal motor driver

Features

■ Able to drive both windings of a bipolar stepper

motor or two DC motors

■ Output current up to 1.5A each winding

■ Wide voltage range: 12V to 40V

■ Four quadrant current control, ideal for

microstepping and dc motor control

■ Precision PWM control

■ No need for recirculation diodes

■ TTL/CMOS compatible inputs

■ Cross conduction protection

■ Thermal shutdow

■ Extended low operating temperature range:

-40°C

Description

L6258EA is a dual full bridge for motor control
applications realized in BCD technology, with the
capability of driving both windings of a bipolar
stepper motor or bidirectionally control two DC
motors.

L6258EA

PWM controlled

PowerSO36

The power stage is a dual DMOS full bridge
capable of sustaining up to 40V, and includes the
diodes for current recirculation.The output current
capability is 1.5A per winding in continuous mode,
with peak start-up current up to 2A. A thermal
protection circuitry disables the outputs if the chip
temperature exceeds the safe limits.

L6258EA and a few external components form a
complete control and drive circuit. It has high
efficiency phase shift chopping that allows a very
low current ripple at the lowest current control
levels, and makes this device ideal for steppers as
well as for DC motors.

Table 1. Device summary

Order code Package Packing

E-L6258EA PowerSO36 Tube

December 2007 Rev 5 1/32

www.st.com

1

Contents L6258EA

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2 Input logic (I0 - I1 - I2 - I3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3 Phase input ( PH ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4 Triangular generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5 Charge pump circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.6 Current control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.7 Current control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 PWM current control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1 Open loop transfer function analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2 Power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.3 Load attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.4 Error amplifier and sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.5 Effect of the Bemf on the current control loop stability . . . . . . . . . . . . . . . 22

4 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1 Interference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2 Motor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.3 Notes on PCB design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5 Operation mode time diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2/32

L6258EA List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 3. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 5. Current levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 6. Charge pump capacitor's values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 7. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3/32

List of figures L6258EA

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. Power bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5. Current control loop block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 6. Output comparator waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 7. Ax bode plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 8. Aloop bode plot (uncompensated) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 9. Aloop bode plot (compensated) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 10. Electrical model of the load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 11. Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 12. Full step operation mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 13. Half step operation mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 14. 4 bit microstep operation mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 15. PowerSO36 mechanical data & package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4/32

L6258EA Block diagram

1 Block diagram

Figure 1. Block diagram

R

1M

VDD(5V)

TRI_CAP

VCP1

VREF1

I3_1

I2_1

I1_1

I0_1

PH_1

VREF1

I3_2

I2_2

I1_2

I0_2

PH_2

C

FREF

C

P

CHARGE

PUMP

DAC

VR GEN

DAC

TRIANGLE

GENERATOR

VR (VDD/2)

TRI_0

TRI_180

INPUT

&

SENSE

AMP

INPUT

&

SENSE

AMP

EA_IN1 EA_OUT1VCP2

THERMAL

PROT.

1

C

C1

R

C1

TRI_0

+

C

TRI_0

TRI_180

-

+

C

-

+

C

-

+

C

-

ERROR

V

R

AMP

+

TRI_180

-

ERROR

V

R

AMP

+

-

VS

POWER
BRIDGE

C

1

POWER
BRIDGE

2

BOOT

VBOOT

OUT1A

OUT1B

SENSE1B

SENSE1A

DISABLE

VS

OUT2A

OUT2B

SENSE2B

SENSE2A

R

s

R

s

EA_IN2 EA_OUT2GND

R

C2

C

C2

R

1M

2

Table 2. Absolute maximum rating

Parameter Description Value Unit

V

s

V

DD

V

ref1/Vref2

I

O

I

O

V

in

V

boot

- V

V

boot

s

T

j

T

stg

1. This current is intended as not repetitive current for max. 1 second.

Supply voltage 45 V

Logic supply voltage 7 V

Reference voltage 2.5 V

Output current (peak)

(1)

Output current (continuous) 1.5 A

Logic input voltage range -0.3 to 7 V

Bootstrap supply 60 V

Maximum Vgate applicable 15 V

Junction temperature 150 °C

Storage temperature range -55 to 150 °C

D96IN430D

2A

5/32

Block diagram L6258EA

Figure 2. Pin connection (top view)

PWR_GND

PH_1

I1_1

I0_1

OUT1A

DISABLE

TRI_CAP

V

GND

VCP1

VCP2

VBOOT

VS

OUT2A

I0_2

I1_2

PH_2

PWR_GND

DD

1

2

3

4

5

6

7

8

9

10

11

12

13 24

14

15

16

17

18

D96IN432F

36

35

34

33

32

31

30

29

28

27

26

25

23

22

21

20

19

PWR_GND

SENSE1

OUT1B

I3_1

I2_1

VS

EA_OUT1

EA_IN1

VREF1

SIG_GND

VREF2

EA_IN2

EA_OUT2

I2_2

I3_2

OUT2B

SENSE2

PWR_GND

Table 3. Pin functions

Pin # Name Description

1, 36 PWR_GND

Ground connection (1). They also conduct heat from die to
printed circuit copper.

These TTL compatible logic inputs set the direction of

2, 17 PH_1, PH_2

current flow through the load. A high level causes current to
flow from OUTPUT A to OUTPUT B.

Logic input of the internal DAC (1). The output voltage of the

3I

1_1

DAC is a percentage of the Vref voltage applied according to
the thruth Table 5 on page 12.

4I

0_1

See pin 3

5 OUT1A Bridge output connection (1)

6 DISABLE

7TRI_cap

Disables the bridges for additional safety during switching.
When not connected the bridges are enabled

Triangular wave generation circuit capacitor. The value of
this capacitor defines the output switching frequency

6/32

L6258EA Block diagram

Table 3. Pin functions (continued)

Pin # Name Description

8V

(5V) Supply voltage input for logic circuitry

DD

9 GND Power ground connection of the internal charge pump circuit

10 V

11 V

12 V

BOOT

13, 31 V

CP1

CP2

S

Charge pump oscillator output

Input for external charge pump capacitor

Overvoltage input for driving of the upper DMOS

Supply voltage input for output stage. They are shorted
internally

14 OUT2A Bridge output connection (2)

Logic input of the internal DAC (2). The output voltage of the

15 I

0_2

DAC is a percentage of the VRef voltage applied according
to the truth Table 5 on page 12.

16 I

1_2

18, 19 PWR_GND

See pin 15

Ground connection. They also conduct heat from die to
printed circuit copper

20, 35 SENSE2, SENSE1 Negative input of the transconductance input amplifier (2, 1)

21 OUT2B

22 I

23 I

3_2

2_2

Bridge output connection and positive input of the
tranconductance (2)

See pin 15

See pin 15

24 EA_OUT_2 Error amplifier output (2)

25 EA_IN_2 Negative input of error amplifier (2)

Reference voltages for the internal DACs, determining the

26, 28 V

REF2

, V

REF1

output current value. Output current also depends on the
logic inputs of the DAC and on the sensing resistor value

27 SIG_GND Signal ground connection

29 EA_IN_1 Negative input of error amplifier (1)

30 EA_OUT_1 Error amplifier output (1)

32 I

33 I

2_1

3_1

34 OUT1B

See pin 3

See pin 3

Bridge output connection and positive input of the
tranconductance (1)

Note: The number in parenthesis shows the relevant Power Bridge of the circuit. Pins 18, 19, 1

and 36 are connected together.

7/32

Block diagram L6258EA

Figure 3. Thermal characteristics

Conditions

pad layout + ground layers + 16 via hol

PCB ref.: 4 LAYER cm 12 x 12

pad layout + ground layers

PCB ref.: 4 LAYER cm 12 x 12

pad layout + 6cm2 on board heat sink

PCB ref.: 2 LAYER cm 12 x 12

12

10

8

6

4

Power Dissipated (W)

2

Power Dissipated

(W)

5.3 70 15

4.0 70 20

2.3 70 35

15˚C/W

20˚C/W

35˚C/W

T Ambient

(˚C)

Thermal J-A resistance

(˚C/W)

D02IN1370

0

0-20-40

20 40 60 80 100 120 140 160

Ambient Temperature (˚C)

D04IN1525A

Table 4. Electrical characteristics

(V

= 40V; VDD = 5V; Tj = 25°; unless otherwise specified.)

S

Parameter Description Test condition Min. Typ. Max. Unit

V

V

V

BOOT

V

Sense

V

S(off)

V

DD(off)

I

S(on)

I

S(off)

I

DD

DD

Supply voltage 12 40 V

S

Logic supply voltage 4.75 5.25 V

Storage voltage VS = 12 to 40V VS+6 VS+12 V

Max drop across sense
resistor

Power off reset Off threshold 6 7.2 V

Power off reset Off threshold 3.3 4.1 V

VS quiescent current Both bridges ON, no load 15 mA

VS quiescent current Both bridges OFF 7 mA

VDD operative current 15 mA

1.25 V

8/32

L6258EA Block diagram

Table 4. Electrical characteristics (continued)

(V

= 40V; VDD = 5V; Tj = 25°; unless otherwise specified.)

S

Parameter Description Test condition Min. Typ. Max. Unit

ΔT

SD-H

T

f

osc

SD

Shut down hysteresis 25 °C

Thermal shutdown 150 °C

Triangular oscillator
frequency

TRANSISTORS

I

R

DSS

ds(on)

V

Leakage current OFF State 500 μA

On resistance ON state 0.6 0.75 W

Flywheel diode voltage If =1.0A 1 1.4 V

f

CONTROL LOGIC

V

in(H)

V

in(L)

I

in

I

dis

V

ref1/ref2

I

ref

FI =

V

ref/Vsense

V

FS

V

offset

lnput voltage All Inputs 2 V

Input voltage All inputs 0 0.8 V

Input current

Disable pin input current -10 +150 μA

Reference voltage Operating 0

V

terminal input current V

ref

PWM loop transfer ratio 2

DAC full scale precision V

Current loop offset

DAC factor ratio

(1)

(2)

C

= 1nF 12.5 15 18.5 KHz

FREF

DD

-150 +10 μA

0 < Vin < 5V

(3)

= 1.25 -2 5 μA

ref

= 2.5V I0/I1/I2/I3 = L 1.23 1.34 V

ref

V

= 2.5V I0/I1/I2/I3 = H -30 +30 mV

ref

= 2V I0/I1/I2/I3 = H;

V

ref

= -40 to 125°C

T

j

Normalized @ full scale

value

-60 +60 mV

-2 +2 %

V

V

SENSE AMPLIFIER

V

cm

I

inp

lnput common mode
voltage range

Input bias sense1/sense2 -200 0 μA

-0.7 V

+0.7 V

S

ERROR AMPLIFIER

G

Open loop voltage gain 70 dB

V

SR Output slew rate Open loop 0.2 V/μs

GBW Gain bandwidth product 400 kHz

1. Chopping frequency is twice fosc value.

2. This is true for all the logic inputs except the disable input.

is inside the range -40 to -10°C then V

3. If T

j

then V

max is 2.5V.

ref

max is 2V+0.5V·(Tj + 40°C)/30°C. If Tj is greater than -10°C

ref

9/32

Functional description L6258EA

2 Functional description

The circuit is intended to drive both windings of a bipolar stepper motor or two DC motors.

The current control is generated through a switch mode regulation.

With this system the direction and the amplitude of the load current are depending on the
relation of phase and duty cycle between the two outputs of the current control loop.

The L6258EA power stage is composed by power DMOS in bridge configuration as it is
shown in Figure 4, where the bridge outputs OUT_A and OUT_B are driven to V
high level at the inputs IN_A and IN_B while are driven to ground with a low level at the
same inputs.

The zero current condition is obtained by driving the two half bridge using signals IN_A and
IN_B with the same phase and 50% of duty cycle.

In this case the outputs of the two half bridges are continuously switched between power
supply (V

) and ground, but keeping the differential voltage across the load equal to zero.

s

In Figure 4 is shown the timing diagram of the two outputs and the load current for this
working condition.

Following we consider positive the current flowing into the load with a direction from OUT_A
to OUT_B, while we consider negative the current flowing into load with a direction from
OUT_B to OUT_A.

with an

s

Now just increasing the duty cycle of the IN_A signal and decreasing the duty cycle of IN_B
signal we drive positive current into the load.

In this way the two outputs are not in phase, and the current can flow into the load trough the
diagonal bridge formed by T1 and T4 when the output OUT_A is driven to V

and the output

s

OUT_B is driven to ground, while there will be a current recirculation into the higher side of
the bridge, through T1 and T2, when both the outputs are at Vs and a current recirculation
into the lower side of the bridge, through T3 and T4, when both the outputs are connected to
ground.

Since the voltage applied to the load for recirculation is low, the resulting current discharge
time constant is higher than the current charging time constant during the period in which
the current flows into the load through the diagonal bridge formed by T1 and T4. In this way
the load current will be positive with an average amplitude depending on the difference in
duty cycle of the two driving signals.

In Figure 4 is shown the timing diagram in the case of positive load current

On the contrary, if we want to drive negative current into the load is necessary to decrease
the duty cycle of the IN_A signal and increase the duty cycle of the IN_B signal. In this way
we obtain a phase shift between the two outputs such to have current flowing into the
diagonal bridge formed by T2 and T3 when the output OUT_A is driven to ground and
output OUT_B is driven to Vs, while we will have the same current recirculation conditions of
the previous case when both the outputs are driven to Vs or to ground.

So, in this case the load current will be negative with an average amplitude always
depending by the difference in duty cycle of the two driving signals.

In Figure 4 is shown the timing diagram in the case of negative load current.

Figure 5 shows the device block diagram of the complete current control loop.

10/32

L6258EA Functional description

2.1 Reference voltage

The voltage applied to VREF pin is the reference for the internal DAC and, together with the
sense resistor value, defines the maximum current into the motor winding according to the
following relation:

0,5 V

----------------------------- -

where R

= sense resistor value

s

I

MAX

Figure 4. Power bridge configuration

IN_A IN_B

OUTA

OUTB

Iload

0

T1

OUT_A OUT_B

T3

⋅

R

S

V

S

LOAD

REF

T2

T4

1

-----

FI

V

REF

--------------

⋅==

R

S

Fig. 1A

OUTA

OUTB

Iload

OUTA

OUTB

Iload

Fig. 1B

0

Fig. 1C

0

D97IN624

11/32

Functional description L6258EA

Figure 5. Current control loop block diagram

POWER AMPL.

VS

OUTA

OUTB

D97IN625

LOAD

R

L

L

L

R

S

VREF

PH

Tri_0

INPUT TRANSCONDUCTANCE

I0

I1

I2

I3

DAC

VDAC

AMPL.

ia

+

-

Gin=1/Ra

ERROR AMPL.

V

R

+

­ic

Rc

Cc

ib

-

VSENSE

+

Gs=1/Rb

SENSE TRANSCONDUCTANCE

AMPL.

Tri_180

-

+

VS

-

+

2.2 Input logic (I0 - I1 - I2 - I3)

The current level in the motor winding is selected according to this table:

Table 5. Current levels

I3 I2 I1 I0

HHHH No Current

HHHL 9.5

HHLH 19.1

HHLL 28.6

HLHH 38.1

HLHL 47.6

HLLH 55.6

HLLL 63.5

LHHH 71.4

LHHL 77.8

LHLH 82.5

Current level

% of IMAX

12/32

L6258EA Functional description

Table 5. Current levels (continued)

I3 I2 I1 I0

LHLL 88.9

LLHH 92.1

LLHL 95.2

LLLH 98.4

LLLL 100

2.3 Phase input ( PH )

The logic level applied to this input determines the direction of the current flowing in the
winding of the motor.

High level on the phase input causes the motor current flowing from OUT_A to OUT_B
through the load.

2.4 Triangular generator

This circuit generates the two triangular waves TRI_0 and TRI_180 internally used to
generate the duty cycle variation of the signals driving the output stage in bridge
configuration.

Current level

% of IMAX

The frequency of the triangular wave defines the switching frequency of the output, and can
be adjusted by changing the capacitor connected at TR1_CAP pin:

where: K = 1.5 x 10

-5

2.5 Charge pump circuit

To ensure the correct driving of the high side drivers a voltage higher than Vs is supplied on
the Vboot pin. This boostrap voltage is not needed for the low side power DMOS transistors
because their sources terminals are grounded. To produce this voltage a charge pump
method is used. It is made by using two external capacitors; one connected to the internal
oscillator (CP) and the other (Cboot) to storage the overvoltage needed for the driving the
gates of the high side DMOS. The value suggested for the capacitors are:

Table 6. Charge pump capacitor's values

Component name Component's function Value Unit

C

boot

C

P

Storage capacitor 100 nF

Pump capacitor 10 nF

ref

K

--- -=

C

F

13/32

Functional description L6258EA

2.6 Current control loop

The current control loop is a transconductance amplifier working in PWM mode.

The motor current is a function of the programmed DAC voltage.

To keep under control the output current, the current control modulates the duty cycle of the
two outputs OUT_A and OUT_B, and a sensing resistor Rs is connected in series with the
motor winding in order to produce a voltage feedback compared with the programmed
voltage of the DAC.

The duty cycle modulation of the two outputs is generated comparing the voltage at the
outputs of the error amplifier, with the two triangular wave references.

In order to drive the output bridge with the duty cycle modulation explained before, the
signals driving each output (OUTA & OUTB) are generated by the use of the two
comparators having as reference two triangular wave signals Tri_0 and Tri_180 of the same
amplitude, the same average value (in our case Vr), but with a 180° of phase shift each
other.

The two triangular wave references are respectively applied to the inverting input of the first
comparator and to the non inverting input of the second comparator.

The other two inputs of the comparators are connected together to the error amplifier output
voltage resulting by the difference between the programmed DAC. The reset of the
comparison between the mentioned signals is shown in Figure 6.

Figure 6. Output comparator waveforms

Tri_0

Error Ampl.

Output

Tri_180

First Comp.
Output

Second Comp.
Output

In the case of V

equal to zero, the transconductance loop is balanced at the value of Vr,

DAC

so the outputs of the two comparators are signals having the same phase and 50% of duty
cycle.

As we have already mentioned, in this situation, the two outputs OUT_A and OUT_B are
simultaneously driven from V

to ground; and the differential voltage across the load in this

s

case is zero and no current flows in the motor winding.

14/32

L6258EA Functional description

With a positive differential voltage on V

(see Figure 5, the transconductance loop will be

DAC

positively unbalanced respected Vr.

In this case being the error amplifier output voltage greater than Vr, the output of the first
comparator is a square wave with a duty cycle higher than 50%, while the output of the
second comparator is a square wave with a duty cycle lower than 50%.

The variation in duty cycle obtained at the outputs of the two comparators is the same, but
one is positive and the other is negative with respect to the 50% level.

The two driving signals, generated in this case, drive the two outputs in such a way to have
switched current flowing from OUT_A through the motor winding to OUT_B.

With a negative differential voltage V

, the transconductance loop will be negatively

DAC

unbalanced respected Vr.

In this case the output of the first comparator is a square wave with a duty cycle lower than
50%, while the output of the second comparator is a square wave with a duty cycle higher
than 50%.

The variation in the duty cycle obtained at the outputs of the two comparators is always of
the same.

The two driving signals, generated in this case, drive the the two outputs in order to have the
switched current flowing from OUT_B through the motor winding to OUT_A.

2.7 Current control loop compensation

In order to have a flexible system able to drive motors with different electrical characteristics,
the non inverting input and the output of the error amplifier ( EA_OUT ) are available.

Connecting at these pins an external RC compensation network it is possible to adjust the
gain and the bandwidth of the current control loop.

15/32

PWM current control loop L6258EA

3 PWM current control loop

3.1 Open loop transfer function analysis

Block diagram: refer to Figure 5.

Input parameters:

● V

● L

● R

● R

● R

● C

● Gs transconductance gain = 1/Rb

● Gin transconductance gain = 1/Ra

● Ampl. of the Tria_0_180 ref. = 1.6V (peak to peak)

● R

● R

● V

these data refer to a typical application, and will be used as an example during the analysis
of the stability of the current control loop.

= 24V

S

= 12mH

L

= 12Ω

L

= 0.33Ω

S

= to be calculated

C

= to be calculated

C

= 40KΩ

a

= 20KΩ

b

= Internal reference equal to VDD/2 (Typ. 2.5V)

r

The block diagram shows the schematics of the L6258 internal current control loop working
in PWM mode; the current into the load is a function of the input control voltage V

DAC

, and

the relation between the two variables is given by the following formula:

I

I

LOAD

LOAD

I

⋅⋅ V

LOAD

V

· RS · GS = V

1

-------

R

S

R

b

R

----------------------

⋅ 0,5

DAC

RaRs⋅

b

DAC

DAC

· G

⋅=

in

1

-------

R

a

V

-------------- -

DAC

R

S

A()⋅==

where:

V

G

G

R

DAC

in

s

s

is the control voltage defining the load current value

is the gain of the input transconductance amplifier ( 1/Ra )

is the gain of the sense transconductance amplifier ( 1/Rb )

is the resistor connected in series to the output to sense the load current

In this configuration the input voltage is compared with the feedback voltage coming from
the sense resistor, then the difference between this two signals is amplified by the error
amplifier in order to have an error signal controlling the duty cycle of the output stage
keeping the load current under control.

It is clear that to have a good performance of the current control loop, the error amplifier
must have an high DC gain and a large bandwidth.

16/32

L6258EA PWM current control loop

Gain and bandwidth must be chosen depending on many parameters of the application, like
the characteristics of the load, power supply etc..., and most important is the stability of the
system that must always be guaranteed.

To have a very flexible system and to have the possibility to adapt the system to any
application, the error amplifier must be compensated using an RC network connected
between the output and the negative input of the same.

For the evaluation of the stability of the system, we have to consider the open loop gain of
the current control loop:

Aloop = ACerr · ACpw · ACload · ACsense

where AC... is the gain of the blocks that refers to the error, power and sense amplifier plus
the attenuation of the load block.

The same formula in dB can be written in this way:

Aloop

So now we can start to analyse the dynamic characteristics of each single block, with
particular attention to the error amplifier.

3.2 Power amplifier

The power amplifier is not a linear amplifier, but is a circuit driving in PWM mode the output
stage in full bridge configuration.

The output duty cycle variation is given by the comparison between the voltage of the error
amplifier and two triangular wave references Tri_0 and Tri_180. Because all the current
control loop is referred to the Vr reference, the result is that when the output voltage of the
error amplifier is equal to the Vr voltage the two output Out_A and Out_B have the same
phase and duty cycle at 50%; increasing the output voltage of the error amplifier above the
Vr voltage, the duty cycle of the Out_A increases and the duty cycle of the Out_B decreases
of the same percentage; on the contrary decreasing the voltage of the error amplifier below
the Vr voltage, the duty cycle of the Out_A decreases and the duty cycle of the Out_B
increases of the same percentage.

The gain of this block is defined by the amplitude of the two triangular wave references;
more precisely the gain of the power amplifier block is a reversed proportion of the
amplitude of the two references.

In fact a variation of the error amplifier output voltage produces a larger variation in duty
cycle of the two outputs Out_A and Out_B in case of low amplitude of the two triangular
wave references.

= ACerrdB + ACpwdB + ACloaddB + ACsense

dB

dB

The duty cycle has the max value of 100% when the input voltage is equal to the amplitude
of the two triangular references.

The transfer function of this block consist in the relation between the output duty cycle and
the amplitude of the triangular references.

ACpw

dB

Vout = 2 · V

20

· (0.5 - DutyCycle)

S

V

Δ

out

----------------

log⋅

VinΔ

17/32

2V

⋅

------------------------------------------------------ -==

Triangular Amplitude

S

PWM current control loop L6258EA

224⋅

ACpw

dB

20

---------------- -

log⋅ 29,5dB==

1,6

Moreover, having the two references Tri_0 and Tri_180 a triangular shape it is clear that the
transfer function of this block is a linear constant gain without poles and zeros.

3.3 Load attenuation

The load block is composed by the equivalent circuit of the motor winding (resistance and
inductance) plus the sense resistor.

We will considered the effect of the Bemf voltage of the motor in the next chapter.

The input of this block is the PWM voltage of the power amplifier and as output we have the
voltage across the sense resistor produced by the current flowing into the motor winding.
The relation between the two variable is:

V

out

----------------------

RLRS+

RS⋅=

so the gain of this block is:

V

sense

V

sense

---------------------

v

20

dB

20

log⋅ 31,4dB–==

Aload

ACload

ACload

dB

where:

R

= equivalent resistance of the motor winding

L

R

= sense resistor

S

Because of the inductance of the motor L

Fpole

---------------------------------- -=

2π

Fpole

---------------------------------------------- 163Hz==
12 10

-------------------------- -

⋅

6,28

12 0,33+

R

S

----------------------==

log⋅=

0,33

RLRS+

R

S

----------------------

RLRS+

out

------------------------

12 0,33+

, the load has a pole at the frequency:

L

1

L

L

-------------------- -

⋅

RLRS+

1

3–

⋅

18/32

L6258EA PWM current control loop

Before analysing the error amplifier block and the sense transconductance block, we have to
do this consideration:

Aloop

Ax|dB = ACpw|dB + ACload|

= AxdB + Bx

dB

dB

dB

and

Bx|

= ACerr|dB + ACsense|

dB

dB

this means that Ax|dB is the sum of the power amplifier and load blocks;

Ax|

= (29,5) + (-31.4) = -1.9dB

dB

The BODE analysis of the transfer function of Ax is:

Figure 7. Ax bode plot

The Bode plot of the Ax|dB function shows a DC gain of -1.9dB and a pole at 163Hz.

It is clear now that (because of the negative gain of the Ax function), Bx function must have
an high DC gain in order to increment the total open loop gain increasing the bandwidth too.

3.4 Error amplifier and sense amplifier

As explained before the gain of these two blocks is:

Bx

= ACerrdB + ACsense

dB

Being the voltage across the sense resistor the input of the Bx block and the error amplifier
voltage the output of the same, the voltage gain is given by:

dB

ib Vsense Gs⋅ Vsense

19/32

1

------- -

⋅==

Rb

PWM current control loop L6258EA

1

1

------ -

Zc

------ -

Zc

because ib = icwe have:

Verr_out = -(ic · Zc) so ic = -(Verr_out · )

1

Vsense · = -(Verr_out · )

------- -

Rb

Bx

In the case of no external RC network is used to compensate the error amplifier, the typical
open loop transfer function of the error plus the sense amplifier is something with a gain
around 80dB and a unity gain bandwidth at 400kHz. In this case the situation of the total
transfer function Aloop, given by the sum of the Ax

Figure 8. Aloop bode plot (uncompensated)

Verr_out

----------------------- -–

Vsense

Zc

------- -–==

Rb

and BxdB is:

dB

The BODE diagram shows together the error amplifier open loop transfer function, the Ax
function and the resultant total Aloop given by the following equation:

Aloop

The total Aloop has an high DC gain of 78.1dB with a bandwidth of 15KHz, but the problem
in this case is the stability of the system; in fact the total Aloop cross the zero dB axis with a
slope of -40dB/decade.

Now it is necessary to compensate the error amplifier in order to obtain a total Aloop with an
high DC gain and a large bandwidth. Aloop must have enough phase margin to guarantee
the stability of the system.

A method to reach the stability of the system, using the RC network showed in the block
diagram, is to cancel the load pole with the zero given by the compensation of the error
amplifier.

The transfer function of the Bx block with the compensation on the error amplifier is:

20/32

= AxdB + Bx

dB

dB

L6258EA PWM current control loop

1

------------------------------

–

Rc j

Bx

Zc

------- -–

Rb

--------------------------------------------- -–==

2π fCc⋅⋅

Rb

In this case the Bx block has a DC gain equal to the open loop and equal to zero at a
frequency given by the following formula:

Fzero

1

------------------------------------=

2π Rc Cc⋅⋅

In order to cancel the pole of the load, the zero of the Bx block must be located at the same
frequency of 163Hz; so now we have to find a compromise between the resistor and the
capacitor of the compensation network.

Considering that the resistor value defines the gain of the Bx block at the zero frequency, it
is clear that this parameter will influence the total bandwidth of the system because,
annulling the load pole with the error amplifier zero, the slope of the total transfer function is

-20dB/decade.

So the resistor value must be chosen in order to have an error amplifier gain enough to
guarantee a desired total bandwidth.

In our example we fix at 35dB the gain of the Bx block at zero frequency, so from the
formula:

Rc

------- -

log⋅=

Rb

where: Rb = 20kΩ

Bx_gain

@ zero freq.

20

we have: Rc = 1.1MΩ

Therefore we have the zero with a 163Hz the capacitor value:

Cc

---------------------------------------------

2π Fzero Rc⋅⋅

1

---------------------------------------------------------------- - 880pF== =
6,28 163 1,1 10

⋅⋅⋅

1

6–

Now we have to analyse how the new Aloop transfer function with a compensation network
on the error amplifier is.

The following bode diagram shows:

– the Ax function showing the position of the load pole
– the open loop transfer function of the Bx block
– the transfer function of the Bx with the RC compensation network on the error

amplifier

– the total Aloop transfer function that is the sum of the Ax function plus the transfer

function of the compensated Bx block.

21/32

PWM current control loop L6258EA

Figure 9. Aloop bode plot (compensated)

We can see that the effect of the load pole is cancelled by the zero of the Bx block ; the total
Aloop cross a the 0dB axis with a slope of -20dB/decade, having in this way a stable system
with an high gain at low frequency and a bandwidth of around 8KHz.

To increase the bandwidth of the system, we should increase the gain of the Bx block,
keeping the zero in the same position. In this way the result is a shift of the total Aloop
transfer function up to a greater value.

3.5 Effect of the Bemf on the current control loop stability

In order to evaluate what is the effect of the Bemf voltage of the stepper motor we have to
look at the load block:

22/32

L6258EA PWM current control loop

Figure 10. Electrical model of the load

OUT+

Bemf

R

L

L

L

to Sense

Amplifier

OUT-

R

S

The schematic now shows the equivalent circuit of the stepper motor including a sine wave
voltage generator of the Bemf. The Bemf voltage of the motor is not constant, its value
changes depending on the speed of the motor.

Increasing the motor speed the Bemf voltage increases:
Bemf = Kt · ω

where:

Kt is the motor constant
ω is the motor speed in radiant per second

The formula defining the gain of the load considering the Bemf of the stepper motor
becomes:

R

S

----------------------

⋅

RLRS+

V

S

R

S

----------------------

RLRS+

ACload

Vsense

---------------------

Vout

Acload

VSBemf–()

--------------------------------------------------------------- -==

VSBemf–

---------------------------- -

V

⋅=

S

ACload

dB

20

VSBemf–

⎛⎞

---------------------------- -

log⋅=

⎜⎟

V

⎝⎠

S

----------------------

⋅

RLRS+

R

S

we can see that the Bemf influences only the gain of the load block and does not introduce
any other additional pole or zero, so from the stability point of view the effect of the Bemf of
the motor is not critical because the phase margin remains the same.
Practically the only effect of the Bemf is to limit the gain of the total Aloop with a consequent
variation of the bandwidth of the system.

23/32

Application information L6258EA

4 Application information

A typical application circuit is shown in Figure 11.

Note: For avoid current spikes on falling edge of DISABLE a "DC feedback" would be added to the

ERROR Amplifier. (R1-R2 on Figure 11).

4.1 Interference

Due to the fact that the circuit operates with switch mode current regulation, to reduce the
effect of the wiring inductance a good capacitor (100nF) can be placed on the board near
the package, between the power supply line (pin 13,31) and the power ground (pin
1,36,18,19) to absorb the small amount of inductive energy.
It should be noted that this capacitor is usually required in addition to an electrolytic
capacitor, that has poor performance at the high frequencies, always located near the
package, between power supply voltage (pin 13,31) and power ground (pin 1,36,18,19), just
to have a current recirculation path during the fast current decay or during the phase
change.
The range value of this capacitor is between few µF and 100µF, and it must be chosen
depending on application parameters like the motor inductance and load current amplitude.
A decoupling capacitor of 100nF is suggested also between the logic supply and ground.

The EA_IN1 and EA_IN2 pins carry out high impedance lines and care must be taken to
avoid coupled noise on this signals. The suggestion is to put the components connected to
this pins close to the L6258, to surround them with ground tracks and to keep as far as
possible fast switching outputs of the device. Remember also an 1 Mohm resistor between
EA_INx and EA_OUTx to avoid output current spike during supply startup/shutdown.
A non inductive resistor is the best way to implement the sensing. Whether this is not
possible, some metal film resistor of the same value can be paralleled.
The two inputs for the sensing of the winding motor current (SENSE_A & SENSE_B) should
be connected directly on the sensing resistor Rs terminals, and the path lead between the
Rs and the two sensing inputs should be as short as possible.

Note: Connect the DISABLE pin to a low impedance (< 300

minimum the interference on the output current due to capacitive coupling of OUT1A (pin5)
and DISABLE (pin 6).

Ω

) voltage source to reduce at

24/32

L6258EA Application information

Figure 11. Typical application circuit

VS

10nF

100nF

1nF

VCP1

VCP2

VBOOT

TRI_CAP

I0_1

I1_1

I2_1

I3_1

PH2

I0_2

I1_2

I2_2

I3_2

DISABLE

VS

EA_IN1

10

11

12

13,31

7

2

4

3

32

33

17

15

16

23

22

6

OUT2B

SENSE2

OUT2A

SENSE1

OUT1B

OUT1APH1

GND

PWR_GND

V

DD

SIG_GND

VREF1

VREF2

0.33

0.33

D97IN626E

M

VDD(5V)

VREF

STEPPER

MOTOR

12mH 10Ω

21

20

14

35

34

820pF

1,36

18,19

5

9

8

27

28

26

24

L6258EA

SOP36

PACKAGE

29

1M

EA_OUT1

820pF

30

EA_IN2

25

EA_OUT2

1M

R2 1MR1 1M

4.2 Motor selection

Some stepper motor have such high core losses that they are not suitable for switch mode
current regulation. Furthermore, some stepper motors are not designed for continuous
operating at maximum current. Since the circuit can drive a constant current through the
motor, its temperature might exceed, both at low and high speed operation.

25/32

Application information L6258EA

4.3 Notes on PCB design

We recommend to observe the following layout rules to avoid application problems with
ground and anomalous recirculation current.
The by-pass capacitors for the power and logic supply must be kept as near as possible to
the IC.
It's important to separate on the PCB board the logic and power grounds and the internal
charge pump circuit ground avoiding that ground traces of the logic signals cross the ground
traces of the power signals.
Because the IC uses the board as a heat sink, the dissipating copper area must be sized in
accordance with the required value of R

thj-amb

.

26/32

L6258EA Operation mode time diagrams

5 Operation mode time diagrams

Figure 12. Full step operation mode timing diagram

(Phase - DAC input and motor current)

Position

Phase

1

Phase

2

DAC 1

Inputs

DAC 2

Inputs

Motor drive

Current 1

Motor drive

Current 2

I0_1

I1_1

I2_1

I3_1

I0_2

I1_2

I2_2

I3_2

5V

0

5V

0

5V

0

5V

0

5V

0

5V

0

5V

0

5V

0

5V

0

023103210

Ph2

FULL Step Vector

Ph1

1

Ph1

I3 I2 I1 I0

0

Ph2

32

Current

level% of I

0000 100
0001 98.4
0010 95.2
0011 92.1
0100 88.9

MAX

0101 82.5

0

95.2%

19.1%

0

0110 77.8
0111 71.4
1000 63.5
1001 55.6
1010 47.6

95.2%

19.1%

0

D97IN629A

1011 38.1
1100 28.6
1101 19.1
1110 9.5
1 1 1 1 No Current

27/32

Operation mode time diagrams L6258EA

Figure 13. Half step operation mode timing diagram

(Phase - DAC input and motor current)

67451320

I0_1

I1_1

I2_1

I3_1

I0_2

I1_2

I2_2

I3_2

5V

5V

5V

5V

5V

5V

5V

5V

5V

5V

100%

71.4%

-71.4%

-100%

100%

71.4%

-71.4%

-100%

0

0

Half Step Vector

Ph1

0

0

0

0

0

0

0

0

Ph2

3

4

5

I3 I2 I1 I0

2

6

Ph1

1

7

Current

level% of I

0

MAX

Ph2

0000 100

0

0001 98.4
0010 95.2
0011 92.1
0100 88.9
0101 82.5
0110 77.8
0111 71.4
1000 63.5
1001 55.6
1010 47.6

0

1011 38.1
1100 28.6
1101 19.1
1110 9.5

D97IN627C

1111 No Current

Phase 1

Phase 2

DAC 1
Inputs

DAC 2

Inputs

Motor drive

Current 1

Motor drive

Current 2

28/32

L6258EA Operation mode time diagrams

Figure 14. 4 bit microstep operation mode timing diagram

(Phase - DAC input and motor current)

Position

Phase

1

Phase

2

I0_1

I1_1

DAC 1
Inputs

I2_1

I3_1

I0_2

DAC 2
Inputs

I1_2

I2_2

I3_2

Motor drive

Current 1

Motor drive

Current 2

0

4

8

12

16

5V

0

5V

0

5V

0

5V

0

5V

0

5V

0

5V

0

5V

0

5V

0

20

36

40

44

48

52

24

28

32

56

60

64

Micro Step Vector

Ph1

16

8

Ph2

0

56

Ph2

24

32

40

48

Ph1

I3 I2 I1 I0

Current

level% of I

MAX

0000 100
0001 98.4
0010 95.2
0011 92.1

0

100%

95.2%

82.5%

63.5%

47.6%

38.1%

0

19.1%

0100 88.9
0101 82.5
0110 77.8
0111 71.4
1000 63.5

0%

1001 55.6
1010 47.6
1011 38.1
1100 28.6
1101 19.1

0

1110 9.5
1111 No Current

D97IN628A

29/32

Package information L6258EA

6 Package information

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

Figure 15. PowerSO36 mechanical data & package dimensions

DIM.

A 3.60 0.1417

a1 0.10 0.30 0.0039 0.0118

a2 3.30 0.1299

a3 0 0.10 0.0039

b 0.22 0.38 0.0087 0.0150

c 0.23 0.32 0.0091 0.0126

D 15.80 16.00 0.6220 0.6299

D1 9.40 9.80 0.3701 0.3858

E 13.90 14.5 0.5472 0.5709

E1 10.90 11.10 0.4291 0.4370

E2 2.90 0.1142

E3 5.80 6.20 0.2283 0.2441

e 0.65 0.0256

e3 11.05 0.4350

G 0 0.10 0.0039

H 15.50 15.90 0.6102 0.6260

h 1.10 0.0433

L 0.8 1.10 0.0315 0.0433

N 10˚ (max)

s 8˚ (max)

Note: “D and E1” do not include mold flash or protusions.

- Mold flash or protusions shall not exceed 0.15mm (0.006”)

- Critical dimensions are "a3", "E" and "G".

mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

OUTLINE AND

MECHANICAL DATA

PowerSO-36

30/32

0096119 C

L6258EA Revision history

7 Revision history

Table 7. Document revision history

Date Revision Changes

11-May-2004 1 First Issue

29-Jun-2004 2 Updated the table 1: Order Codes

24-Sep-2004 3

23-Mar-2005 4 Add. note at the bottom of Table 2: Absolute maximum rating.

03-Dec-2007 5

Changed on the page 5 the f

18.5kHz

Document reformatted.
Modified the ACpw formula in Section 3.2 on page 17.
Added the disable note in Section 4.1 on page 24.

parameter max. value from 17.5 to

osc

31/32

L6258EA

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32/32