L6258EA
PWM controlled high current DMOS universal motor driver
Features
■Able to drive both windings of a bipolar stepper motor or two DC motors
■Output current up to 1.5A each winding
■Wide voltage range: 12V to 40V
■Four quadrant current control, ideal for microstepping and dc motor control
■Precision PWM control
■No need for recirculation diodes
■TTL/CMOS compatible inputs
■Cross conduction protection
■Thermal shutdow
■Extended low operating temperature range: -40°C
Description
L6258EA is a dual full bridge for motor control applications realized in BCD technology, with the capability of driving both windings of a bipolar stepper motor or bidirectionally control two DC motors.
L6258EA and a few external components form a complete control and drive circuit. It has high efficiency phase shift chopping that allows a very low current ripple at the lowest current control levels, and makes this device ideal for steppers as well as for DC motors.
PowerSO36
The power stage is a dual DMOS full bridge capable of sustaining up to 40V, and includes the diodes for current recirculation.The output current capability is 1.5A per winding in continuous mode, with peak start-up current up to 2A. A thermal protection circuitry disables the outputs if the chip temperature exceeds the safe limits.
Table 1. |
Device summary |
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Order code |
Package |
Packing |
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E-L6258EA |
PowerSO36 |
Tube |
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December 2007 |
Rev 5 |
1/32 |
www.st.com
Contents |
L6258EA |
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Contents
1 |
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2 |
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.1 |
Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.2 |
Input logic (I0 - I1 - I2 - I3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
12 |
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2.3 |
Phase input ( PH ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.4 |
Triangular generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.5 |
Charge pump circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.6 |
Current control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.7 |
Current control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
15 |
3 |
PWM current control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
16 |
3.1 Open loop transfer function analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 Power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 Load attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 Error amplifier and sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 Effect of the Bemf on the current control loop stability . . . . . . . . . . . . . . . 22
4 |
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
24 |
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4.1 |
Interference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
24 |
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4.2 |
Motor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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4.3 |
Notes on PCB design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
26 |
5 |
Operation mode time diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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6 |
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
30 |
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7 |
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
31 |
2/32
L6258EA |
List of tables |
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List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 3. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 5. Current levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 6. Charge pump capacitor's values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 7. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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List of figures |
L6258EA |
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List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Power bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Current control loop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. Output comparator waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7. Ax bode plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8. Aloop bode plot (uncompensated) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9. Aloop bode plot (compensated) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 10. Electrical model of the load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 11. Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 12. Full step operation mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 13. Half step operation mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 14. 4 bit microstep operation mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 15. PowerSO36 mechanical data & package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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L6258EA |
Block diagram |
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R1 1M |
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RC1 |
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CC1 |
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CBOOT |
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CP |
VCP2 |
EA_IN1 |
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EA_OUT1 |
VS |
VBOOT |
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TRI_0 |
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VCP1 |
CHARGE |
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C |
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OUT1A |
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PUMP |
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ERROR |
- |
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VR |
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POWER |
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+ |
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AMP |
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BRIDGE |
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VREF1 |
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1 |
OUT1B |
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INPUT |
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C |
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I3_1 |
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TRI_180 |
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SENSE1B |
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- |
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I2_1 |
DAC |
SENSE |
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Rs |
I1_1 |
AMP |
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I0_1 |
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PH_1 |
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SENSE1A |
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VDD(5V) |
VR GEN |
VR (VDD/2) |
THERMAL |
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DISABLE |
PROT. |
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VS |
VREF1 |
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ERROR |
TRI_0 |
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I3_2 |
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VR |
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OUT2A |
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INPUT |
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AMP |
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C |
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I2_2 |
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DAC |
& |
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POWER |
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I1_2 |
SENSE |
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BRIDGE |
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+ |
OUT2B |
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I0_2 |
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AMP |
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2 |
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- |
C |
SENSE2B |
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PH_2 |
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TRI_180 |
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TRI_CAP |
TRIANGLE |
TRI_0 |
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Rs |
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GENERATOR |
TRI_180 |
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CFREF |
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SENSE2A |
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GND |
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EA_IN2 |
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EA_OUT2 |
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D96IN430D |
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RC2 |
CC2 |
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R2 1M |
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Table 2. |
Absolute maximum rating |
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Parameter |
Description |
Value |
Unit |
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Vs |
Supply voltage |
45 |
V |
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VDD |
Logic supply voltage |
7 |
V |
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Vref1/Vref2 |
Reference voltage |
2.5 |
V |
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IO |
Output current (peak)(1) |
2 |
A |
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IO |
Output current (continuous) |
1.5 |
A |
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Vin |
Logic input voltage range |
-0.3 to 7 |
V |
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Vboot |
Bootstrap supply |
60 |
V |
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Vboot - Vs |
Maximum Vgate applicable |
15 |
V |
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Tj |
Junction temperature |
150 |
°C |
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Tstg |
Storage temperature range |
-55 to 150 |
°C |
1. This current is intended as not repetitive current for max. 1 second.
5/32
Block diagram |
L6258EA |
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Figure 2. |
Pin connection (top view) |
PWR_GND |
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1 |
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36 |
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PWR_GND |
PH_1 |
2 |
35 |
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SENSE1 |
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I1_1 |
3 |
34 |
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OUT1B |
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I0_1 |
4 |
33 |
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I3_1 |
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OUT1A |
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5 |
32 |
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I2_1 |
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DISABLE |
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6 |
31 |
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VS |
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TRI_CAP |
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7 |
30 |
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EA_OUT1 |
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VDD |
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29 |
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EA_IN1 |
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9 |
28 |
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GND |
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VREF1 |
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VCP1 |
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10 |
27 |
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SIG_GND |
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VCP2 |
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11 |
26 |
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VREF2 |
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VBOOT |
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12 |
25 |
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EA_IN2 |
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VS |
13 |
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EA_OUT2 |
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OUT2A |
14 |
23 |
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I2_2 |
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I0_2 |
15 |
22 |
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I3_2 |
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I1_2 |
16 |
21 |
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OUT2B |
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PH_2 |
17 |
20 |
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SENSE2 |
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PWR_GND |
18 |
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19 |
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PWR_GND |
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D96IN432F
Table 3. |
Pin functions |
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Pin # |
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Name |
Description |
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1, 36 |
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PWR_GND |
Ground connection (1). They also conduct heat from die to |
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printed circuit copper. |
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These TTL compatible logic inputs set the direction of |
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PH_1, PH_2 |
current flow through the load. A high level causes current to |
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flow from OUTPUT A to OUTPUT B. |
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Logic input of the internal DAC (1). The output voltage of the |
3 |
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I1_1 |
DAC is a percentage of the Vref voltage applied according to |
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the thruth Table 5 on page 12. |
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4 |
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I0_1 |
See pin 3 |
5 |
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OUT1A |
Bridge output connection (1) |
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6 |
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DISABLE |
Disables the bridges for additional safety during switching. |
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When not connected the bridges are enabled |
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7 |
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TRI_cap |
Triangular wave generation circuit capacitor. The value of |
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this capacitor defines the output switching frequency |
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6/32
L6258EA |
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Block diagram |
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Table 3. |
Pin functions (continued) |
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Name |
Description |
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8 |
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VDD (5V) |
Supply voltage input for logic circuitry |
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9 |
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GND |
Power ground connection of the internal charge pump circuit |
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10 |
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VCP1 |
Charge pump oscillator output |
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11 |
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VCP2 |
Input for external charge pump capacitor |
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12 |
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VBOOT |
Overvoltage input for driving of the upper DMOS |
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13, 31 |
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VS |
Supply voltage input for output stage. They are shorted |
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internally |
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14 |
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OUT2A |
Bridge output connection (2) |
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Logic input of the internal DAC (2). The output voltage of the |
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I0_2 |
DAC is a percentage of the VRef voltage applied according |
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to the truth Table 5 on page 12. |
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16 |
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I1_2 |
See pin 15 |
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18, 19 |
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PWR_GND |
Ground connection. They also conduct heat from die to |
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printed circuit copper |
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20, 35 |
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SENSE2, SENSE1 |
Negative input of the transconductance input amplifier (2, 1) |
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21 |
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OUT2B |
Bridge output connection and positive input of the |
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tranconductance (2) |
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22 |
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I3_2 |
See pin 15 |
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23 |
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I2_2 |
See pin 15 |
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24 |
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EA_OUT_2 |
Error amplifier output (2) |
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25 |
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EA_IN_2 |
Negative input of error amplifier (2) |
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Reference voltages for the internal DACs, determining the |
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VREF2, VREF1 |
output current value. Output current also depends on the |
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logic inputs of the DAC and on the sensing resistor value |
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27 |
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SIG_GND |
Signal ground connection |
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29 |
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EA_IN_1 |
Negative input of error amplifier (1) |
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30 |
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EA_OUT_1 |
Error amplifier output (1) |
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32 |
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I2_1 |
See pin 3 |
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33 |
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I3_1 |
See pin 3 |
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34 |
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OUT1B |
Bridge output connection and positive input of the |
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tranconductance (1) |
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Note: |
The number in parenthesis shows the relevant Power Bridge of the circuit. Pins 18, 19, 1 |
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and 36 are connected together. |
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7/32
Block diagram |
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L6258EA |
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Figure 3. Thermal characteristics |
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Conditions |
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Power Dissipated |
T Ambient |
Thermal J-A resistance |
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(W) |
(˚C) |
(˚C/W) |
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5.3 |
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pad |
layout + ground layers + 16 |
via hol |
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PCB ref.: 4 LAYER cm 12 x 12 |
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4.0 |
70 |
20 |
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pad layout + ground layers |
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PCB ref.: 4 LAYER cm 12 x 12 |
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2.3 |
70 |
35 |
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pad layout + 6cm2 on board heat sink |
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PCB ref.: 2 LAYER cm 12 x 12 |
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D02IN1370 |
Power Dissipated (W)
12
10
8 |
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15˚C/W |
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6 |
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20˚C/W |
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4 |
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35˚C/W |
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2 |
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0 |
-40 |
-20 |
0 |
20 |
40 |
60 |
80 |
100 |
120 |
140 |
160 |
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Ambient Temperature (˚C) |
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D04IN1525A |
Table 4. |
Electrical characteristics |
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(VS = 40V; VDD = 5V; Tj = 25°; unless otherwise specified.) |
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Parameter |
Description |
Test condition |
Min. |
Typ. |
Max. |
Unit |
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VS |
Supply voltage |
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12 |
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40 |
V |
VDD |
Logic supply voltage |
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4.75 |
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5.25 |
V |
VBOOT |
Storage voltage |
VS = 12 to 40V |
VS+6 |
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VS+12 |
V |
VSense |
Max drop across sense |
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1.25 |
V |
resistor |
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VS(off) |
Power off reset |
Off threshold |
6 |
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7.2 |
V |
VDD(off) |
Power off reset |
Off threshold |
3.3 |
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4.1 |
V |
IS(on) |
VS quiescent current |
Both bridges ON, no load |
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15 |
mA |
IS(off) |
VS quiescent current |
Both bridges OFF |
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7 |
mA |
IDD |
VDD operative current |
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15 |
mA |
8/32
L6258EA |
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Block diagram |
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Table 4. |
Electrical characteristics |
(continued) |
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(VS = 40V; VDD = 5V; Tj = 25°; unless otherwise specified.) |
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Parameter |
Description |
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Test condition |
Min. |
Typ. |
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Max. |
Unit |
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TSD-H |
Shut down hysteresis |
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25 |
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°C |
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TSD |
Thermal shutdown |
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150 |
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°C |
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fosc |
Triangular oscillator |
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CFREF = 1nF |
12.5 |
15 |
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18.5 |
KHz |
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frequency(1) |
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TRANSISTORS |
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IDSS |
Leakage current |
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OFF State |
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500 |
μA |
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Rds(on) |
On resistance |
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ON state |
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0.6 |
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0.75 |
W |
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Vf |
Flywheel diode voltage |
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If =1.0A |
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1 |
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1.4 |
V |
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CONTROL LOGIC |
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Vin(H) |
lnput voltage |
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All Inputs |
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2 |
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VDD |
V |
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Vin(L) |
Input voltage |
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All inputs |
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0 |
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0.8 |
V |
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Iin |
Input current (2) |
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0 < Vin < 5V |
-150 |
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+10 |
μA |
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Idis |
Disable pin input current |
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-10 |
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+150 |
μA |
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Vref1/ref2 |
Reference voltage |
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Operating |
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0 |
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(3) |
V |
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Iref |
Vref terminal input current |
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Vref = 1.25 |
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-2 |
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5 |
μA |
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FI = |
PWM loop transfer ratio |
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2 |
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Vref/Vsense |
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VFS |
DAC full scale precision |
Vref = 2.5V I0/I1/I2/I3 = L |
1.23 |
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1.34 |
V |
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Vref = 2.5V I0/I1/I2/I3 = H |
-30 |
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+30 |
mV |
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Voffset |
Current loop offset |
V |
ref |
= 2V I |
/I /I /I |
= H; |
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0 |
1 2 |
3 |
-60 |
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+60 |
mV |
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Tj = -40 to 125°C |
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DAC factor ratio |
Normalized @ full scale |
-2 |
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+2 |
% |
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value |
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SENSE AMPLIFIER |
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Vcm |
lnput common mode |
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-0.7 |
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VS+0.7 |
V |
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voltage range |
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Iinp |
Input bias |
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sense1/sense2 |
-200 |
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0 |
μA |
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ERROR AMPLIFIER |
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GV |
Open loop voltage gain |
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70 |
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dB |
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SR |
Output slew rate |
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Open loop |
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0.2 |
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V/μs |
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GBW |
Gain bandwidth product |
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400 |
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kHz |
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1.Chopping frequency is twice fosc value.
2.This is true for all the logic inputs except the disable input.
3.If Tj is inside the range -40 to -10°C then Vref max is 2V+0.5V·(Tj + 40°C)/30°C. If Tj is greater than -10°C then Vref max is 2.5V.
9/32
Functional description |
L6258EA |
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The circuit is intended to drive both windings of a bipolar stepper motor or two DC motors.
The current control is generated through a switch mode regulation.
With this system the direction and the amplitude of the load current are depending on the relation of phase and duty cycle between the two outputs of the current control loop.
The L6258EA power stage is composed by power DMOS in bridge configuration as it is shown in Figure 4, where the bridge outputs OUT_A and OUT_B are driven to Vs with an high level at the inputs IN_A and IN_B while are driven to ground with a low level at the same inputs.
The zero current condition is obtained by driving the two half bridge using signals IN_A and IN_B with the same phase and 50% of duty cycle.
In this case the outputs of the two half bridges are continuously switched between power supply (Vs) and ground, but keeping the differential voltage across the load equal to zero.
In Figure 4 is shown the timing diagram of the two outputs and the load current for this working condition.
Following we consider positive the current flowing into the load with a direction from OUT_A to OUT_B, while we consider negative the current flowing into load with a direction from OUT_B to OUT_A.
Now just increasing the duty cycle of the IN_A signal and decreasing the duty cycle of IN_B signal we drive positive current into the load.
In this way the two outputs are not in phase, and the current can flow into the load trough the diagonal bridge formed by T1 and T4 when the output OUT_A is driven to Vs and the output OUT_B is driven to ground, while there will be a current recirculation into the higher side of the bridge, through T1 and T2, when both the outputs are at Vs and a current recirculation into the lower side of the bridge, through T3 and T4, when both the outputs are connected to ground.
Since the voltage applied to the load for recirculation is low, the resulting current discharge time constant is higher than the current charging time constant during the period in which the current flows into the load through the diagonal bridge formed by T1 and T4. In this way the load current will be positive with an average amplitude depending on the difference in duty cycle of the two driving signals.
In Figure 4 is shown the timing diagram in the case of positive load current
On the contrary, if we want to drive negative current into the load is necessary to decrease the duty cycle of the IN_A signal and increase the duty cycle of the IN_B signal. In this way we obtain a phase shift between the two outputs such to have current flowing into the diagonal bridge formed by T2 and T3 when the output OUT_A is driven to ground and output OUT_B is driven to Vs, while we will have the same current recirculation conditions of the previous case when both the outputs are driven to Vs or to ground.
So, in this case the load current will be negative with an average amplitude always depending by the difference in duty cycle of the two driving signals.
In Figure 4 is shown the timing diagram in the case of negative load current.
Figure 5 shows the device block diagram of the complete current control loop.
10/32