Features
■ 1 A DC output current
■ 2.9 V to 18 V input voltage
■ Output voltage adjustable from 0.6 V
■ 250 kHz switching frequency, programmable
up to 1 MHz
■ Internal soft-start and inhibit
■ Low dropout operation: 100 % duty cycle
■ Voltage feed-forward
■ Zero load current operation
■ Overcurrent and thermal protection
■ VFQFPN8 3 mm x 3 mm package
Applications
■ Consumer: STB, DVD, DVD recorder, car
audio, LCD TV and monitors
■ Industrial: chargers, PLD, PLA, FPGA
■ Networking: XDSL, modems, DC-DC modules
■ Computer: optical storage, hard disk drive,
printers, audio/graphic cards
■ LED driving
Figure 1. Application circuit
L5981
1 A step-down switching regulator
VFQFPN8 3 mm x 3 mm
Description
The L5981 is step-down switching regulator with
1.5 A (min.) current limited embedded power
MOSFET, so it is able to deliver in excess of 1 A
DC current to the load depending on the
application condition.
The input voltage can range from 2.9 V to 18 V,
while the output voltage can be set starting from
0.6 V to V
2.9 V, the device is suitable also for 3.3 V bus.
Requiring a minimum set of external components,
the device includes an internal 250 kHz switching
frequency oscillator that can be externally
adjusted up to 1 MHz.
The VFQFPN8 package with exposed pad allows
reducing the R
60 °C/W.
. Having a minimum input voltage of
IN
down to approximately
thJA
June 2009 Doc ID 13004 Rev 6 1/37
www.st.com
37
Contents L5981
Contents
1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 Error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4 Over-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5 Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.6 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4.1 Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.4.2 Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.5 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.6 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.7 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2/37 Doc ID 13004 Rev 6
L5981 Pin settings
1 Pin settings
1.1 Pin connection
Figure 2. Pin connection (top view)
OUT
1.2 Pin description
OUT
SYNCH
SYNCH
INH
INH
COMP
COMP
V
V
CC
CC
GND
GND
FSW
FSW
FB
FB
Table 1. Pin description
Pin n° Type Description
1 OUT Regulator output
Master/slave synchronization. When it is left floating, a signal with a
phase shift of half a period respect to the power turn on is present at the
pin. When connected to an external signal at a frequency higher than the
2 SYNCH
3INH
4 COMP Error amplifier output to be used for loop frequency compensation
5FB
6F
SW
7 GND Ground
8VCCUnregulated DC input voltage
internal one, then the device is synchronized by the external signal, with
zero phase shift.
Connecting together the SYNCH pin of two devices, the one with higher
frequency works as master and the other one as slave; so the two
powers turn on have a phase shift of half a period.
A logical signal (active high) disable the device. With INH higher than
1.9 V the device is OFF and with INH lower than 0.6 V the device is ON.
Feedback input. Connecting the output voltage directly to this pin the
output voltage is regulated at 0.6 V. To have higher regulated voltages an
external resistor divider is required from Vout to FB pin.
The switching frequency can be increased connecting an external
resistor from FSW pin and ground. If this pin is left floating the device
works at its free-running frequency of 250 kHz.
Doc ID 13004 Rev 6 3/37
Maximum ratings L5981
2 Maximum ratings
2.1 Absolute maximum ratings
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
Vcc Input voltage 20
OUT Output DC voltage -0.3 to V
FSW, COMP, SYNCH Analog pin -0.3 to 4
INH Inhibit pin -0.3 to V
FB Feedback voltage -0.3 to 1.5
CC
V
CC
P
TOT
T
J
T
stg
2.2 Thermal data
Table 3. Thermal data
Symbol Parameter Value Unit
R
thJA
1. Package mounted on demonstration board.
Power dissipation at TA < 60 °C 1.5. W
Junction temperature range -40 to 150 °C
Storage temperature range -55 to 150 °C
Maximum thermal resistance
junction-ambient
(1)
VFQFPN 60 °C/W
4/37 Doc ID 13004 Rev 6
L5981 Electrical characteristics
3 Electrical characteristics
TJ = 25 °C, V
= 12 V, unless otherwise specified.
CC
Table 4. Electrical characteristics
Val ues
Symbol Parameter Test condition
Min Typ Max
V
CC
V
CCON
V
CCHYSVCC
R
DS(on)
I
LIM
Operating input voltage
range
Turn on VCC threshold
UVLO hysteresis
MOSFET on resistance
Maximum limiting current 1.5 1.8 2.1 A
Oscillator
V
F
FSW
SW
Switching frequency
FSW pin voltage 1.254 V
D Duty cycle 0 100 %
F
ADJ
Adjustable switching
frequency
(1)
(1)
(1)
2.9 18
0.175 0.3
140 170
(1)
140 220
225 250 275
(1)
R
= 33 kΩ 1000 kHz
FSW
220 275
2.9
Unit
V
mΩ
kHz
Dynamic characteristics
V
FB
Feedback voltage 2.9 V < V
CC
< 18 V
(1)
0.593 0.6 0.607 V
DC characteristics
I
Q
I
QST-BY
Quiescent current
Total stand-by quiescent
current
Duty cycle = 0,
= 0.8 V
V
FB
20 30 μA
2.4 mA
Inhibit
Device ON level 0.6
INH threshold voltage
V
Device OFF level 1.9
INH current INH = 0 7.5 10 μA
Soft-start
T
SS
Soft-start duration
FSW pin floating 7.4 8.2 9.1
= 1 MHz,
F
R
SW
FSW
= 33 kΩ
2
ms
Doc ID 13004 Rev 6 5/37
Electrical characteristics L5981
Table 4. Electrical characteristics (continued)
Val ues
Symbol Parameter Test condition
Min Typ Max
Error amplifier
Unit
V
CH
V
CL
I
FB
I
O SOURCE
I
O SINK
G
V
High level output voltage V
Low level output voltage V
Bias source current V
Source COMP pin V
Sink COMP pin V
Open loop voltage gain
< 0.6 V 3
FB
> 0.6 V 0.1
FB
= 0 V to 0.8 V 1 μA
FB
FB
FB
(2)
= 0.5 V, V
= 0.7 V, V
=1 V 20 mA
COMP
=1 V 25 mA
COMP
100 dB
Synchronization function
High input voltage 2 3.3
Low input voltage 1
Slave sink current V
Master output amplitude I
SOURCE
= 2.9 V 0.7 0.9 mA
SYNCH
= 4.5 mA 2.0 V
Output pulse width SYNCH floating 110
Input pulse width 70
Protection
I
FBDISC
FB disconnection source
current
1 μA
Thermal shutdown 150
T
SHDN
1. Specification refered to TJ from -40 to +125 °C. Specification in the -40 to +125 °C temperature range are
assured by design, characterization and statistical correlation.
2. Guaranteed by design.
Hystereris 30
V
V
ns
°C
6/37 Doc ID 13004 Rev 6
L5981 Functional description
4 Functional description
The L5981 is based on a “voltage mode”, constant frequency control. The output voltage
V
is sensed by the feedback pin (FB) compared to an internal reference (0.6 V) providing
OUT
an error signal that, compared to a fixed frequency sawtooth, controls the on and off time of
the power switch.
The main internal blocks are shown in the block diagram in Figure 3. They are:
● A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the
synchronization signal. Its switching frequency can be adjusted by and external
resistor. The voltage and frequency feed forward are implemented.
● The soft-start circuitry to limit inrush current during the start up phase.
● The voltage mode error amplifier
● The pulse width modulator and the relative logic circuitry necessary to drive the internal
power switch.
● The high-side driver for embedded p-channel power MOSFET switch.
● The peak current limit sensing block, to handle over load and short circuit conditions.
● A voltage regulator and internal reference. It supplies internal circuitry and provides a
fixed internal reference.
● A voltage monitor circuitry (UVLO) that checks the input and internal voltages.
● A thermal shutdown block, to prevent thermal run away.
Figure 3. Block diagram
Doc ID 13004 Rev 6 7/37
Functional description L5981
4.1 Oscillator and synchronization
Figure 4 shows the block diagram of the oscillator circuit. The internal oscillator provides a
constant frequency clock. Its frequency depends on the resistor externally connect to FSW
pin. In case the FSW pin is left floating the frequency is 250 kHz; it can be increased as
shown in Figure 6 by external resistor connected to ground.
To improve the line transient performance keeping the PWM gain constant versus the input
voltage, the voltage feed forward is implemented by changing the slope of the sawtooth
according to the input voltage change (see Figure 5.a).
The slope of the sawtooth also changes if the oscillator frequency is increased by the
external resistor. In this way a frequency feed forward is implemented (Figure 5.b) in order to
keep the PWM gain constant versus the switching frequency (see Section 5.4 for PWM gain
expression).
On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of
180° with respect to the clock. This delay is useful when two devices are synchronized
connecting the SYNCH pin together. When SYNCH pins are connected, the device with
higher oscillator frequency works as master, so the slave device switches at the frequency
of the Master but with a delay of half a period. This minimizes the RMS current flowing
through the input capacitor [see L5988D data sheet].
Figure 4. Oscillator circuit block diagram
Clock
ClockClock
FSW
FSW
Clock
Clock
Generator
Generator
Synchronization
Synchronization
Ramp
Ramp
Generator
Generator
SYNCH
SYNCH
Sawtooth
Sawtooth
The device can be synchronized to work at higher frequency feeding an external clock
signal. The synchronization changes the sawtooth amplitude, changing the PWM gain
(Figure 5.c). This changing has to be taken into account when the loop stability is studied.
To minimize the change of the PWM gain, the free running frequency should be set (with a
resistor on FSW pin) only slightly lower than the external clock frequency. This pre-adjusting
of the frequency will change the sawtooth slope in order to get negligible the truncation of
sawtooth, due to the external synchronization.
8/37 Doc ID 13004 Rev 6
L5981 Functional description
Figure 5. Sawtooth: voltage and frequency feed forward; external synchronization
Figure 6. Oscillator frequency versus FSW pin resistor
Doc ID 13004 Rev 6 9/37
Functional description L5981
4.2 Soft-start
The soft-start is essential to assure correct and safe start up of the step-down converter. It
avoids inrush current surge and makes the output voltage increases monothonically.
The soft-start is performed by a staircase ramp on the non-inverting input (V
) of the error
REF
amplifier. So the output voltage slew rate is:
Equation 1
R1
⎛⎞
⋅=
VREF
⎝⎠
1
------- -+
R2
where SR
SR
is the slew rate of the non-inverting input while R1 and R2 the resistor divider
VREF
OUT
SR
to regulate the output voltage (see Figure 7). The soft-start stair case consists of 64 steps of
9.5 mV each one, from 0 V to 0.6 V. The time base of one step is of 32 clock cycles. So the
soft-start time and then the output voltage slew rate depend on the switching frequency.
Figure 7. Soft-start scheme
Soft-start time results:
Equation 2
For example with a switching frequency of 250 kHz the SS
10/37 Doc ID 13004 Rev 6
SS
TIME
32 64⋅
-----------------=
Fsw
TIME
is 8 ms.
L5981 Functional description
4.3 Error amplifier and compensation
The error amplifier (E/A) provides the error signal to be compared with the sawtooth to
perform the pulse width modulation. Its non-inverting input is internally connected to a 0.6 V
voltage reference, while its inverting input (FB) and output (COMP) are externally available
for feedback and frequency compensation. In this device the error amplifier is a voltage
mode operational amplifier so with high DC gain and low output impedance.
The uncompensated error amplifier characteristics are the following:
Table 5. Uncompensated error amplifier characteristics
Error amplifier Value
Low frequency gain 100 dB
GBWP 4.5 MHz
Slew rate 7 V/μs
Output voltage swing 0 to 3.3 V
Maximum source/sink current 25 mA/40 mA
In continuos conduction mode (CCM), the transfer function of the power section has two
poles due to the LC filter and one zero due to the ESR of the output capacitor. Different
kinds of compensation networks can be used depending on the ESR value of the output
capacitor. In case the zero introduced by the output capacitor helps to compensate the
double pole of the LC filter a type II compensation network can be used. Otherwise, a type
III compensation network has to be used (see Chapter 5.4 for details about the
compensation network selection).
Anyway the methodology to compensate the loop is to introduce zeros to obtain a safe
phase margin.
Doc ID 13004 Rev 6 11/37
Functional description L5981
4.4 Overcurrent protection
The L5981 implements the over current protection sensing current flowing through the
power MOSFET. Due to the noise created by the switching activity of the power MOSFET,
the current sensing is disabled during the initial phase of the conduction time. This avoids an
erroneous detection of a fault condition. This interval is generally known as “masking time”
or “blanking time”. The masking time is about 200 ns.
When the over current is detected, two different behaviors are possible depending on the
operating condition.
1. Output voltage in regulation. When the over current is sensed, the power MOSFET is
switched off and the internal reference (V
error amplifier, is set to zero and kept in this condition for a soft-start time (T
clock cycles). After this time, a new soft-start phase takes place and the internal
reference begins ramping (see Figure 8.a).
2. Soft-start phase. If the over current limit is reached the power MOSFET is turned off
implementing the pulse by pulse over current protection. During the soft-start phase,
under over current condition, the device can skip pulses in order to keep the output
current constant and equal to the current limit. If at the end of the "masking time" the
current is higher than the over current threshold, the power MOSFET is turned off and it
will skip one pulse. If, at the next switching on at the end of the "masking time" the
current is still higher than the threshold, the device will skip two pulses. This
mechanism is repeated and the device can skip up to seven pulses. While, if at the end
of the "masking time" the current is lower than the over current threshold, the number of
skipped cycles is decreased of one unit. At the end of soft-start phase the output
voltage is in regulation and if the over current persists the behavior explained above
takes place. (see Figure 8.b)
), that biases the non-inverting input of the
REF
SS
, 2048
So the over current protection can be summarized as an “hiccup” intervention when the
output is in regulation and a constant current during the soft-start phase. If the output is
shorted to ground when the output voltage is on regulation, the over current is triggered and
the device starts cycling with a period of 2048 clock cycles between “hiccup” (power
MOSFET off and no current to the load) and “constant current” with very short on-time and
with reduced switching frequency (up to one eighth of normal switching frequency). See
Figure 32. for short circuit behavior.
12/37 Doc ID 13004 Rev 6
L5981 Functional description
Figure 8. Overcurrent protection strategy
4.5 Inhibit function
The inhibit feature allows to put in stand-by mode the device.With INH pin higher than 1.9 V
the device is disabled and the power consumption is reduced to less than 30 μA. With INH
pin lower than 0.6 V, the device is enabled. If the INH pin is left floating, an internal pull up
ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled.
The pin is also VCC compatible.
4.6 Hysteretic thermal shutdown
The thermal shutdown block generates a signal that turns off the power stage if the junction
temperature goes above 150 °C. Once the junction temperature goes back to about 130 °C,
the device restarts in normal operation. The sensing element is very close to the PDMOS
area, so ensuring an accurate and fast temperature detection.
Doc ID 13004 Rev 6 13/37
Application information L5981
5 Application information
5.1 Input capacitor selection
The capacitor connected to the input has to be capable to support the maximum input
operating voltage and the maximum RMS input current required by the device. The input
capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR,
affecting the overall system efficiency.
So the input capacitor must have a RMS current rating higher than the maximum RMS input
current and an ESR value compliant with the expected efficiency.
The maximum RMS input current flowing through the capacitor can be calculated as:
Equation 3
2
D
------ -+⋅=
η2
2
⋅
2D
I
RMSIO
-------------- -–
D
η
Where Io is the maximum DC output current, D is the duty cycle, η is the efficiency.
Considering
η = 1, This function has a maximum at D = 0.5 and it is equal to Io/2.
In a specific application the range of possible duty cycles has to be considered in order to
find out the maximum RMS input current. The maximum and minimum duty cycles can be
calculated as:
Equation 4
V
+
OUTVF
D
MAX
------------------------------------ -=
V
–
INMINVSW
and
Equation 5
V
+
OUTVF
--------------------------------------=
V
–
INMAXVSW
Where V
D
MIN
is the forward voltage on the freewheeling diode and VSW is voltage drop across
F
the internal PDMOS. In Ta b l e 6 some multi layer ceramic capacitors suitable for this device
are reported
Table 6. Input MLCC capacitors
Manufacturer Series Cap value (μF) Rated voltage (V)
MURATA
TDK C3225 10 25
GRM31 10 25
GRM55 10 25
14/37 Doc ID 13004 Rev 6
L5981 Application information
5.2 Inductor selection
The inductance value fixes the current ripple flowing through the output capacitor. So the
minimum inductance value in order to have the expected current ripple has to be selected.
The rule to fix the current ripple value is to have a ripple at 20 % - 40 % of the output current.
In the continuos current mode (CCM), the inductance value can be calculated by the
following equation:
Equation 6
VINV
ΔI
L
–
OUT
----------------------------- -
L
T
⋅
ON
V
+
OUTVF
--------------------------- -
L
T
⋅==
OFF
Where T
time of the external diode (in CCM, F
fixed Vout, is obtained at maximum T
to calculate minimum duty). So fixing ΔI
is the conduction time of the internal high side switch and T
ON
= 1 / (TON + T
SW
that is at minimum duty cycle (see previous section
OFF
= 20 % to 40 % of the maximum output current, the
L
)). The maximum current ripple, at
OFF
is the conduction
OFF
minimum inductance value can be calculated:
Equation 7
+
1D
–
---------------------- -
⋅=
F
).
OFF
MIN
SW
= 250 kHz the minimum
SW
where F
For example for V
is the switching frequency, 1/(TON + T
SW
= 3.3 V, V
OUT
inductance value to have ΔI
V
OUTVF
L
IN
= 30 % of IO is about 31 μH.
L
--------------------------- -
MIN
ΔI
MAX
= 12 V, IO = 1 A and F
The peak current through the inductor is given by:
Equation 8
ΔI
I
LPK,
L
I
--------+=
O
2
So if the inductor value decreases, the peak current (that has to be lower than the current
limit of the device) increases. The higher is the inductor value, the higher is the average
output current that can be delivered, without reaching the current limit.
In the table below some inductor part numbers are listed.
Table 7. Inductors
Manufacturer Series Inductor value (μH) Saturation current (A)
Wurth PD M 10 to 18 1.7 to 2.2
Coilcraft
Coiltronics
SUMIDA
MSS1038 22 to 47 1.9 to 2.9
LPS6235 10 to 18 1.8 to 2.4
DRQ73 10 to 22 1.67 to 2.47
LD2 27 to 47 1.64 to 2.1
CDR6D28MN 10 to 22 1.65 to 2.5
CDRH105RNP 27 to 56 1.9 to 2.7
Doc ID 13004 Rev 6 15/37
Application information L5981
5.3 Output capacitor selection
The current in the capacitor has a triangular waveform which generates a voltage ripple
across it. This ripple is due to the capacitive component (charge and discharge of the output
capacitor) and the resistive component (due to the voltage drop across its ESR). So the
output capacitor has to be selected in order to have a voltage ripple compliant with the
application requirements.
The amount of the voltage ripple can be calculated starting from the current ripple obtained
by the inductor selection.
Equation 9
ΔI
MAX
ΔV
OUT
ESR ΔI
⋅
Usually the resistive component of the ripple is much higher than the capacitive one, if the
output capacitor adopted is not a multi layer ceramic capacitor (MLCC) with very low ESR
value.
The output capacitor is important also for loop stability: it fixes the double LC filter pole and
the zero due to its ESR. In Chapter 5.4, it will be illustrated how to consider its effect in the
system stability.
MAX
------------------------------------ -+=
8C
⋅⋅
OUTfSW
For example with V
order to have a ΔV
OUT
OUT
= 3.3 V, V
= 0.01·V
= 12 V, ΔIL = 0.3 A (resulting by the inductor value), in
IN
, if the multi layer capacitor are adopted, 10 μF are
OUT
needed and the ESR effect on the output voltage ripple can be neglected. In case of not
negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into
account its ESR value.
So in case of 100 μF with ESR = 40 μF, the resistive component of the drop dominates and
the voltage ripple is 12 mV.
The output capacitor is also important to sustain the output voltage when a load transient
with high slew rate is required by the load. When the load transient slew rate exceeds the
system bandwidth the output capacitor provides the current to the load. So if the high slew
rate load transient is required by the application the output capacitor and system bandwidth
have to be chosen in order to sustain the load transient .
In the table below some capacitor series are listed.
Table 8. Output capacitors
Manufacturer Series Cap value (μF) Rated voltage (V) ESR (mΩ)
MURATA
PANASONIC
GRM32 22 to 100 6.3 to 25 < 5
GRM31 10 to 47 6.3 to 25 < 5
ECJ 10 to 22 6.3 < 5
EEFCD 10 to 68 6.3 15 to 55
SANYO TPA/B/C 100 to 470 4 to 16 40 to 80
TDK C3225 22 to 100 6.3 < 5
16/37 Doc ID 13004 Rev 6
L5981 Application information
5.4 Compensation network
The compensation network has to assure stability and good dynamic performance. The loop
of the L5981 is based on the voltage mode control. The error amplifier is a voltage
operational amplifier with high bandwidth. So selecting the compensation network the E/A
will be considered as ideal, that is, its bandwidth is much larger than the system one.
The transfer functions of PWM modulator and the output LC filter are studied (see Figure 9).
The transfer function of the PWM modulator, from the error amplifier output (COMP pin) to
the OUT pin, results:
Equation 10
V
G
PW0
IN
-------- -=
V
s
where V
is the sawtooth amplitude. As seen in Chapter 4.1, the voltage feed forward
S
generates a sawtooth amplitude directly proportional to the input voltage, that is:
Equation 11
V
KVIN⋅=
S
In this way the PWM modulator gain results constant and equals to:
Equation 12
V
1
IN
-------- -
G
PW0
V
s
--- - 9===
K
The synchronization of the device with an external clock provided trough SYNCH pin can
modifies the PWM modulator gain (see Chapter 4.1 to understand how this gain changes
and how to keep it constant in spite of the external synchronization).
Figure 9. The error amplifier, the PWM modulator and the LC output filter
V
V
CC
CC
V
V
S
S
V
V
REF
REF
FB
FB
E/A
E/A
COMP
COMP
PWM
PWM
OUT
OUT
L
L
ESR
ESR
G
G
PW0
PW0
G
G
LC
LC
C
C
OUT
OUT
The transfer function on the LC filter is given by:
Doc ID 13004 Rev 6 17/37
Application information L5981
Equation 13
GLCs()
1
------------------------------------------------------------------------ -=
1
----------------------------
++
2π Qf⋅LC⋅
s
s
------------------------- -+
2π f
⋅
zESR
⎛⎞
-------------------
⎝⎠
2π f
2
s
⋅
LC
where:
Equation 14
f
----------------------------------------------------------------------- -= f
LC
2π LC
1
⋅ 1
OUT
ESR
-------------- -+⋅⋅
R
OUT
zESR
------------------------------------------- -=,
2π ESR C
1
⋅⋅
OUT
Equation 15
R
LC
Q
LC
OUT
------------------------------------------------------------------------------------------
OUTROUT
OUTROUT
ESR+()⋅⋅ ⋅
ESR⋅⋅+
R
OUT
V
--------------=,=
I
OUT
OUT
As seen in Chapter 4.3 two different kind of network can compensate the loop. In the two
following paragraph the guidelines to select the type II and type III compensation network
are illustrated.
5.4.1 Type III compensation network
The methodology to stabilize the loop consists of placing two zeros to compensate the effect
of the LC double pole, so increasing phase margin; then to place one pole in the origin to
minimize the dc error on regulated output voltage; finally to place other poles far away the
zero dB frequency.
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a
frequency higher than the desired bandwidth (that is: 2π * ESR * COUT < 1 / BW), the type
III compensation network is needed. Multi Layer Ceramic capacitors (MLCC) have very low
ESR (<1 mΩ), with very high frequency zero, so type III network is adopted to compensate
the loop.
In Figure 10 the type III compensation network is shown. This network introduces two zeros
(f
, fZ2) and three poles (fP0, fP1, fP2). They expression are:
Z1
Equation 16
f
Z1
------------------------------------------------= f
2π C
1
+()⋅⋅
3R1R3
Z2
----------------------------- -=,
⋅⋅
2π R
1
4C4
18/37 Doc ID 13004 Rev 6
L5981 Application information
Equation 17
1
f
0= f
P0
----------------------------- -= f
P1
⋅⋅
2π R
3C3
P2
------------------------------------------- -=,,
2π R
1
C4C5⋅
--------------------
⋅⋅
4
C
+
4C5
Figure 10. Type III compensation network
In Figure 11 the Bode diagram of the PWM and LC filter transfer function (G
and the open loop gain (G
LOOP
(f)=G
· GLC(f) · G
PW0
(f)) are drawn.
TYPEIII
PW0
· GLC(f))
Figure 11. Open loop gain: module Bode diagram
The guidelines for positioning the poles and the zeroes and for calculating the component
values can be summarized as follow:
1. Choose a value for R
2. Choose a gain (R
, usually between 1 k and 5 k.
1
) in order to have the required bandwidth (BW), that means:
4/R1
Doc ID 13004 Rev 6 19/37
Application information L5981
Equation 18
BW K⋅
------------------
R
4
⋅=
R
f
LC
1
where K is the feed forward constant and 1 / K is equals to 9.
3. Calculate C
by placing the zero at 50 % of the output filter double pole frequency (fLC):
4
Equation 19
1
---------------------------=
C
4
⋅⋅
π R
4fLC
4. Calculate C
by placing the second pole at four times the system bandwidth (BW):
5
Equation 20
C
C
------------------------------------------------------------- -=
5
2π R4C44BW⋅ 1–⋅⋅⋅
4
5. Set also the first pole at four times the system bandwidth and also the second zero at
the output filter double pole:
Equation 21
R
R
3
1
-------------------------- -= C
4BW⋅
----------------- 1–
f
LC
3
1
---------------------------------------- -=,
2π R34BW⋅⋅⋅
The suggested maximum system bandwidth is equals to the switching frequency divided by
3.5 (F
For example with V
/ 3.5), anyway lower than 100 kHz if the FSW is set higher than 500 kHz.
SW
OUT
= 3.3 V, V
= 12 V, IO = 1 A, L =33 μH, C
IN
= 22 μF, E S R < 1 m Ω,
OUT
the type III compensation network is:
4.99k Ω= R21.1kΩ= R3110Ω= R45.6kΩ= C34.7nF= C410nF= C5100pF=,,,,,,
R
1
In Figure 12 is shown the module and phase of the open loop gain. The bandwidth is about
56 kHz and the phase margin is 53 °.
20/37 Doc ID 13004 Rev 6
L5981 Application information
Figure 12. Open loop gain Bode diagram with ceramic output capacitor
Doc ID 13004 Rev 6 21/37
Application information L5981
5.4.2 Type II compensation network
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a
frequency lower than the desired bandwidth (that is: 2π * ESR * COUT > 1 / BW), this zero
helps stabilize the loop. Electrolytic capacitors show not negligible ESR (> 30 mΩ), so with
this kind of output capacitor the type II network combined with the zero of the ESR allows
stabilizing the loop.
In Figure 13 the type II network is shown.
Figure 13. Type II compensation network
The singularity of the network are:
f
Z1
⋅⋅
2π R
4C4
P0
0= f
P1
------------------------------------------- -=,,
2π R
1
----------------------------- -= f
In Figure 14 the Bode diagram of the PWM and LC filter transfer function (G
and the open loop gain (G
LOOP
(f) = G
· GLC(f) · G
PW0
TYPEII
1
C4C5⋅
--------------------
⋅⋅
4
+
C
4C5
(f)) are drawn.
PW0
· GLC(f))
22/37 Doc ID 13004 Rev 6
L5981 Application information
Figure 14. Open loop gain: module Bode diagram
The guidelines for positioning the poles and the zeroes and for calculating the component
values can be summarized as follow:
1. Choose a value for R
, usually between 1 k and 5 k, in order to have values of C4 and
1
C5 not comparable with parasitic capacitance of the board.
2. Choose a gain (R
) in order to have the required bandwidth (BW), that means:
4/R1
Equation 22
Where f
is the ESR zero:
ESR
R
4
2
f
ESR
⎛⎞
----------- -
⎝⎠
⋅⋅⋅=
f
LC
BW
----------- -
f
ESR
V
-------- -
V
IN
S
R
1
Equation 23
f
ESR
------------------------------------------- -=
2π ESR C
1
⋅⋅
OUT
and Vs is the saw-tooth amplitude. The voltage feed forward keeps the ratio Vs/Vin constant.
3. Calculate C
by placing the zero one decade below the output filter double pole:
4
Equation 24
------------------------------ -=
⋅⋅
2π R
10
4fLC
C
4
4. Then calculate C
in order to place the second pole at four times the system bandwidth
3
(BW):
Doc ID 13004 Rev 6 23/37
Application information L5981
Equation 25
C
------------------------------------------------------------- -=
C
5
2π R4C44BW⋅ 1–⋅⋅⋅
4
For example with V
OUT
= 3.3 V, V
= 12 V, IO = 1 A, L = 33 μH, C
IN
OUT
= 220 μF,
ESR = 100 mΩ, the type II compensation network is:
R
1.1kΩ= R2249Ω= R410k Ω= C410nF= C5100pF=,,,,
1
In Figure 15 is shown the module and phase of the open loop gain. The bandwidth is about
33 kHz and the phase margin is 46°.
24/37 Doc ID 13004 Rev 6
L5981 Application information
Figure 15. Open loop gain Bode diagram with electrolytic/tantalum output capacitor
Doc ID 13004 Rev 6 25/37
Application information L5981
5.5 Thermal considerations
The thermal design is important to prevent the thermal shutdown of device if junction
temperature goes above 150 °C. The three different sources of losses within the device are:
a) conduction losses due to the not negligible R
equal to:
Equation 26
of the power switch; these are
DS(on)
P
ONRDS on()IOUT
Where D is the duty cycle of the application and the maximum R
the duty cycle is theoretically given by the ratio between V
()2D⋅⋅=
is 220 mΩ. Note that
DSON
an VIN, but actually it is quite
OUT
higher to compensate the losses of the regulator. So the conduction losses increases
compared with the ideal case.
b) switching losses due to power MOSFET turn ON and OFF; these can be
calculated as:
Equation 27
T
+()
RISETFALL
Where T
RISE
P
SWVINIOUT
and T
FAL L
------------------------------------------ -
2
are the overlap times of the voltage across the power switch (VDS)
Fsw⋅⋅ ⋅ V
⋅⋅⋅==
INIOUTTSWFSW
and the current flowing into it during turn ON and turn OFF phases, as shown in Figure 16.
T
is the equivalent switching time. For this device the typical value for the equivalent
SW
switching time is 50 ns.
c) Quiescent current losses, calculated as:
Equation 28
where I
The junction temperature T
is the quiescent current (IQ = 2.4 mA).
Q
can be calculated as:
J
Equation 29
T
Where T
Rth
is the ambient temperature and P
A
is the equivalent thermal resistance junction to ambient of the device; it can be
JA
calculated as the parallel of many paths of heat conduction from the junction to the ambient.
For this device the path through the exposed pad is the one conducting the largest amount
26/37 Doc ID 13004 Rev 6
P
JTA
QVINIQ
⋅=
RthJAP
⋅+=
TOT
is the sum of the power losses just seen.
TOT
L5981 Application information
of heat. The R
measured on the demonstration board described in the following
thJA
paragraph is about 60 °/W.
Figure 16. Switching losses
5.6 Layout considerations
The PC board layout of switching DC/DC regulator is very important to minimize the noise
injected in high impedance nodes and interferences generated by the high switching current
loops.
In a step-down converter the input loop (including the input capacitor, the power MOSFET
and the free wheeling diode) is the most critical one. This is due to the fact that the high
value pulsed current are flowing through it. In order to minimize the EMI, this loop has to be
as short as possible.
The feedback pin (FB) connection to external resistor divider is a high impedance node, so
the interferences can be minimized placing the routing of feedback node as far as possible
from the high current paths. To reduce the pick up noise the resistor divider has to be placed
very close to the device.
To filter the high frequency noise, a small capacitor (100 nF) can be added as close as
possible to the input voltage pin of the device.
To filter the high frequency noise, a small capacitor can be added as close as possible to the
input voltage pin of the device.
Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal
resistance junction to ambient; so a large ground plane enhances the thermal performance
of the converter allowing high power conversion.
In Figure 17 a layout example is shown.
Doc ID 13004 Rev 6 27/37
Application information L5981
Figure 17. Layout example
28/37 Doc ID 13004 Rev 6
L5981 Application information
5.7 Application circuit
In Figure 18 the demonstration board application circuit is shown.
Figure 18. Demonstration board application circuit
L1 15uH
VIN=3.3V to 18V
VIN=3.3V to 18V
VIN=3.3V to 18V
VIN=3.3V to 18V
C1
C1
C1
C1
10uF
10uF
10uF
10uF
C6
C6
C6
C6
68nF
68nF
68nF
68nF
VCC
VCC
VCC
VCC
INH
INH
INH
INH
GND
GND
GND
GND
8
8
8
8
3
3
3
3
7
7
7
7
FSW
FSW
FSW
FSW
R5 100K
R5 100K
6
6
6
6
L5985
L5981
L5985
L5981
COMP
COMP
COMP
COMP
COMP
COMP
COMP
COMP
4
4
4
4
1
1
1
1
1
1
1
1
2
2
2
2
5
5
5
5
R4 3.9K
R4 3.9K
C5 150pF
C5 150pF
OUT
OUT
OUT
OUT
SYNCH
SYNCH
SYNCH
SYNCH
FB
FB
FB
FB
C4 10nF
C4 10nF
C4 10nF
C4 10nF
L1 15uH
D1
D1
D1
D1
STPS2L25U
STPS2L25U
STPS2L25U
STPS2L25U
R1 4.99K
R1 4.99K
R1 4.99K
R1 4.99K
R2 1.1K
R2 1.1K
R2 1.1K
R2 1.1K
Vout=3.3V
Vout=3.3V
Vout=3.3V
Vout=3.3V
C2
C2
C2
C2
22uF
22uF
22uF
22uF
C3 3.3nFR3 180
C3 3.3nFR3 180
Table 9. Component list
Reference Part number Description Manufacturer
C1 GRM31CR61E106KA12 10 μF, 25 V MURATA
C2 GRM32ER61E226KE15 22 μF, 25 V MURATA
C3 3.3 nF, 50 V
C4 10 nF, 50 V
C5 150 pF, 50 V
C6 68 nF, 25 V
R1 4.99 kΩ, 1 %, 0.1 W 0603
R2 1.1 kΩ, 1 %, 0.1 W 0603
R3 180 Ω, 1 %, 0.1 W 0603
R4 3.9 kΩ, 1 %, 0.1 W 0603
R5 100 kΩ, 1 %, 0.1 W 0603
D1 STPS2L25V 2 A, 25 V STMicroelectronics
L1 7447779115 15 μH, 20 %, 2.2 A Wurth elektronik
Doc ID 13004 Rev 6 29/37
Application information L5981
Figure 19. PCB layout (component side)
Figure 20. PCB layout (bottom side)
Figure 21. PCB layout (front side)
30/37 Doc ID 13004 Rev 6
L5981 Application information
V
Figure 22. Junction temperature vs output
current
Figure 24. Junction temperature vs output
current
Figure 23. Junction temperature vs output
current
Figure 25. Efficiency vs output current
95
90
85
80
Efficiency [%]
75
70
0.1 0.2 0.3 0.4 0.5 0. 6 0.7 0.8 0.9 1.0
VCC=12V
=250KHz
F
SW
Io [A]
Vo=5.0V
o=3.3V
Vo=2.5V
Figure 26. Efficiency vs output current Figure 27. Efficiency vs output current
94
92
90
88
86
84
82
Efficien c y [% ]
80
78
76
0.1 0.2 0.3 0. 4 0.5 0.6 0.7 0.8 0.9 1
VCC=5V
F
=250KHz
SW
Io [A]
Vo=3.3V
Vo=2.5V
Vo=1.8V
95
90
85
80
75
Efficie n c y [% ]
70
65
0.1 0.2 0 .3 0.4 0.5 0.6 0.7 0.8 0.9 1
VCC=3.3V
=250KHz
F
SW
Io [A]
Doc ID 13004 Rev 6 31/37
Vo=2.5V
Vo=1.8V
Vo=1.2V
Application information L5981
Figure 28. Load regulation Figure 29. Line regulation
0.3
=250KHz
F
SW
0.25
=12V
V
0.2
[%]
FB
0.15
/V
FB
V
0.1
Δ
0.05
0
0 0.2 0.4 0.6 0.8 1
VCC=3.3V
CC
V
=5.0V
CC
Io [A]
Figure 30. Load transient: from 0.2 A to 1 A Figure 31. Soft-start
V
V
OUT
OUT
100mV/div
100mV/div
AC coupled
AC coupled
0.4
0.35
0.3
0.25
0.2
0.15
0.1
VFB/VFB [%]
Δ
0.05
0
2 4 6 8 10 12 14 16 18
-0.05
VCC [V]
Io=1A
V
V
OUT
OUT
500mV/div
500mV/div
C
C
L=15μH
L=15μH
F
I
I
L
L
200mA/div
200mA/div
Figure 32. Short circuit behavior
OUT
OUT
10V/div
10V/div
OUTPUT
OUTPUT
SHORTED
SHORTED
V
V
OUT
OUT
1V/div
1V/div
Time base 100μs/div
Time base 100μs/div
Load slew rate 2.5A/μs
Load slew rate 2.5A/μs
I
I
L
L
500mA/div
500mA/div
F
Time base 5ms/div
Time base 5ms/div
=47μF
=47μF
OUT
OUT
=520KHz
=520KHz
SW
SW
I
I
L
L
500mA/div
500mA/div
Time base 1ms/div
Time base 1ms/div
V
V
FB
FB
200mV/div
200mV/div
32/37 Doc ID 13004 Rev 6
L5981 Package mechanical data
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Doc ID 13004 Rev 6 33/37
Package mechanical data L5981
Table 10. VFQFPN8 (3 x 3 x 1.08 mm) mechanical data
mm inch
Dim.
Min Typ Max Min Typ Max
A 0.80 0.90 1.00 0.0315 0.0354 0.0394
A1 0.02 0.05 0.0008 0.0020
A2 0.70 0.0276
A3 0.20 0.0079
b 0.18 0.23 0.30 0.0071 0.0091 0.0118
D 2.95 3.00 3.05 0.1161 0.1181 0.1200
D2 2.23 2.38 2.48 0.0878 0.0937 0.0976
E 2.95 3.00 3.05 0.1161 0.1181 0.1200
E2 1.65 1.70 1.75 0.0587 0.0646 0.0685
e0.50 0.0197
L 0.30 0.40 0.50 0.0118 0.0157 0.0197
ddd 0.08 0.0031
Figure 33. Package dimensions
34/37 Doc ID 13004 Rev 6
L5981 Order codes
7 Order codes
Table 11. Order codes
Order codes Package Packaging
L5981
L5981TR Tube and reel
VFQFPN8
(3 x 3 x 1.08 mm)
Tube
Doc ID 13004 Rev 6 35/37
Revision history L5981
8 Revision history
Table 12. Document revision history
Date Revision Changes
21-Dec-2006 1 Initial release
16-Oct-2007 2 Document status promoted from preliminary data to datasheet
Updated: Cover page, Figure 2 on page 3, Figure 8 on page 13,
27-May-2008 3
09-Sep-2008 4 Updated: Table 4 on page 5
27-Jan-2009 5 Updated: Equation 18
15-Jun-2009 6 Updated Table 4 on page 5 and Figure 6 on page 9
Figure 5 on page 9, Figure 17 on page 28, Figure 18 on page 29,
Table 8 on page 16, Table 10 on page 34
Added: Table 3 on page 4
36/37 Doc ID 13004 Rev 6
L5981
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Doc ID 13004 Rev 6 37/37
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