2 A switch step down switching regulator
Features
■ 2 A internal switch
■ Operating input voltage from 4 V to 36 V
■ 3.3 V / (±2%) reference voltage
■ Output voltage adjustable from 1.235 V to 35 V
■ Low dropout operation: 100% duty cycle
■ 500 kHz Internally fixed frequency
■ Voltage feedforward
■ Zero load current operation
■ Internal current limiting
■ Inhibit for zero current consumption
■ Synchronization
■ Protection against feedback disconnection
■ Thermal shutdown
Applications
■ Consumer: STB, DVD, TV, VCR, car radio,
LCD monitors
■ Networking: XDSL, modems, DC-DC modules
■ Computer: printers, audio/graphic cards,
optical storage, hard disk drive
■ Industrial: chargers, car battery, DC-DC
converters
Figure 1. Test application circuit
VREF
VIN = 4V to 35V
C1
10μF
35V
CERAMIC
3.3V
C4
22nF
C3
220pF
SYNC.
COMP
VCC
R3
4.7K
6
8
L5973AD
2
4
3
L5973AD
HSOP8 exposed pad
Description
The L5973AD is a step down monolithic power
switching regulator with a switch current limit of
2 A so it is able to deliver more than 1.5 A DC
current to the load depending on the application
conditions.
The output voltage can be set from 1.235 V
to 35 V. The high current level is also achieved
thanks to an SO8 package with exposed frame,
that allows to reduce the R
approximately 40 °C/W.
The device uses an internal P-Channel D-MOS
transistor (with a typical of 200 mΩ) as switching
element to avoid the use of bootstrap capacitor
and guarantee high efficiency.
An internal oscillator fixes the switching frequency
at 500 kHz to minimize the size of external
components.
Having a minimum input voltage of 4 V only, it is
particularly suitable for 5 V bus, available in all
computer related applications.
Pulse by pulse current limit with the internal
frequency modulation offers an effective constant
current short circuit protection.
L1 15μH
OUT
1
D1
STPS340U
5
7
FB
GNDINH
R1
5.6K
R2
3.3K
down to
thJA
VOUT=3.3V
C2
330μF
10V
D03IN1453
November 2009 Doc ID 9552 Rev 9 1/22
www.st.com
22
Contents L5973AD
Contents
1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Voltages monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.3 Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.4 Current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.5 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.6 PWM comparator and power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.7 Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.8 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Additional features and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2 Output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3 Zero load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8 Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/22 Doc ID 9552 Rev 9
L5973AD Pin settings
1 Pin settings
1.1 Pin connection
Figure 2. Pin connection (top view)
COMP
1.2 Pin description
Table 1. Pin description
N° Type Description
1 OUT Regulator output.
2 SYNC
3INH
4 COMP E/A output to be used for frequency compensation.
OUT
SYNC
INH
1
2
3
4
D98IN955
Master/slave synchronization. When it is open, a signal synchronous with the
turn-off of the internal power is present at the pin. When connected to an
external signal at a frequency higher than the internal one, then the device is
synchronized by the external signal.
Connecting together the SYNC pin of two devices, the one with the higher
frequency works as master and the other one, works as slave.
A logical signal (active high) disables the device. With IHN higher than 2.2 V
the device is OFF and with INH lower than 0.8V, the device is ON.
If INH is not used the pin must be grounded. When it is open, an internal pullup disables the device.
8
7
6
5
VCC
GND
VREF
FB
Stepdown feedback input. Connecting the output voltage directly to this pin
5FB
6 VREF Reference voltage of 3.3 V. No filter capacitor is needed to stability.
7 GND Ground.
8 VCC Unregulated DC input voltage.
results in an output voltage of 1.235 V. An external resistor divider is required
for higher output voltages (the typical value for the resistor connected
between this pin and ground is 4.7 K).
Doc ID 9552 Rev 9 3/22
Electrical data L5973AD
2 Electrical data
2.1 Maximum ratings
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
V
8
V
1
I
1
V
, V
4
V
3
V
2
P
TOT
T
J
T
STG
Input voltage 40 V
Output DC voltage
Output peak voltage at t = 0.1 μs
-1 to 40
-5 to 40
Maximum output current int. limit.
Analog pins 4 V
5
INH -0.3V to V
SYNC -0.3 to 4 V
Power dissipation at TA ≤ 60 °C 2.25 W
Operating junction temperature range -40 to 150 °C
Storage temperature range -55 to 150 °C
V
V
CC
2.2 Thermal data
Table 3. Thermal data
Symbol Parameter
R
thJA
1. Package mounted on board
Maximum thermal resistance junction-ambient
HSOP8
Exposed pad
(1)
40
Unit
°C/W
4/22 Doc ID 9552 Rev 9
L5973AD Electrical characteristics
3 Electrical characteristics
TJ = 25 °C, VCC = 12 V, unless otherwise specified
Table 4. Electrical characteristics
Symbol Parameter Test condition Min Typ Max Unit
V
CC
Operating input voltage
range
Vo = 1.235 V; Io = 2 A
436V
R
DS(on)
I
l
f
s
MOSFET on
resistance
Maximum limiting
current
Switching frequency 500 kHz
Duty cycle 0 100 %
Dynamic characteristics (see test circuit).
V
5
η
Voltage feedback
Efficiency
DC characteristics
I
qop
I
I
qst-by
q
Total operating
quiescent current
Quiescent current
Total stand-by
quiescent current
Inhibit
VCC = 4.4 V to 36 V
4.4 V < VCC < 36 V,
20 mA < I
= 5 V, VCC = 12 V
V
O
< 2 A
O
Duty cycle = 0;
V
= 1.5 V
FB
V
> 2.2 V
inh
0.250 0.5 Ω
22.33.5A
1.220 1.235 1.25 V
90 %
57mA
2.7 mA
50 100 μA
Error amplifier
V
OH
V
OL
I
o source
I
o sink
I
b
INH threshold voltage
Device ON 0.8 V
Device OFF 2.2 V
High level output
voltage
Low level output
voltage
Source output current
Sink output current
VFB = 1 V 3.5 V
VFB = 1.5 V 0.4 V
= 1.9 V;
V
COMP
V
FB
V
COMP
V
FB
= 1 V
= 1.9 V;
= 1.5 V
200 300 μA
11.5 mA
Source bias current 2.5 4 μA
R
DC open loop gain
= ∞ 50 57 dB
L
Doc ID 9552 Rev 9 5/22
Electrical characteristics L5973AD
Table 4. Electrical characteristics (continued)
Symbol Parameter Test condition Min Typ Max Unit
I
= -0.1 mA to
comp
gm Transconductance
Sync function
0.1mA
V
COMP
= 1.9 V
2.3 mS
High input voltage
Low input voltage
Slave sink current
Master output
amplitude
Output pulse width
Reference section
Reference voltage 3.234 3.3 3.366 V
Line regulation
Load regulation
Short circuit current 10 18 30 mA
1. Guaranteed by design.
= 4.4 V to 36 V 2.5 V
V
CC
V
= 4.4 V to 36 V 0.74 V
CC
V
= 0.74 V
sync
V
= 2.33 V
sync
= 3 mA
I
source
no load, V
I
= 0 to 5 mA
REF
= 4.4 V to 36 V
V
CC
I
= 0 mA
REF
= 4.4 V to 36 V
V
CC
= 0 to 5 mA 8 15 mV
I
REF
(1)
= 1.65 V 0.20 0.35 μs
sync
0.11
0.21
2.75 3 V
3.2 3.3 3.399 V
510mV
REF
0.25
0.45mAmA
V
6/22 Doc ID 9552 Rev 9
L5973AD Functional description
4 Functional description
The main internal blocks are shown in Figure 3, where is reported the device block diagram.
They are:
● A voltage regulator that supplies the internal circuitry. From this regulator, a 3.3 V
reference voltage is externally available.
● A voltage monitor circuit that checks the input and internal voltages.
● A fully integrated sawtooth oscillator whose frequency is 500 kHz
● Two embedded current limitations circuitries which control the current that flows
through the power switch. The Pulse by Pulse Current Limit forces the power switch
OFF cycle by cycle if the current reaches an internal threshold, while the Frequency
Shifter reduces the switching frequency in order to strongly reduce the duty cycle.
● A transconductance error amplifier.
● A pulse width modulator (PWM) comparator and the relative logic circuitry necessary to
drive the internal power.
● An high side driver for the internal P-MOS switch.
● An inhibit block for stand-by operation.
● A circuit to realize the thermal protection function.
Figure 3. Block diagram
Doc ID 9552 Rev 9 7/22
Functional description L5973AD
4.1 Power supply and voltage reference
The internal regulator circuit (shown in Figure 4) consists of a start-up circuit, an internal
voltage pre-regulator, the Bandgap voltage reference and the Bias block that provides
current to all the blocks.
The Starter gives the start-up currents to the whole device when the input voltage goes high
and the device is enabled (inhibit pin connected to ground).
The pre-regulator block supplies the Bandgap cell with a pre-regulated voltage V
has a very low supply voltage noise sensitivity.
4.2 Voltages monitor
An internal block senses continuously the VCC, V
their thresholds, the regulator starts to work. There is also an hysteresis on the V
Figure 4. Internal regulator circuit
STARTER
that
REG
and Vbg. If the voltages go higher than
ref
V
CC
PREREGULATOR
VREG
BANDGAP
IC BIAS
(UVLO).
CC
D00IN1126
4.3 Oscillator and synchronization
Figure 5 shows the block diagram of the oscillator circuit.
The clock generator provides the switching frequency of the device that is internally fixed at
500 kHz. The frequency shifter block acts reducing the switching frequency in case of strong
overcurrent or short circuit. The clock signal is then used in the internal logic circuitry and is
the input of the ramp generator and synchronization blocks.
The ramp generator circuit provides the sawtooth signal, used to realize the PWM control
and the internal voltage feed forward, while the Synchronization circuit generates the
synchronization signal. In fact the device has a synchronization pin that can works both as
Master and Slave.
As Master to synchronize external devices to the internal switching frequency.
As Slave to synchronize itself by external signal.
8/22 Doc ID 9552 Rev 9
VREF
L5973AD Functional description
In particular, connecting together two devices, the one with the lower switching frequency
works as Slave and the other one works as Master.
To synchronize the device, the SYNC pin has to pass from a low level to a level higher than
the synchronization threshold with a duty cycle that can vary approximately from 10% to
90%, depending also on the signal frequency and amplitude.
The frequency of the synchronization signal must be at least higher than the internal
switching frequency of the device (500 kHz).
Figure 5. Oscillator circuit
FREQUENCY
SHIFTER
Ibias_osc
CLOCK
t
CLOCK
GENERATOR
D00IN1131
4.4 Current protection
The L5973AD has two current limit protections, pulse by pulse and frequency fold back.
The schematic of the current limitation circuitry for the pulse by pulse protection is shown in
Figure 6.
The output power PDMOS transistor is split in two parallel PDMOS. The smallest one has a
resistor in series, R
threshold, the mirror is unbalanced and the PDMOS is switched off until the next falling edge
of the internal clock pulse.
Due to this reduction of the ON time, the output voltage decreases.
Since the minimum switch ON time (necessary to avoid false overcurrent signal) is not
enough to obtain a sufficiently low duty cycle at 500 kHz, the output current, in strong
overcurrent or short circuit conditions, could increase again. For this reason the switching
frequency is also reduced, so keeping the inductor current under its maximum threshold.
The Frequency Shifter (see Figure 5) depends on the feedback voltage. As the feedback
voltage decreases (due to the reduced duty cycle), the switching frequency decreases too.
. The current is sensed through Rsense and if reaches the
SENSE
RAMP
GENERATOR
SYNCHRONIZATOR
RAMP
SYNC
Doc ID 9552 Rev 9 9/22
Functional description L5973AD
Figure 6. Current limitation circuitry
VCC
DRIVER
OUT
A1/A2=95
4.5 Error amplifier
The voltage error amplifier is the core of the loop regulation. It is a transconductance
operational amplifier whose non inverting input is connected to the internal voltage
reference (1.235 V), while the inverting input (FB) is connected to the external divider or
directly to the output voltage. The output (COMP) is connected to the external compensation
network.
The uncompensated error amplifier has the following characteristics:
I
OFF
PWM
RSENSE
A1
A2
II
RTH
I
NOT
D00IN1134
L
Table 5. Uncompensated error amplifier
Transconductance 2300 μS
Low frequency gain 65 dB
Minimum sink/source voltage 1500 μA/300 μA
Output voltage swing 0.4 V/3.65 V
Input bias current 2.5 μA
The error amplifier output is compared with the oscillator sawtooth to perform PWM control.
10/22 Doc ID 9552 Rev 9
L5973AD Functional description
4.6 PWM comparator and power stage
This block compares the oscillator sawtooth and the error amplifier output signals
generating the PWM signal for the driving stage. The power stage is a very critical block
cause it has to guarantee a correct turn on and turn OFF of the PDMOS. The turn ON of the
power element, or better, the rise time of the current at turn on, is a very critical parameter to
compromise.
At a first approach, it looks like the faster it is the rise time, the lower are the turn on losses.
But there is a limit introduced by the recovery time of the recirculation diode. In fact when the
current of the power element equals the inductor current, the diode turns off and the drain of
the power is free to go high. But during its recovery time, the diode can be considered as an
high value capacitor and this produces a very high peak current, responsible of many
problems:
● Spikes on the device supply voltage that cause oscillations (and thus noise) due to the
board parasitic.
● Turn ON overcurrent causing a decrease of the efficiency and system reliability.
● Big EMI problems.
● Shorter freewheeling diode life.
The fall time of the current during the turn off is also critical. In fact it produces voltage
spikes (due to the parasites elements of the board) that increase the voltage drop across the
PDMOS.
In order to minimize all these problems, a new topology of driving circuit has been used and
its block diagram is shown in Figure 7.
The basic idea is to change the current levels used to turn on and off the power switch,
according with the PDMOS status and with the gate clamp status.
This circuitry allow to turn off and on quickly the power switch and to manage the above
question related to the freewheeling diode recovery time problem.
The gate clamp is necessary to avoid that Vgs of the internal switch goes higher than
Vgsmax. The ON/OFF Control block avoids any cross conduction between the supply line
and ground.
Doc ID 9552 Rev 9 11/22
Functional description L5973AD
Figure 7. Driving circuitry
VCC
Vgs
max
I
OFF
CLAMP
STOP
ON/OFF
DRIVE
DRAIN
D00IN1133
CONTROL
4.7 Inhibit function
The inhibit feature allows to put in stand-by mode the device. With INH pin higher than 2.2 V
the device is disabled and the power consumption is reduced to less than 100 μA. With INH
pin lower than 0.8 V, the device is enabled. If the INH pin is left floating, an internal pull up
ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled.
The pin is also Vcc compatible.
4.8 Thermal shutdown
GATE
OFF
ON
DRAIN
I
ON
PDMOS
L
ESR
C
VOUT
I
LOAD
The shutdown block generates a signal that turns off the power stage if the temperature of
the chip goes higher than a fixed internal threshold (150 °C). The sensing element of the
chip is very close to the PDMOS area, so ensuring an accurate and fast temperature
detection. An hysteresis of approximately 20 °C avoids that the devices turns on and off
continuously
12/22 Doc ID 9552 Rev 9
L5973AD Additional features and protections
5 Additional features and protections
5.1 Feedback disconnection
In case of feedback disconnection, the duty cycle increases versus the maximum allowed
value, bringing the output voltage close to the input supply. This condition could destroy the
load.
To avoid this dangerous condition, the device is turned off if the feedback pin remains
floating.
5.2 Output overvoltage protection
The overvoltage protection, OVP, is realized by using an internal comparator, which input is
connected to the feedback, that turns off the power stage when the OVP threshold is
reached. This threshold is typically 30% higher than the feedback voltage.
When a voltage divider is requested for adjusting the output voltage (see test application
circuit), the OVP intervention will be set at:
Equation 1
R1R2+
V
OVP
1.3
--------------------
⋅⋅=
R
V
2
FB
Where R
R
is between the feedback pin and ground.
2
is the resistor connected between the output voltage and the feedback pin, while
1
5.3 Zero load
Due to the fact that the internal power is a PDMOS, no boostrap capacitor is required and
so, the device works properly also with no load at the output. In this condition it works in
burst mode, with random repetition rate of the burst.
5.4 Application circuit
In Figure 8 is shown the demo board application circuit, where the input supply voltage,
V
, can range from 4 V to 25 V due to the rated voltage of the input capacitor and the
CC
output voltage is adjustable from 1.235 V to V
CC
.
Doc ID 9552 Rev 9 13/22
Additional features and protections L5973AD
Figure 8. Demo board application circuit
VIN = 4V to 25V
C1
10μF
25V
CERAMIC
3.3V
C4
22nF
C3
220pF
VREF
VCC
SYNC.
COMP
R3
4.7K
6
8
L5973AD
2
4
OUT
1
7
5
FB
GNDINH
D03IN1454
3
L1 15μH
D1
STPS2L25U
R1
5.6K
R2
3.3K
Table 6. Component List
Reference Part Number Description Manufacturer
C1 GRM32DR61E106KA12L 10 μF, 25 V MURATA
C2 POSCAP 6TPB330M 330 μF, 6.3 V Sanyo
C3 C1206C221J5GAC 220 pF, 5%, 50 V KEMET
C4 C1206C223K5RAC 22 nF, 10%, 50 V KEMET
R1 5.6 K, 1%, 0.1 W 0603 Neohm
R2 3.3 K, 1%, 0.1 W 0603 Neohm
VOUT=3.3V
C2
330μF
6.3V
R3 4.7 K, 1%, 0.1 W 0603 Neohm
D1 STPS2L25U 2 A, 25 V ST
L1 DO3316P-153 15 μH, 3 A COILCRAFT
14/22 Doc ID 9552 Rev 9
L5973AD Additional features and protections
V
V
Figure 9. Junction temperature vs output
Tj (° C)
Tj (° C)
100
100
90
90
80
80
70
70
60
60
50
50
40
40
30
30
20
20
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Figure 11. Efficiency vs output current Figure 12. Efficiency vs output current
95
95
90
90
85
85
80
80
75
75
Efficiency (%)
Efficiency (%)
70
70
65
65
current
Vin=5V
Vin=5V
Tamb=25° C
Tamb=25° C
Io(A)
Io(A)
Vin=5V
Vin=5V
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Io(A)
Io(A)
Vout=3.3V
Vout=3.3V
Vout=2.5V
Vout=2.5V
Vout =1.8V
Vout =1.8V
Vo=3. 3V
Vo=3. 3V
Vo=1. 8V
Vo=1. 8V
Figure 10. Junction temperature vs output
current
Tj ( C)
Tj ( C)
110
110
100
100
Vo=2. 5
Vo=2. 5
Vi n=12V
Vi n=12V
90
90
Tamb=25°C
Tamb=25°C
80
80
70
70
60
60
50
50
40
40
30
30
20
20
0. 2 0. 4 0.6 0. 8 1 1. 2 1. 4 1. 6 1. 8 2
0. 2 0. 4 0.6 0. 8 1 1. 2 1. 4 1. 6 1. 8 2
Io(A)
Io(A)
95
95
90
90
85
85
80
80
Efficiency (%)
Efficiency (%)
75
75
Vin=12V
70
70
65
65
Vin=12V
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Io(A)
Io(A)
Vout=5V
Vout=5V
Vout=2.5V
Vout=2.5V
Vo=5 V
Vo=5 V
Vo=2 . 5 V
Vo=2 . 5 V
Vout=3.3V
Vout=3.3V
Vo= 3. 3 V
Vo= 3. 3 V
Doc ID 9552 Rev 9 15/22
Application ideas L5973AD
/
/
6 Application ideas
Figure 13. Positive buck-boost regulator
Figure 14. Buck-boost regulator
VIN = 5V
C1
10μF
10V
CERAMIC
C2
10μF
25V
CERAMIC
3.3V
C4
22nF
C3
220pF
VREF
VCC
SYNC.
COMP
4.7K
R3
6
8
L5973AD
2
4
OUT
1
D1
STPS2L25U
3
5
7
GNDINH
2.7K
FB
24K
L1 15μH
VOUT=-12V
0.6A
C5
100μF
16V
D03IN1455
Figure 15. Dual output voltage with auxiliary winding
VREF
VIN = 5V
C1
10μF
25V
CERAMIC
3.3V
C3
22nF
C2
220pF
VCC
SYNC.
COMP
R3
4.7K
6
8
L5973AD
2
4
3
7
GNDINH
OUT
1
5
FB
D03IN1456
N1/N2=2
Lp 22μH
D1
STPS25L25U
100μF
10V
C4
D2
1N4148
VOUT1=5V/
50mA
VOUT=3.3V
0.5A
C5
47μF
10V
16/22 Doc ID 9552 Rev 9
L5973AD Application ideas
Refer to L5973AD application note (AN1723) to have additional information, details, and
more application ideas.
L5973AD belongs to L597x family.
Related part numbers are:
● L5970D: 1.5 A (I
● L5972D: 2 A (I
● L5973D: 2.5 A (I
), 250 kHz step down DC-DC Converter in SO8
sw
), 250 kHz step down DC-DC Converter in SO8
sw
), 250 kHz step down DC-DC Converter in HSOP8
sw
In case higher current is needed, the nearest DC-DC Converter family is L497x.
Doc ID 9552 Rev 9 17/22
Package mechanical data L5973AD
7 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
18/22 Doc ID 9552 Rev 9
L5973AD Package mechanical data
Table 7. HSOP8 mechanical data
mm. inch
Dim.
Min Typ Max Min Typ Max
A 1.70 0.0669
A1 0.00 0.15 0.00 0.0059
A2 1.25 0.0492
b 0.31 0.51 0.0122 0.0201
c 0.17 0.25 0.0067 0.0098
D 4.80 4.90 5.00 0.1890 0.1929 0.1969
D1 3 3.1 3.2 0.118 0.122 0.126
E 5.80 6.00 6.20 0.2283 0.2441
E1 3.80 3.90 4.00 0.1496 0.1575
E2 2.31 2.41 2.51 0.091 0.095 0.099
e 1.27
h 0.25 0.50 0.0098 0.0197
L 0.40 1.27 0.0157 0.0500
k 0 8 0.3150
ccc 0.10 0.0039
Figure 16. Package dimensions
Doc ID 9552 Rev 9 19/22
Order code L5973AD
8 Order code
Table 8. Ordering information
Order code Package Packaging
L5973AD HSOP8 (Exposed pad) Tube
L5973ADTR HSOP8 (Exposed pad) Tape and reel
20/22 Doc ID 9552 Rev 9
L5973AD Revision history
9 Revision history
Table 9. Document revision history
Date Revision Changes
December 2003 1 First Issue
January 2004 2 Migration to EDOCS
December 2004 3 Added D1 and E1 dimensions in HSOP8 package information.
November 2005 4 Updated the package information section.
value updated to 4V in Table 4 on page 5, the document has
V
14-Dec-2006 5
CC
been reformatted.
15-Jan-2007 6
11-Oct-2007 7 Updated Table 6: Component List on page 14
24-Oct-2007 8 Updated Table 7 on page 19
01-Nov-2009 9 Updated Table 7 on page 19 and Table 4 on page 5
Modified V
Table 6 on page 14
value in Table 4 on page 5, added part number for C1
CC
.
Doc ID 9552 Rev 9 21/22
L5973AD
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22/22 Doc ID 9552 Rev 9
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