L5973AD
2 A switch step down switching regulator
Features
■2 A internal switch
■Operating input voltage from 4 V to 36 V
■3.3 V / (±2%) reference voltage
■Output voltage adjustable from 1.235 V to 35 V
■Low dropout operation: 100% duty cycle
■500 kHz Internally fixed frequency
■Voltage feedforward
■Zero load current operation
■Internal current limiting
■Inhibit for zero current consumption
■Synchronization
■Protection against feedback disconnection
■Thermal shutdown
Applications
■Consumer: STB, DVD, TV, VCR, car radio, LCD monitors
■Networking: XDSL, modems, DC-DC modules
■Computer: printers, audio/graphic cards, optical storage, hard disk drive
■Industrial: chargers, car battery, DC-DC converters
HSOP8 exposed pad
Description
The L5973AD is a step down monolithic power switching regulator with a switch current limit of 2 A so it is able to deliver more than 1.5 A DC current to the load depending on the application conditions.
The output voltage can be set from 1.235 V
to 35 V. The high current level is also achieved thanks to an SO8 package with exposed frame,
that allows to reduce the RthJA down to approximately 40 °C/W.
The device uses an internal P-Channel D-MOS transistor (with a typical of 200 mΩ) as switching element to avoid the use of bootstrap capacitor and guarantee high efficiency.
An internal oscillator fixes the switching frequency at 500 kHz to minimize the size of external components.
Having a minimum input voltage of 4 V only, it is particularly suitable for 5 V bus, available in all computer related applications.
Pulse by pulse current limit with the internal frequency modulation offers an effective constant current short circuit protection.
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3.3V |
VREF |
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OUT |
L1 15μH |
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VOUT=3.3V |
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6 |
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VIN = 4V to 35V |
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VCC |
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1 |
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D1 |
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8 |
L5973AD |
R1 |
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SYNC. 2 |
STPS340U |
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5.6K |
C2 |
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5 |
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C1 |
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COMP |
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330μF |
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C4 |
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FB |
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10V |
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10μF |
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INH |
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GND |
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35V |
22nF |
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R2 |
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CERAMIC |
C3 |
R3 |
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3.3K |
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220pF |
4.7K |
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D03IN1453 |
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November 2009 |
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Doc ID 9552 Rev 9 |
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1/22 |
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www.st.com |
Contents |
L5973AD |
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Contents
1 |
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
3 |
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1.1 |
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
3 |
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1.2 |
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
3 |
2 |
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
4 |
2.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 |
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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4 |
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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4.1 |
Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Voltages monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
8 |
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4.3 |
Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
8 |
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4.4 |
Current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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4.5 |
Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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4.6 |
PWM comparator and power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
11 |
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4.7 |
Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
12 |
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4.8 |
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
12 |
5 |
Additional features and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . |
13 |
5.1 Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 Output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 Zero load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.4 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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7 |
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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8 |
Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
20 |
9 |
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
21 |
2/22 |
Doc ID 9552 Rev 9 |
L5973AD |
Pin settings |
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1.2Pin description
Table 1. |
Pin description |
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Type |
Description |
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1 |
OUT |
Regulator output. |
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Master/slave synchronization. When it is open, a signal synchronous with the |
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turn-off of the internal power is present at the pin. When connected to an |
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2 |
SYNC |
external signal at a frequency higher than the internal one, then the device is |
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synchronized by the external signal. |
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Connecting together the SYNC pin of two devices, the one with the higher |
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frequency works as master and the other one, works as slave. |
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A logical signal (active high) disables the device. With IHN higher than 2.2 V |
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3 |
INH |
the device is OFF and with INH lower than 0.8V, the device is ON. |
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If INH is not used the pin must be grounded. When it is open, an internal pull- |
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up disables the device. |
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4 |
COMP |
E/A output to be used for frequency compensation. |
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Stepdown feedback input. Connecting the output voltage directly to this pin |
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5 |
FB |
results in an output voltage of 1.235 V. An external resistor divider is required |
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for higher output voltages (the typical value for the resistor connected |
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between this pin and ground is 4.7 K). |
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6 |
VREF |
Reference voltage of 3.3 V. No filter capacitor is needed to stability. |
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7 |
GND |
Ground. |
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8 |
VCC |
Unregulated DC input voltage. |
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Doc ID 9552 Rev 9 |
3/22 |
Electrical data |
L5973AD |
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Table 2. |
Absolute maximum ratings |
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Symbol |
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Parameter |
Value |
Unit |
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V8 |
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Input voltage |
40 |
V |
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V1 |
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Output DC voltage |
-1 to 40 |
V |
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Output peak voltage at t = 0.1 μs |
-5 to 40 |
V |
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I1 |
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Maximum output current |
int. limit. |
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V4, V5 |
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Analog pins |
4 |
V |
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V3 |
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INH |
-0.3V to VCC |
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V2 |
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SYNC |
-0.3 to 4 |
V |
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PTOT |
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Power dissipation at TA ≤ 60 °C |
2.25 |
W |
TJ |
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Operating junction temperature range |
-40 to 150 |
°C |
TSTG |
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Storage temperature range |
-55 to 150 |
°C |
2.2Thermal data
Table 3. |
Thermal data |
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Symbol |
Parameter |
HSOP8 |
Unit |
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Exposed pad |
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RthJA |
Maximum thermal resistance junction-ambient |
40 (1) |
°C/W |
1. Package mounted on board
4/22 |
Doc ID 9552 Rev 9 |
L5973AD |
Electrical characteristics |
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TJ = 25 °C, VCC = 12 V, unless otherwise specified |
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Table 4. |
Electrical characteristics |
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Symbol |
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Parameter |
Test condition |
Min |
Typ |
Max |
Unit |
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V |
CC |
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Operating input voltage |
V = 1.235 V; I |
o |
= 2 A |
4 |
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36 |
V |
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range |
o |
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RDS(on) |
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MOSFET on |
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0.250 |
0.5 |
Ω |
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resistance |
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Il |
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Maximum limiting |
VCC = 4.4 V to 36 V |
2 |
2.3 |
3.5 |
A |
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current |
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fs |
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Switching frequency |
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500 |
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kHz |
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Duty cycle |
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0 |
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100 |
% |
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Dynamic characteristics (see test circuit). |
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V5 |
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Voltage feedback |
4.4 V < VCC < 36 V, |
1.220 |
1.235 |
1.25 |
V |
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20 mA < IO < 2 A |
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η |
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Efficiency |
VO = 5 V, VCC = 12 V |
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% |
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DC characteristics |
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Iqop |
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Total operating |
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5 |
7 |
mA |
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quiescent current |
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Iq |
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Quiescent current |
Duty cycle = 0; |
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2.7 |
mA |
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VFB = 1.5 V |
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Iqst-by |
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Total stand-by |
Vinh > 2.2 V |
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50 |
100 |
μA |
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quiescent current |
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Inhibit |
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INH threshold voltage |
Device ON |
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0.8 |
V |
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Device OFF |
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2.2 |
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V |
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Error amplifier |
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VOH |
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High level output |
VFB = 1 V |
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3.5 |
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V |
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voltage |
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VOL |
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Low level output |
VFB = 1.5 V |
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0.4 |
V |
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voltage |
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Io source |
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Source output current |
VCOMP = 1.9 V; |
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200 |
300 |
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μA |
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VFB = 1 V |
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Io sink |
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Sink output current |
VCOMP = 1.9 V; |
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1 |
1.5 |
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mA |
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VFB = 1.5 V |
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Ib |
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Source bias current |
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2.5 |
4 |
μA |
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DC open loop gain |
RL = ∞ |
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50 |
57 |
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dB |
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Doc ID 9552 Rev 9 |
5/22 |
Electrical characteristics |
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L5973AD |
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Table 4. |
Electrical characteristics (continued) |
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Symbol |
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Parameter |
Test condition |
Min |
Typ |
Max |
Unit |
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Icomp = -0.1 mA to |
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gm |
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Transconductance |
0.1mA |
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2.3 |
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mS |
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VCOMP = 1.9 V |
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Sync function |
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High input voltage |
VCC = 4.4 V to 36 V |
2.5 |
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VREF |
V |
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Low input voltage |
VCC = 4.4 V to 36 V |
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0.74 |
V |
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Slave sink current |
Vsync = 0.74 V |
(1) |
0.11 |
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0.25 |
mA |
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0.21 |
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0.45 |
mA |
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Vsync = 2.33 V |
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Master output |
Isource = 3 mA |
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2.75 |
3 |
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V |
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amplitude |
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Output pulse width |
no load, Vsync = 1.65 V |
0.20 |
0.35 |
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μs |
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Reference section |
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Reference voltage |
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3.234 |
3.3 |
3.366 |
V |
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IREF = 0 to 5 mA |
3.2 |
3.3 |
3.399 |
V |
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VCC = 4.4 V to 36 V |
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Line regulation |
IREF = 0 mA |
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5 |
10 |
mV |
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VCC = 4.4 V to 36 V |
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Load regulation |
IREF = 0 to 5 mA |
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8 |
15 |
mV |
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Short circuit current |
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10 |
18 |
30 |
mA |
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1. Guaranteed by design.
6/22 |
Doc ID 9552 Rev 9 |
L5973AD |
Functional description |
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The main internal blocks are shown in Figure 3, where is reported the device block diagram. They are:
●A voltage regulator that supplies the internal circuitry. From this regulator, a 3.3 V reference voltage is externally available.
●A voltage monitor circuit that checks the input and internal voltages.
●A fully integrated sawtooth oscillator whose frequency is 500 kHz
●Two embedded current limitations circuitries which control the current that flows through the power switch. The Pulse by Pulse Current Limit forces the power switch OFF cycle by cycle if the current reaches an internal threshold, while the Frequency Shifter reduces the switching frequency in order to strongly reduce the duty cycle.
●A transconductance error amplifier.
●A pulse width modulator (PWM) comparator and the relative logic circuitry necessary to drive the internal power.
●An high side driver for the internal P-MOS switch.
●An inhibit block for stand-by operation.
●A circuit to realize the thermal protection function.
Doc ID 9552 Rev 9 |
7/22 |