ST L5973AD User Manual

2 A switch step down switching regulator

Features

■ 2 A internal switch

■ Operating input voltage from 4 V to 36 V

■ 3.3 V / (±2%) reference voltage

■ Output voltage adjustable from 1.235 V to 35 V

■ Low dropout operation: 100% duty cycle

■ 500 kHz Internally fixed frequency

■ Voltage feedforward

■ Zero load current operation

■ Internal current limiting

■ Inhibit for zero current consumption

■ Synchronization

■ Protection against feedback disconnection

■ Thermal shutdown

Applications

■ Consumer: STB, DVD, TV, VCR, car radio,

LCD monitors

■ Networking: XDSL, modems, DC-DC modules

■ Computer: printers, audio/graphic cards,

optical storage, hard disk drive

■ Industrial: chargers, car battery, DC-DC

converters

Figure 1. Test application circuit

VREF

VIN = 4V to 35V

C1

10μF

35V

CERAMIC

3.3V

C4

22nF

C3

220pF

SYNC.

COMP

VCC

R3

4.7K

6

8

L5973AD

2

4

3

L5973AD

HSOP8 exposed pad

Description

The L5973AD is a step down monolithic power
switching regulator with a switch current limit of
2 A so it is able to deliver more than 1.5 A DC
current to the load depending on the application
conditions.
The output voltage can be set from 1.235 V
to 35 V. The high current level is also achieved
thanks to an SO8 package with exposed frame,
that allows to reduce the R
approximately 40 °C/W.
The device uses an internal P-Channel D-MOS
transistor (with a typical of 200 mΩ) as switching
element to avoid the use of bootstrap capacitor
and guarantee high efficiency.
An internal oscillator fixes the switching frequency
at 500 kHz to minimize the size of external
components.
Having a minimum input voltage of 4 V only, it is
particularly suitable for 5 V bus, available in all
computer related applications.
Pulse by pulse current limit with the internal
frequency modulation offers an effective constant
current short circuit protection.

L1 15μH

OUT

1

D1

STPS340U

5

7

FB

GNDINH

R1

5.6K

R2

3.3K

down to

thJA

VOUT=3.3V

C2

330μF

10V

D03IN1453

November 2009 Doc ID 9552 Rev 9 1/22

www.st.com

22

Contents L5973AD

Contents

1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.1 Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2 Voltages monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.3 Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.4 Current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.5 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.6 PWM comparator and power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.7 Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.8 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5 Additional features and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.1 Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.2 Output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.3 Zero load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.4 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6 Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8 Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2/22 Doc ID 9552 Rev 9

L5973AD Pin settings

1 Pin settings

1.1 Pin connection

Figure 2. Pin connection (top view)

COMP

1.2 Pin description

Table 1. Pin description

N° Type Description

1 OUT Regulator output.

2 SYNC

3INH

4 COMP E/A output to be used for frequency compensation.

OUT

SYNC

INH

1

2

3

4

D98IN955

Master/slave synchronization. When it is open, a signal synchronous with the
turn-off of the internal power is present at the pin. When connected to an
external signal at a frequency higher than the internal one, then the device is
synchronized by the external signal.
Connecting together the SYNC pin of two devices, the one with the higher
frequency works as master and the other one, works as slave.

A logical signal (active high) disables the device. With IHN higher than 2.2 V
the device is OFF and with INH lower than 0.8V, the device is ON.
If INH is not used the pin must be grounded. When it is open, an internal pull­up disables the device.

8

7

6

5

VCC

GND

VREF

FB

Stepdown feedback input. Connecting the output voltage directly to this pin

5FB

6 VREF Reference voltage of 3.3 V. No filter capacitor is needed to stability.

7 GND Ground.

8 VCC Unregulated DC input voltage.

results in an output voltage of 1.235 V. An external resistor divider is required
for higher output voltages (the typical value for the resistor connected
between this pin and ground is 4.7 K).

Doc ID 9552 Rev 9 3/22

Electrical data L5973AD

2 Electrical data

2.1 Maximum ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

V

8

V

1

I

1

V

, V

4

V

3

V

2

P

TOT

T

J

T

STG

Input voltage 40 V

Output DC voltage
Output peak voltage at t = 0.1 μs

-1 to 40

-5 to 40

Maximum output current int. limit.

Analog pins 4 V

5

INH -0.3V to V

SYNC -0.3 to 4 V

Power dissipation at TA ≤ 60 °C 2.25 W

Operating junction temperature range -40 to 150 °C

Storage temperature range -55 to 150 °C

V
V

CC

2.2 Thermal data

Table 3. Thermal data

Symbol Parameter

R

thJA

1. Package mounted on board

Maximum thermal resistance junction-ambient

HSOP8

Exposed pad

(1)

40

Unit

°C/W

4/22 Doc ID 9552 Rev 9

L5973AD Electrical characteristics

3 Electrical characteristics

TJ = 25 °C, VCC = 12 V, unless otherwise specified

Table 4. Electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit

V

CC

Operating input voltage
range

Vo = 1.235 V; Io = 2 A

436V

R

DS(on)

I

l

f

s

MOSFET on
resistance

Maximum limiting
current

Switching frequency 500 kHz

Duty cycle 0 100 %

Dynamic characteristics (see test circuit).

V

5

η

Voltage feedback

Efficiency

DC characteristics

I

qop

I

I

qst-by

q

Total operating
quiescent current

Quiescent current

Total stand-by
quiescent current

Inhibit

VCC = 4.4 V to 36 V

4.4 V < VCC < 36 V,
20 mA < I

= 5 V, VCC = 12 V

V

O

< 2 A

O

Duty cycle = 0;
V

= 1.5 V

FB

V

> 2.2 V

inh

0.250 0.5 Ω

22.33.5A

1.220 1.235 1.25 V

90 %

57mA

2.7 mA

50 100 μA

Error amplifier

V

OH

V

OL

I

o source

I

o sink

I

b

INH threshold voltage

Device ON 0.8 V

Device OFF 2.2 V

High level output
voltage

Low level output
voltage

Source output current

Sink output current

VFB = 1 V 3.5 V

VFB = 1.5 V 0.4 V

= 1.9 V;

V

COMP

V

FB

V

COMP

V

FB

= 1 V

= 1.9 V;

= 1.5 V

200 300 μA

11.5 mA

Source bias current 2.5 4 μA

R

DC open loop gain

= ∞ 50 57 dB

L

Doc ID 9552 Rev 9 5/22

Electrical characteristics L5973AD

Table 4. Electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit

I

= -0.1 mA to

comp

gm Transconductance

Sync function

0.1mA
V

COMP

= 1.9 V

2.3 mS

High input voltage

Low input voltage

Slave sink current

Master output
amplitude

Output pulse width

Reference section

Reference voltage 3.234 3.3 3.366 V

Line regulation

Load regulation

Short circuit current 10 18 30 mA

1. Guaranteed by design.

= 4.4 V to 36 V 2.5 V

V

CC

V

= 4.4 V to 36 V 0.74 V

CC

V

= 0.74 V

sync

V

= 2.33 V

sync

= 3 mA

I

source

no load, V

I

= 0 to 5 mA

REF

= 4.4 V to 36 V

V

CC

I

= 0 mA

REF

= 4.4 V to 36 V

V

CC

= 0 to 5 mA 8 15 mV

I

REF

(1)

= 1.65 V 0.20 0.35 μs

sync

0.11

0.21

2.75 3 V

3.2 3.3 3.399 V

510mV

REF

0.25

0.45mAmA

V

6/22 Doc ID 9552 Rev 9

L5973AD Functional description

4 Functional description

The main internal blocks are shown in Figure 3, where is reported the device block diagram.
They are:

● A voltage regulator that supplies the internal circuitry. From this regulator, a 3.3 V

reference voltage is externally available.

● A voltage monitor circuit that checks the input and internal voltages.

● A fully integrated sawtooth oscillator whose frequency is 500 kHz

● Two embedded current limitations circuitries which control the current that flows

through the power switch. The Pulse by Pulse Current Limit forces the power switch
OFF cycle by cycle if the current reaches an internal threshold, while the Frequency
Shifter reduces the switching frequency in order to strongly reduce the duty cycle.

● A transconductance error amplifier.

● A pulse width modulator (PWM) comparator and the relative logic circuitry necessary to

drive the internal power.

● An high side driver for the internal P-MOS switch.

● An inhibit block for stand-by operation.

● A circuit to realize the thermal protection function.

Figure 3. Block diagram

Doc ID 9552 Rev 9 7/22