L5970AD
Fi
1.5A SWITCH STEP DOWN SWITCHING REGULATOR
1 General Features
■ 1.5A INTERNAL SWITCH
■
OPERATING INPUT VOLTAGE FROM 4.4V TO 36V
■ 3.3V / (±2%) REFERENCE VOLTAGE
■ OUTPUT VOLTAGE ADJUSTABLE FROM
1.235V TO 35V
■ LOW DROPOUT OPERATION: 100% DUTY
CYCLE
■ 500KHz INTERNALLY FIXED FREQUENCY
■ VOLTAGE FEEDFORWARD
■ ZERO LOAD CURRENT OPERATION
■ INTERNAL CURRENT LIMITING
■ INHIBIT FOR ZERO CURRENT
CONSUMPTION
■ SYNCHRONIZATION
■ PROTECTION AGAINST FEEDBACK
DISCONNECTION
■ THERMAL SHUTDOWN
1.1 APPLICATIONS:
■ CONSUMER: STB, DVD, TV, VCR,CAR
RADIO, LCD MONITORS
■ NETWORKING: XDSL, MODEMS,DC-DC
MODULES
■ COMPUTER: PRINTERS, AUDIO/GRAPHIC
CARDS, OPTICAL STORAGE, HARD DISK
DRIVE
■ INDUSTRIAL: CHARGERS, CAR BATTERY
DC-DC CONVERTERS
gure 1. Package
SO-8
Table 1. Order Codes
Part Number Package
L5970AD SO-8
L5970ADTR SO-8 in Tape & Reel
2 Description
The L5970AD is a step down monolithic power
switching regulator with a switch current limit of 1.5A
so it is able to deliver more than 1A DC current to the
load depending on the application conditions.
The output voltage can be set from 1.235V to 35V.
The device uses an internal P-Channel D-MOS tran-
sistor (with a typical R
element to avoid the use of bootstrap capacitor and
guarantee high efficiency.
An internal oscillator fixes the switching frequency at
500KHz to minimize the size of external components.
Having a minimum input voltage of 4.4V only, it is
particularly suitable for 5V bus, available in all computer related applications.
Pulse by pulse current limit with the internal frequency modulation offers an effective constant current
short circuit protection.
of 200mΩ) as switching
DSON
Figure 2. Test and Application Circuit
VREF
3.3V
C4
22nF
C3
220pF
VCC
SYNC.
COMP
R3
4.7K
VIN = 4.4V to 35V
C1
10µF
35V
CERAMIC
March 2005
6
8
L5970AD
2
4
OUT
1
7
5
GNDINH
D05IN1530
FB
3
L1 15µH
D1
STPS2L25U
R1
5.6K
R2
3.3K
VOUT=3.3V
C2
330µF
10V
Rev. 1
1/11
L5970AD
Table 2. Thermal Data
Symbol Parameter Value Unit
R
th (j-amb)
(*) Package mounted on board
Figure 3. Pin Connection (top view)
Table 3. Pin Description
N. Name Description
1 OUT Regulator Output.
2 SYNC Master/Slave Synchronization. When it is open, a signal synchronous with the turn-off of the inter-
3INH
4 COMP E/A output to be used for frequency compensation.
5 FB Stepdown feedback input. Connecting the output voltage directly to this pin results in an output
6V
7 GND Ground.
8V
Thermal Resistance Junction to ambient Max. 120 (*) °C/W
VCC
OUT
SYNC
INH
COMP
1
2
3
4
D98IN955
8
GND
7
VREF
6
FB
5
nal power is present at the pin. When connected to an external signal at a frequency higher than
the internal one, then the device is synchronized by the external signal.
Connecting together the SYNC pin of two devices, the one with the higher frequency works as
master and the other one, works as slave.
A logical signal (active high) disables the device. With IHN higher than 2.2V the device is OFF and with
INH lower than 0.8V, the device is ON.
If INH is not used the pin must be grounded. When it is open, an internal pull-up disables the device.
voltage of 1.235V. An external resistor divider is required for higher output voltages (the typical
value for the resistor connected between this pin and ground is 4.7K).
Reference voltage of 3.3V. No filter capacitor is needed to stability.
REF
Unregulated DC input voltage.
CC
Table 4. Absolute Maximum Ratings
Symbol Parameter Value Unit
2/11
V
V
I
1
, V
V
4
V
V
P
tot
T
T
stg
Input Voltage 40 V
8
Output DC voltage
1
Output peak voltage at t = 0.1µs
-1 to 40
-5 to 40
Maximum output current int. limit.
Analog pins 4 V
5
INH -0.3V to V
3
SYNC -0.3 to 4 V
2
Power dissipation at T
Operating junction temperature range -40 to 150 °C
j
≤ 60°C 0.75 W
amb
Storage temperature range -55 to 150 °C
CC
V
V
L5970AD
Table 5. Electrical Characteristics (Tj = 25°C, VCC = 12V, unless otherwise specified.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
V
R
DSON
DYNAMIC CHARACTERISTICS
V
DC CHARACTERISTICS
I
qop
I
qst-by
INHIBIT
ERROR AMPLIFIER
V
V
I
o source
I
o sink
gm Transconductance I
SYNC FUNCTION
REFERENCE SECTION
Note: 1. Guaranteed by design
Operating input voltage range 4.4 36 V
CC
Mosfet on Resistance 0.250 0.5 Ω
Maximum limiting current VCC = 4.4V to 36V 1.8 A
I
l
Switching frequency 500 KHz
f
s
Duty cycle 0 100 %
Voltage feedback 4.4V < VCC < 36V 1.220 1.235 1.25 V
5
η Efficiency V
= 5V, VCC = 12V 90 %
O
Total Operating Quiescent Current 5 7 mA
Quiescent current Duty Cycle = 0; VFB = 1.5V 2.7 mA
I
q
Total stand-by quiescent current V
> 2.2V 50 100 µA
inh
INH Threshold Voltage Device ON 0.8 V
Device OFF 2.2 V
High level output voltage VFB = 1V 3.5 V
OH
Low level output voltage VFB = 1.5V 0.4 V
OL
Source output current V
Sink output current V
Source bias current 2.5 4 µA
I
b
DC open loop gain R
High Input Voltage V
Low Input Voltage V
Slave Sink Current
Master Output Amplitude I
Output Pulse Width no load, V
= 1.9V; VFB = 1V 200 300 µA
COMP
= 1.9V; VFB = 1.5V 1 1.5 mA
COMP
= ∞ 50 57 dB
L
= -0.1mA to 0.1mA
comp
V
= 1.9V
COMP
= 4.4V to 36V 2.5 V
CC
= 4.4V to 36V 0.74 V
CC
= 0.74V
V
sync
V
= 2.33V
sync
= 3mA 2.75 3 V
source
(1)
= 1.65V 0.20 0.35 µs
sync
0.11
0.21
2.3 mS
Reference Voltage 3.234 3.3 3.366 V
I
= 0 to 5mA
REF
3.2 3.3 3.399 V
VCC = 4.4V to 36V
Line Regulation I
REF
= 0mA
510mV
VCC = 4.4V to 36V
Load Regulation I
= 0 to 5mA 8 15 mV
REF
Short Circuit Current 10 18 30 mA
REF
0.25
0.45mAmA
V
3/11
L5970AD
3 Functional Description
The main internal blocks are shown in Fig. 4, where is reported the device block diagram. They are:
● A voltage regulator that supplies the internal circuitry. From this regulator, a 3.3V reference
voltage is externally available.
● A voltage monitor circuit that checks the input and internal voltages.
● A fully integrated sawtooth oscillator whose frequency is500KHz
● Two embedded current limitations circuitries which control the current that flows through the
power switch. The Pulse by Pulse Current Limit forces the power switch OFF cycle by cycle
if the current reaches an internal threshold, while the Frequency Shifter reduces the switching frequency in order to strongly reduce the duty cycle.
● A transconductance error amplifier.
● A pulse width modulator (PWM) comparator and the relative logic circuitry necessary to drive
the internal power.
● An high side driver for the internal P-MOS switch.
● An inhibit block for stand-by operation.
● A circuit to realize the thermal protection function.
Figure 4. Block Diagram
VCC
VOLTAGES
MONITOR
PWM
+
-
THERMAL
SHUTDOWN
SUPPLY
1.235V 3.5V
PEAK TO PEAK
CURRENT LIMIT
DCkQ
DRIVER
FREQUENCY
SHIFTER
GND OUT
V
REF
BUFFER
LPDMOS
POWER
D00IN1125
V
REF
INH
COMP
FB
SYNC
TRIMMING
1.235V
INHIBIT
E/A
-
+
OSCILLATOR
3.1 POWER SUPPLY & VOLTAGE REFERENCE
The internal regulator circuit (shown in Figure 2) consists of a start-up circuit, an internal voltage Preregulator, the Bandgap voltage reference and the Bias block that provides current to all the blocks.
The Starter gives the start-up currents to the whole device when the input voltage goes high and the device is enabled (inhibit pin connected to ground).
The Preregulator block supplies the Bandgap cell with a preregulated voltage V
that has a very low
REG
supply voltage noise sensitivity.
3.2 VOLTAGES MONITOR
An internal block senses continuously the Vcc, V
and Vbg. If the voltages go higher than their thresholds, the
ref
regulator starts to work. There is also an hysteresis on the V
4/11
(UVLO).
CC
Figure 5. Internal Regulator Circuit
V
CC
L5970AD
STARTER
IC BIAS
D00IN1126
PREREGULATOR
VREG
BANDGAP
VREF
3.3 OSCILLATOR & SYNCHRONIZATOR
Figure 6 shows the block diagram of the oscillator circuit.
The Clock Generator provides the switching frequency of the device that is internally fixed at 500KHz. The frequency
shifter block acts reducing the switching frequency in case of strong overcurrent or short circuit. The clock signal is
then used in the internal logic circuitry and is the input of the Ramp Generator and Synchronizator blocks.
The Ramp Generator circuit provides the sawtooth signal, used to realize the PWM control and the internal voltage feed forward, while the Synchronizator circuit generates the synchronization signal. Infact the device has a
synchronization pin that can works both as Master and Slave.
As Master to synchronize external devices to the internal switching frequency.
As Slave to synchronize itself by external signal.
In particular, connecting together two devices, the one with the lower switching frequency works as Slave and
the other one works as Master.
To synchronize the device, the SYNC pin has to pass from a low level to a level higher than the synchronization
threshold with a duty cycle that can vary approximately from 10% to 90%, depending also on the signal frequency and amplitude.
The frequency of the synchronization signal must be at least higher than the internal switching frequency of the
device (500KHz).
Figure 6. Oscillator Circuit
Ibias_osc
FREQUENCY
SHIFTER
CLOCK
GENERATOR
D00IN1131
RAMP
GENERATOR
SYNCHRONIZATOR
CLOCK
RAMP
SYNC
t
5/11
L5970AD
3.4 CURRENT PROTECTION
The L5970AD has two current limit protections, pulse by pulse and frequency fold back.
The schematic of the current limitation circuitry for the pulse by pulse protection is shown in figure 7.
The output power PDMOS transistor is split in two parallel PDMOS. The smallest one has a resistor in series,
R
PDMOS is switched off until the next falling edge of the internal clock pulse.
Due to this reduction of the ON time, the output voltage decreases.
Since the minimum switch ON time (necessary to avoid false overcurrent signal) is not enough to obtain a suf-
ficiently low duty cycle at 500KHz, the output current, in strong overcurrent or short circuit conditions, could increase again. For this reason the switching frequency is also reduced, so keeping the inductor current under its
maximum threshold. The Frequency Shifter (see fig. 6) depends on the feedback voltage. As the feedback voltage decreases (due to the reduced duty cycle), the switching frequency decreases too.
Figure 7. Current Limitation Circuitry
. The current is sensed through Rsense and if reaches the threshold, the mirror is unbalanced and the
SENSE
VCC
DRIVER
OUT
A1/A2=95
I
OFF
PWM
RSENSE
A1
A2
II
RTH
I
NOT
D00IN1134
L
3.5 ERROR AMPLIFIER
The voltage error amplifier is the core of the loop regulation. It is a transconductance operational amplifier whose
non inverting input is connected to the internal voltage reference (1.235V), while the inverting input (FB) is connected to the external divider or directly to the output voltage. The output (COMP) is connected to the external
compensation network.
The uncompensated error amplifier has the following characteristics:
Transconductance 2300µS
Low frequency gain 65dB
Minimum sink/source voltage 1500µA/300µA
Output voltage swing 0.4V/3.65V
Input bias current 2.5µA
The error amplifier output is compared with the oscillator sawtooth to perform PWM control.
3.6 PWM COMPARATOR AND POWER STAGE
This block compares the oscillator sawtooth and the error amplifier output signals generating the PWM
signal for the driving stage.
The power stage is a very critical block cause it has to guarantee a correct turn on and turn off of the PDMOS.
6/11
L5970AD
The turn on of the power element, or better, the rise time of the current at turn on, is a very critical parameter to compromise.
At a first approach, it looks like the faster it is the rise time, the lower are the turn on losses.
But there is a limit introduced by the recovery time of the recirculation diode.
In fact when the current of the power element equals the inductor current, the diode turns off and the drain
of the power is free to go high. But during its recovery time, the diode can be considered as an high value
capacitor and this produces a very high peak current, responsible of many problems:
Spikes on the device supply voltage that cause oscillations (and thus noise) due to the board parasitics.
Turn on overcurrent causing a decrease of the efficiency and system reliability.
Big EMI problems.
Shorter freewheeling diode life.
The fall time of the current during the turn off is also critical. In fact it produces voltage spikes (due to the
parasitics elements of the board) that increase the voltage drop across the PDMOS.
In order to minimize all these problems, a new topology of driving circuit has been used and its block diagram is shown in fig. 8.
The basic idea is to change the current levels used to turn on and off the power switch, according with the
PDMOS status and with the gate clamp status.
This circuitry allow to turn off and on quickly the power switch and to manage the above question related
to the freewheeling diode recovery time problem. The gate clamp is necessary to avoid that Vgs of the
internal switch goes higher than Vgsmax. The ON/OFF Control block avoids any cross conduction between the supply line and ground.
Figure 8. Driving Circuitry
VCC
Vgs
max
I
OFF
STOP
DRIVE
DRAIN
D00IN1133
CLAMP
ON/OFF
CONTROL
GATE
OFF
ON
DRAIN
I
ON
PDMOS
L
ESR
C
VOUT
I
LOAD
3.7 INHIBIT FUNCTION
The inhibit feature allows to put in stand-by mode the device. With INH pin higher than 2.2V the device is disabled and the power consumption is reduced to less than 100
µ
A. With INH pin lower than 0.8V, the device is
enabled. If the INH pin is left floating, an internal pull up ensures that the voltage at the pin reaches the inhibit
threshold and the device is disabled. The pin is also Vcc compatible.
7/11
L5970AD
3.8 THERMAL SHUTDOWN
The shutdown block generates a signal that turns off the power stage if the temperature of the chip goes higher
than a fixed internal threshold (150°C). The sensing element of the chip is very close to the PDMOS area, so
ensuring an accurate and fast temperature detection. An hysteresis of approximately 20°C avoids that the devices turns on and off continuously
4 Additional Features and Protections
4.1 FEEDBACK DISCONNECTION
In case of feedback disconnection, the duty cycle increases versus the maximum allowed value, bringing the
output voltage close to the input supply. This condition could destroy the load.
To avoid this dangerous condition, the device is turned off if the feedback pin remains floating.
4.2 OUTPUT OVERVOLTAGE PROTECTION
The overvoltage protection, OVP, is realized by using an internal comparator, which input is connected to the
feedback, that turns off the power stage when the OVP threshold is reached. This threshold is typically 30%
higher than the feedback voltage.
When a voltage divider is requested for adjusting the output voltage (see test application circuit), the OVP intervention will be set at:
+
R
1R2
--------------------
1.3
V
OVP
⋅⋅=
R
V
2
FB
Where R
is the resistor connected between the output voltage and the feedback pin, while R2 is between the
1
feedback pin and ground.
4.3 ZERO LOAD
Due to the fact that the internal power is a PDMOS, no boostrap capacitor is required and so, the device works properly also with no load at the output. In this condition it works in burst mode, with random repetition rate of the burst.
5 Application Ideas
L5970AD belongs to L597x family.
Related part numbers are:
● L5970D: 1.5A (I
● L5972D: 2A (I
● L5973AD: 2A (I
● L5973D: 2.5A (I
In case higher current is needed, the nearest DC-DC Converter family is L497x.
), 250KHz Step Down DC-DC Converter in SO8
sw
), 250KHz Step Down DC-DC Converter in SO8
sw
), 500KHz Step Down DC-DC Converter in HSOP8
sw
), 250KHz Step Down DC-DC Converter in HSOP8
sw
8/11
6 Package Information
Figure 9. SO-8 Mechanical Data & Package Dimensions
L5970AD
DIM.
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
A2 1.10 1.65 0.043 0.065
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
(1)
D
E 3.80 4.00 0.15 0.157
e 1.27 0.050
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 1.27 0.016 0.050
k 0˚ (min.), 8˚ (max.)
ddd 0.10 0.004
Note: (1) Dimensions D does not include mold flash , protru-
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
4.80 5.00 0.189 0.197
sions or gate burrs.
Mold flash, potrusions or gate b urrs shall no t exceed
0.15mm (.006inch) in total (both side).
OUTLINE AND
MECHANICAL DATA
SO-8
0016023 C
9/11
L5970AD
7 REVISION HISTORY
Table 6. Revision History
Date Revision Description of Changes
March 2005 1 Initial load.
10/11
L5970AD
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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All other names are the property of their respective owners
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11/11
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