Datasheet L5962 Datasheet (ST)

Multiple linear/switching voltage regulator for car-radio

Features

■ Step-down synchronous switching voltage

regulator
– Internal high-side/ Low-side NDMOS
–1.2 < V

resistors

– 1.2/2.5 A load current selected through

dedicated pin
– 185 kHz free-run frequency
– SYNC function (220 < f

■ Linear regulators

– 3.3/5 V @ 150 mA standby regulator

selected through dedicated pin

(VSTBYSEL)
– 5/8.5 V @ 350 mA switched linear regulator

enabled and selected through I

(VLR1)
– 3.3/10 V @ 1 A switched linear regulator

enabled and selected through I

(VLR2)

■ 2 High side drivers (0.5 V max drop @ 0.5 A)

enabled through I
protection circuit against:

– short to ground and battery
– loss of ground and battery
– unsupplied short to battery

■ Reset function with configurable delay (RST,

RSTDLY)

2

■ I

C bus

Table 1. Device summary

< 8 V selectable through external

out

< 400 kHz)

sw

2

C bus

2

C bus

2

C bus and equipped with

L5962

PowerSO36 (slug-up)

■ Enable pin to drive switching regulator and I

bus logic

■ Under/over voltage battery detector

(VBATVW)
– Under voltage threshold adjustable through

dedicated pin (LVWIN)

■ Load dump protection

■ Independent thermal protection on all

regulators

Description

L5962 is a very versatile device exploiting BCD
technology characteristics to provide a complete
set of regulated voltages covering all the needs of
a car-radio set.

In standby condition the device guarantees
extremely low quiescent current (90 µA max ­40 °C < T < 85 °C) and minimum operating
voltage (4.5 V using an external Schottky diode
for the back-up function).

2

C

Order code Package Packing

L5962 PowerSO36 Tray

L5962TR PowerSO36 Tape and reel

December 2009 Doc ID 16819 Rev 2 1/24

www.st.com

1

Contents L5962

Contents

1 Block and application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1 Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1.1 Linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1.2 Switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2 High side drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5 Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1 Battery detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6I

2

C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.2 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7 Software specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2/24 Doc ID 16819 Rev 2

L5962 List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 6. Chip address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 7. IB1 data byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 8. VLR2 output level selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 9. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Doc ID 16819 Rev 2 3/24

List of figures L5962

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Low voltage warning high level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 5. Data validity on the I
Figure 6. Timing diagram on the I
Figure 7. Acknowledge on the I

Figure 8. PowerSO36 (slug-up) mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . 22

2

C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2

C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2

C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4/24 Doc ID 16819 Rev 2

L5962 Block and application diagram

1 Block and application diagram

Figure 1. Block diagram

VINSW

VBATP

SYNCH

LVWIN

VBATVW

RST

RSTDLY

SDA
SCL

EN

Bandgap Reference

External
Storage

POR &

Startup Logic

Oscillator

Clock

UV / OV

Detect

Synch

Logic

Reset &

Delay

I2Cbus

Logic

Ground

Switching
Regulator

Standby

Regulator

Linear

Regulator

#1

Linear

Regulator

#2

HSD

HSD

PH

CBS

CLIM

VFB

VCMP

SOST

VSTBYSEL

VSTBY

VLR1

VINLR2

VLR2

HSD1

HSD2

TAB

SUBS

AGNDPGND

VBAT

AC00428

Doc ID 16819 Rev 2 5/24

Block and application diagram L5962

Figure 2. Application diagram

VDCOUT

22µH

2.2µ

200u/10V

22

TAB 1

1500pF

0.1µF

CBS 3

PGND 2

4.7µ

NC 5

PHASE 4

30µ/35V

NC 6

VBAT

HSD1

HSD1 9

VINsw 8

SUBGND 7

HSD2

VBAT 10

1000u/50 V

HSD2 11

VBATP 12

0.1µ

RSTDLY 13

0.1µ

470µ/25V

0.1µ

0.1µ

1µ

VSTBY

S3

NC 17

NC 18

AGND 16

VSTBY 14

VSTBYS 15

L5962

36 NC

35 NC

34 CLIM

33 VFB

32 VCMP

31 SOST

30 SYNC

29 SCL

28 EN

27 RESET

EN

SCL

S1

47K

+5V

470

3.3nF

2.7nF

22K

75k

1.8nF

22k/(VDCOUT-1)

6/24 Doc ID 16819 Rev 2

SYNC

47K

+5V

RESET

S2

10K

VSTBY

VLR2

26 VLR2

25 VINLR

VBAT

SDA

R1

0.1µ

R2

24 SDA

23 VLR1

22 VBATW

21 LVWIN

20 NC

19 NC

10K

VSTBY

VLR1

VBATW

1µ

0.1µ

1µ

0.1µ

L5962 Pin description

2 Pin description

Figure 3. Pin connection (top view)

Table 2. Pin description

N.C.

N.C.

CLIM

VFB

VCMP

SOST

SYNC

SCL

RST

VLR2

VINLR2

SDA

VLR1

VBATW

LVWIN

N.C.

N.C.

EN

36

35

34

33

32

31

30

29

28

27

26

25

23

22

21

20

19

AC00429

1

TAB

2

PGND

3

CBS

4

PH

5

N.C.

6

N.C.

7

SUBGND

8

VINsw

9

HSD1

10

11

12

1324

14

15

16

17

18

VBAT

HSD2

VBATP

RSTDLY

VSTBY

VSTBYSEL

AGND

N.C.

N.C.

Pin # Pad name Function Description

1 TAB This pin must be connected to GND

2 PGND Switching regulator ground It is the power ground reference

3 CBS Bootstrap for switching regulator

Bootstrap capacitor Input for the switching
regulator

Phase output. It is the switching output of the

4 PH Switching stage output

switching regulator. It also provides phase
reference for bootstrap drive.

5 N.C. Not connected -

6 N.C. Not connected -

7 SUBGND Substrate ground Substrate ground

8 VINsw Switching regulator supply voltage Battery voltage for the switching regulator

st

9 HSD1 High side driver 1 Output of the 1

10 VBAT VLR1/HSD1/HSD2 supply voltage

Voltage input for linear regulator #1 high side
driver and battery warnings

11 HSD2 High side driver 2 Output of the 2

12 VBATP Standby regulator supply voltage

Protected battery input for bias, bandgap,
oscillator, and VSTBY regulator

high side driver

nd

high side driver

13 RSTDLY Reset delay function Input

14 VSTBY Standby regulator output Output of the standby regulator

Doc ID 16819 Rev 2 7/24

Pin description L5962

Table 2. Pin description (continued)

Pin # Pad name Function Description

15 VSTBYSEL Standby regulator selector

Selection input for standby regulator output (3.3 V
or 5 V)

16 AGND Analog ground Analog voltage reference

17 N.C. Not connected -

18 N.C. Not connected -

19 N.C. Not connected -

20 N.C. Not connected -

21 LVWIN Battery detector adjustment input Low-voltage warning input

22 VBATW Battery detector output (open-drain) Battery voltage warning output

st

23 VLR1 Switched linear regulator 1 Output of the 1

24 SDA I

2

C bus data I2C data line

25 VINLR2 VLR2 supply voltage Battery supply for the 2

26 VLR2 Switched linear regulator 2 Output of the 2

linear regulator

nd

linear regulator

nd

linear regulator

27 RST Reset Output

28 EN Enable Active mode enable input. Active high

2

29 SCL I

C bus clock I2C clock source supplied by the master device

30 SYNC Switching regulator SYNC function Synchronization Input

31 SOST Switching regulator soft-start Soft start external capacitor

32 VCMP Switching regulator compensation Feedback compensation input.

33 VFB Switching regulator feedback Regulated output voltage sense

34 CLIM Switching regulator current limit selector Choose between two current limits

35 N.C. Not connected -

36 N.C. Not connected -

8/24 Doc ID 16819 Rev 2

L5962 Electrical specification

3 Electrical specification

3.1 Absolute maximum ratings

Table 3. Absolute maximum ratings

Pin name/Symbol Parameter Value Unit

Vs

MAX

Vpin

MAX

AGND, PGND,
SUBGND, TAB

T

op

T

stg

3.2 Thermal data

Table 4. Thermal data

Symbol Parameter Value Unit

R

th j-case

Thermal resistance junction-to-case (max) 2 °C/W

Operating supply voltage (VBAT,
VBATP, VINSW, VINLR2)

Transient supply voltage (VBAT,
VBATP, VINSW, VINLR2)

-0.3 to 27 V

-0.3 to 50 V

Input pin voltage
(EN, RSTDLY, VSTBYSEL, SYNCH,
SCL, SDA, VCMP, VFB, CLIM,

-0.3 to 6 V

SOST)

Ground pin voltage -0.3 to +0.3 V

Operating temperature range -40 to 85 °C

Storage temperature range -55 to 150 °C

3.3 Electrical characteristics

VBAT= VINSW = VINLR2 = 14.4 V, T

min

I

q

OV

UV

OV

(

VBATP operating voltage - 4.1 - - V

EN = 0; I

Total quiescent current

@ T = -40 °C
@ 25 °C < T < 85 °C

Overvoltage shut-down VBAT rising 27 29 31 V

Hysteresis on V

OV

VBAT undervoltage threshold

--400-mV

VBAT falling;
VBATVW transition to 0 V

Doc ID 16819 Rev 2 9/24

Table 5. Electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

Input supplies

V

V

HYS

V

= 25 °C unless otherwise specified.

amb

=100 µA

VSTBY

--9075µA

77.58 V

Electrical specification L5962

Table 5. Electrical characteristics (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

HYS

UV

VSTBY (3.3 V)

Vout

VSTBY3

LnR

VSTBY3

LdR

VSTBY3

Vdo

VSTBY3

Ishort

VSTBY3

OS/US

VSTBY3

PSRR

VSTBY3

n

VSTBY3

TS

VSTBY3

HYS

TS-VSTBY3

ESR

VSTBY3

VSTBY (5 V)

Hysteresis on V

UV

Output voltage 0 < I

Line regulation

Load regulation 0<I

Drop out voltage I

--1-V

< 150 mA 3.2 3.3 3.4 V

load

4.1 <VBATP<18V
=150mA

I

load

<150mA - - 20 mV

load

=150mA - - 600 mV

load

-10 - +50 mV

Short circuit current limit - 250 - 450 mA

I

0 ↔ 150 mA, t > 50µs

Overshoot/Undershoot

Power supply rejection ratio

load

C = 1 µF ceramic

I

= 50 mA

load

120 Hz < f < 10 kHz
VBATP

= 1 Vpp

ac

--±5%

70 - - dB

A-weighted filter

Output noise

Thermal shut-down
temperature

Hysteresis on thermal shut­down temperature

20 Hz < f < 20 kHz
I

= 5 mA

load

--200µV

Temperature rising 150 - 190 °C

-5-15°C

External filtering capacitor ESR C > 0.5 µF - - 0.2 Ω

Vout

LnR

LdR

Vdo

Ishort

OS/US

PSRR

VSTBY5

VSTBY5

VSTBY5

VSTBY5

VSTBY5

VSTBY5

VSTBY5

Output voltage 0 < I

Line regulation 6<VBATP<18V I

Load regulation 0 < I

Drop out voltage I

< 150 mA 4.80 5 5.15 V

load

load

< 150 mA - - 25 mV

load

= 150 mA - - 600 mV

load

Short circuit current limit - 250 - 450 mA

0 ↔ 150 mA, t > 50µs

I

Overshoot/Undershoot

Power supply rejection ratio

load

C = 1 µF ceramic

I

= 50 mA

load

120 Hz < f < 10 kHz
VBATPac=1 Vpp

A-weighted filter

n

TS

HYS

VSTBY5

ESR

VSTBY5

VSTBY5

TS-

VSTBY5

Output noise

Thermal shut-down temperature

Hysteresis on thermal shut­down temperature

20 Hz < f < 20 kHz
I

= 5 mA

load

Temperature rising 150 - 190 °C

-5-15°C

External filtering capacitor ESR C > 0.5 µF - - 0.2 Ω

10/24 Doc ID 16819 Rev 2

=150mA -10 - +60 mV

--±5%

70 - - dB

--200µV

L5962 Electrical specification

Table 5. Electrical characteristics (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

VLR1 (5 V)

Vout

VLR1-5

LnR

VLR1-5

LdR

VLR1-5

Vdo

VLR1-5

Ishort

VLR1-5

OS/US

VLR1-5

PSRR

VLR1-5

n

VLR1-5

TS

VLR1-5

HYS

TS-VLR1-5

ESR

VLR1-5

VLR1 (8.5 V)

Vout

VLR1-8

LnR

VLR1-8

LdR

VLR1-8

Vdo

VLR1-8

Ishort

VLR1-8

OS/US

VLR1-8

PSRR

VLR1-8

n

VLR1-8

TS

VLR1-8

Output voltage 0 < I

Line regulation 6<VBAT<18 V I

Load regulation 0 < I

Drop out voltage I

load

< 350 mA 4.85 5 5.15 V

load

=350 mA -25 - +25 mV

load

< 350 mA -90 - - mV

load

= 350 mA - - 650 mV

Short circuit current limit - 500 650 850 mA

Overshoot/Undershoot

Power supply rejection ratio

load

C = 1 µF ceramic

I

= 170 mA

load

120 Hz < f < 10 kHz

--±3%

60 - - dB

0 ↔ 350 mA, t > 50µs

I

VBATac=1 Vpp

A-weighted filter

Output noise

Thermal shut-down
temperature

Hysteresis on thermal shut­down temperature

20 Hz < f < 20 kHz

= 5 mA

I

load

Temperature rising 150 - 190 °C

-5-15°C

--350µV

External filtering capacitor ESR C > 0.5 µF - - 0.2 Ω

Output voltage 0 < I

Line regulation 9.6<VBAT<18VI

Load regulation 0 < I

Drop out voltage I

load

< 350 mA 8.3 8.5 8.7 V

load

=350mA -25 - +25 mV

load

< 350 mA -90 - - mV

load

= 350 mA - - 650 mV

Short circuit current limit - 500 650 850 mA

0 ↔ 350 mA, t > 50µs

I

Overshoot / undershoot

Power supply rejection ratio

load

C = 1 µF ceramic

I

= 170 mA

load

120 Hz < f < 10 kHz
VBAT

=1 Vpp

ac

--±3%

60 - - dB

A-weighted filter

Output noise

Thermal shut-down
temperature

20 Hz < f < 20 kHz

= 5 mA

I

load

Temperature rising 150 - 190 °C

--350µV

HYS

ESR

TS-VLR1-8

VLR1-8

Hysteresis on thermal shut­down temperature

-5-15°C

External filtering capacitor ESR C > 0.5 µF - - 0.2 Ω

Doc ID 16819 Rev 2 11/24

Electrical specification L5962

Table 5. Electrical characteristics (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

VLR2 (3.3 V)

Vout

VLR2-3

LnR

VLR2-3

LdR

VLR2-3

Vdo

VLR2-3

Ishort

VLR2-3

OS/US

VLR2-3

PSRR

VLR2-3

n

VLR2-3

TS

VLR2-3

HYS

TS-VLR2-3

ESR

VLR2-3

VLR2 (10 V)

Output voltage 0 < I

Line regulation

4.5 < VINLR2 < 18 V

I

load

Load regulation 0 < I

Drop out voltage I

load

< 1 A 3.2 3.3 3.4 V

load

= 1 A

< 1 A -70 - - mV

load

-20 - +20 mV

= 1 A - - 1.2 V

Short circuit current limit 1.5 - 2.5 A

0 ↔ 1A, t > 50µs

I

Overshoot / undershoot

Power supply rejection ratio

load

C = 1 µF ceramic

I

= 500 mA

load

120 Hz < f < 10 kHz
VINLR2

=1 Vpp

ac

--±3%

60 - - dB

A-weighted filter

Output noise

Thermal shut-down
temperature

Hysteresis on thermal shut­down temperature

20Hz<f<20kHz
I

=5mA

load

--350µV

Temperature rising 150 - 190 °C

-5-15°C

External filtering capacitor ESR C>0.5µF - - 0.2 Ω

Vout

LnR

LdR

Vdo

Ishort

OS/US

PSRR

n

VLR2-10

TS

HYS

ESR

VLR2-10

VLR2-10

VLR2-10

VLR2-10

VLR2-10

VLR2-10

VLR2-10

VLR2-10

TS-VLR2-10

VLR2-10

Output voltage 0<I

Line regulation

Load regulation 0<I

Drop out voltage I

<1 A 9.7 10 10.3 V

load

11.4<VBAT<18 V
=1 A

I

load

<1 A -70 - - mV

load

=1 A - - 0.75 V

load

-25 - +25 mV

Short circuit current limit 1.5 - 2.5 A

Overshoot / undershoot

Power supply rejection ratio

load

C = 1 µF ceramic

I

= 500 mA

load

120 Hz<f<10 kHz

--±3%

60 - - dB

0 ↔ 1 A, t > 50 µs

I

VINLR2ac=1 Vpp

A-weighted filter

Output noise

Thermal shut-down
temperature

Hysteresis on thermal shut­down temperature

20 Hz < f < 20 kHz
I

= 5 mA

load

--350µV

Temperature rising 150 - 190 °C

-5-15°C

External filtering capacitor ESR C > 0.5 µF - - 0.2 Ω

12/24 Doc ID 16819 Rev 2

L5962 Electrical specification

Table 5. Electrical characteristics (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

HSD1

Vdrop

Ileak

Ishort

TS

HYS

HSD1

HSD1

HSD1

HSD1

TS-HSD1

Output saturation I

Leakage current

Short circuit current limit - 0.75 - 1.5 A

Thermal shut-down
temperature

Hysteresis on thermal shut­down temperature

HSD2

Vdrop

Ileak

Ishort

TS

HYS

HSD2

HSD2

HSD2

HSD2

TS-HSD2

Output saturation I

Leakage current

Short circuit current limit - 0.75 - 1.5 A

Thermal shut-down
temperature

Hysteresis on thermal shut­down temperature

Switching regulator

Vout

SW

Output voltage

= 0.5 A - - 500 mV

load

HSD off
output shorted to GND

--10µA

Temperature rising 150 - 190 °C

-5-15°C

= 0.5 A - - 500 mV

load

HSD off
output shorted to GND

--10µA

Temperature rising 150 - 190 °C

-5-15°C

Selectable through external
resistor divider

1.2 - 8 V

I

LOADmaxSW

f

sw

V

FB

Vdrop

SW

f

SYNC

η Efficiency

SR

SS

TS

SW

HYS

SW

V

decreasing of

outSW

(1)

1.2

2.5

­3

A

6

Load current limitation

100 mV
CLIM = 0 V

CLIM = 5 V

Free-run switching frequency - 150 180 210 kHz

FB voltage - 970 - 1030 mV

Dropout voltage

Switching frequency selectable
through SYNC pin

Soft-start pin slew rate C

Thermal shut-down
temperature

Hysteresis on thermal shut­down temperature

Vout
Iload

- 220 - 400 kHz

free run frequency
V

Temperature rising 150 - 190 °C

-5-15°C

SW

outSW

SOST

= 8 V
= 2.5 A

SW

= 8 V; I

= 10 nF

(1)

load

(1)

(1)

= 2.5 A

--1.2V

85 - - %

--10V/ms

Doc ID 16819 Rev 2 13/24

Electrical specification L5962

Table 5. Electrical characteristics (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Reset function

THR

HYS

Vsat

DLY

Tfall

Tglitch

THR

RSTDLY

I

RSTDLY

Controls

THR

HYS

leak

THR

CLIM

leak

CLIM

THR

LV WI N

HYST

2

I

C bus

RST

RST

RST

RST

RST

RST

EN

EN

EN

LV WI N

Reset threshold on VSTBY VSTBY = 3.3 V 93 - 98 %

Hysteresis on RST - 30 - 150 mV

RST pin saturation voltage I

= 0.5 mA - - 0.4 V

RST

RST delay time C = 100 pF on RSTDLY pin 25 - 75 µs

RST fall time

R = 47 kΩ
C = 50 pF

--1µs

Glitch filter time for RST - 5 - 20 µs

RSTDLY pin threshold RST falling 3 - 3.7 V

RSTDLY output current RSTDLY = Off 7 - 13 µA

EN minimum level recognized
as high

EN maximum level recognized
as low

-2--V

--0.8V

Hysteresis on EN - 150 - - mV

EN pin leakage current - -1 - 1 µA

-0.8--

CLIM pin threshold

V

--2

CLIM pin leakage current - -1 - 1 µA

LVWIN threshold - 1.225 - 1.275 V

LVWIN hysteresis - 100 - 200 mV

CLOCK minimum level
recognized as High

THR

SCL

CLOCK maximum level
recognized as low

DATA minimum level
recognized as High

THR

SDA

DATA maximum level
recognized as low

f

SCL

1. by bench characterization

Clock frequency - - - 400 kHz

-2.2--V

---0.8V

-2.2--V

---0.8V

14/24 Doc ID 16819 Rev 2

L5962 Device description

4 Device description

The IC includes one standby regulator, always active to guarantee the standby functions;
two switched linear regulators, managed by the I
regulator with selectable current limit.

4.1 Regulators

The VSTBY regulator is always active when the IC is supplied.

The other regulators can be enabled or disabled. Their outputs are automatically disabled
whenever the VBAT voltage exceeds the over-voltage shutdown threshold. Upon return from
over-voltage shutdown, the outputs recover without intervention from the system.

4.1.1 Linear regulators

VSTBY (3.3 V / 5.0 V standby)

VSTBY is a linearly regulated 3.3/5 V output. This output is enabled on battery connect. It is
supplied from the protected battery input (VBATP).

In order to select the 3.3 V output, the VSTBYSEL pin must be connected to ground.

In order to select the 5.0 V output, the VSTBYSEL pin must be connected to 5 V.

When the dropout voltage of the regulator cannot be maintained, the output shall track the
VBATP input voltage less the saturation voltage of the regulator pass element.

2

C bus and a step-down switching voltage

This regulator has a short circuit protection consisting of current limit, and thermal
shutdown. If the local die temperature exceeds the thermal shutdown detection threshold,
the output is disabled. The thermal shutdown circuitry has hysteresis such that the output is
enabled only after the die temperature falls below the thermal shutdown disable threshold.
Thermal shutdown on this output doesn't directly disable any other circuitry.

RST provides an indication that VSTBY is in regulation. It is an open drain output used to
indicate that VSTBY is in regulation (below the low-voltage threshold). RST remains low
until VSTBY achieves regulation and the RSTDLY input has charged to its threshold. For
instance, RST remains low during battery connect and disconnect and under low-voltage
battery lockout. The transition from standby mode to active mode (and vice versa) does not
cause the RST output to be triggered.

RSTDLY provides a means to delay the releasing of RST once VSTBY has achieved
regulation. It is used to delay the release of RST when VSTBY achieves regulation. This
input has a current source to charge an external capacitor and an internal pull-down to
discharge the external capacitor. The voltage on this capacitor is used to control the
operation of the RST output.

The RSTDLY pull-down is activated when a loss of regulation is detected. The input remains
low until VSTBY once again achieves regulation.

When the RSTDLY is released the current source charges the external capacitor. When the
voltage exceeds the pin's threshold, RST pin is also released, disabling its pull-down.

Doc ID 16819 Rev 2 15/24

Device description L5962

VLR1 (5.0 V /8.5 V) and VLR2 (3.3 V, 5.0 V, 5.5 V, 6.0 V, 7.0 V, 7.5 V, 8.0 V, 10.0 V)

The output of these two regulators can be selected through the I2C bus.

When the dropout voltage of the regulator cannot be maintained, the output tracks the VBAT
input voltage less the saturation voltage of the regulator pass element.

This regulator has a short circuit protection consisting of current limit and thermal shutdown.
If the local die temperature exceeds the thermal shutdown detection threshold, the output is
disabled. The thermal shutdown circuitry has hysteresis such that the output is enabled only
after the die temperature falls below the thermal shutdown disable threshold. Thermal
shutdown on this output doesn't directly disable any other circuitry.

VLR2 has its own power supply (VINLR2) because of its high current capability.

4.1.2 Switching regulator

The IC contains an independent, step-down, synchronous switching regulator, which is used
to produce an output voltage that is adjustable in the system by means of an external
resistor divider.

The switching regulator functionality is guaranteed in the 1.2-8.0 V output voltage range.
The switching frequency is externally synchronizable. The switcher has its own supply input
pin (VINSW) and is enabled by the EN input.

The regulator contains soft-start control to protect external devices from excessive in-rush
currents. This control is independent of the presence of a synchronizing signal on the
SYNCH input.

The switching cycle is synchronized to the internal oscillator unless a signal is present on
the SYNC input. The signal present on the SYNCH input overrides the internal oscillator to
control the switching of the regulator if its frequency gets inside the allowed range (220­400 kHz). The IC detects a small number of edges (e.g. 2-5) prior to recognize a valid input
signal and synchronizing internal operation to the external signal.

It is designed to operate in continuous conduction mode (CCM), where the inductor current
remains continuous throughout the entire load range of the output. It can also work in DCM
mode.

This regulator has short circuit protection consisting of cycle-by-cycle duty-cycle limitation.

Upon return from over-voltage shutdown this regulator employs the soft-start.

An external bootstrap capacitor must be connected between the output (PH, phase output
pin) and the CBS pin.

The switching regulator output slew rate can be controlled with an external capacitor on the
SOST (soft start) pin. This protects the device against excessive dV/dt transients, lowering
the stress of the internal components. A maximum slews rate of 10 V/ms is suggested.

Two separate current limits for the switching regulator can be chosen in order to guarantee a
proper protection for the device at the desired load current rating. The CLIM pin should be
tied to ground for the low limit (max 3 A) or to 5.0 V for the high limit (max 6 A).

The VFB pin is the voltage feedback from the regulated output for the switching regulator;
the VCMP one is the compensation feedback for the switching regulator.

16/24 Doc ID 16819 Rev 2

L5962 Device description

4.2 High side drivers

The device embeds fully-protected high-side drivers for use outside of the car-radio module.

HSD1, HSD2

These high side driver outputs have short circuit protections consisting of current limit and
independent thermal shutdown. If the local die temperature exceeds the thermal shutdown
detection threshold, the output is disabled. The thermal shutdown circuitry has hysteresis
such that the output is enabled only after the die temperature falls below the thermal
shutdown disable threshold. Thermal shutdown on any one output doesn't directly disable
any other circuitry.

HSD1 and HSD2 are protected from shorts to ground and shorts to battery (0-18 V) during a
loss of car-radio module battery.

Doc ID 16819 Rev 2 17/24

Operating mode L5962

5 Operating mode

When a power source is connected to the IC, the internal circuitry begins to establish
internal bias, the bandgap reference voltage, and other related functions. The standby
(VSTBY) regulator and battery detection are functional.

The standby mode is activated when the enable (EN) input is asserted low.

When the enable (EN) input is set high (EN =1: active mode.), the IC exits the standby mode
and enters the active mode.

During active mode, I2C interface is activated and all functions are operational. The IC
remains in active mode until either the standby regulator falls out of regulation (where the IC
enters the low-voltage reset state) or until the enable (EN) input is brought back to 0 V
(where the IC enters the standby state).

5.1 Battery detection

The operating voltage for VLR1, high side drivers and battery warnings is provided by VBAT
pin. This input is also used as reference to detect an over-voltage or an under-voltage
condition. When such condition is detected, the VBATVW output is pulled down. The
overvoltage detection circuit has hysteresis for noise rejection.

Two external resistors (Rext1, Rext2), whose values are lower than 100 kohm, are
connected to the LWIN (low warning input) pin to give the possibility to trim the threshold at
which the low voltage warning comparator triggers. When LVWIN voltage is below the input
voltage threshold (1.25 V typ), the VBATW (battery voltage warning) output is pulled down
and a low-voltage warning is indicated. When no external resistor network is connected to
LVWIN, the detector sets the threshold to a nominal 7.5 V.

No external interaction is required to reset the output state, because it is automatically reset
when the fault condition is removed.

Figure 4 shows an high level block diagram of the low-voltage warning circuit. VBAT is

divided by two internal resistors (Rint1, Rint2) and two external programming resistors
(Rext1, Rext2). When VBAT decreases so that LVWIN voltage gets lower than the internal
reference (VBG), VBATW is pulled down to ground.

Figure 4. Low voltage warning high level block diagram

VBAT

VBATW

Rext1

LVWIN

Rext2

Rint1=13.89 M ohm

comparator

VBG

Rint2 = 2.83M ohm

18/24 Doc ID 16819 Rev 2

L5962 I2C bus interface

6 I2C bus interface

Data transmission from microprocessor to the L5962 and viceversa takes place through the
2 wires I

2

C bus interface, consisting of the two lines SDA and SCL (pull-up resistors to

positive supply voltage must be connected).

6.1 Data validity

As shown by Figure 5, the data on the SDA line must be stable during the high period of the
clock. The HIGH and LOW state of the data line can only change when the clock signal on
the SCL line is LOW.

6.2 Start and stop conditions

As shown by Figure 6 a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH.

6.3 Byte format

Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.

6.4 Acknowledge

The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse (see Figure 6). The receiver** the acknowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the SDAline is stable LOW during this clock
pulse.

* Transmitter

– master (µP) when it writes an address to the L5962
– slave (L5962) when the µP reads a data byte from L5962

** Receiver

– slave (L5962) when the µP writes an address to the L5962
– master (µP) when it reads a data byte from L5962

Figure 5. Data validity on the I

SDA

SCL

2

C bus

DATA LINE

STABLE, DATA

VALID

CHANGE

DATA

ALLOWED

D99AU1031

Doc ID 16819 Rev 2 19/24

I2C bus interface L5962

Figure 6. Timing diagram on the I2C bus

SCL

2

CBUS

I

SDA

START

Figure 7. Acknowledge on the I

SCL

SDA

START

1

MSB

D99AU1032

2

C bus

23789

D99AU1033

STOP

ACKNOWLEDGMENT

FROM RECEIVER

20/24 Doc ID 16819 Rev 2

L5962 Software specifications

7 Software specifications

Table 6. Chip address

D7 (MSB)

D0 (LSB)

0001000R/W10 Hex

IC functions can be driven sending one data byte IB1

Table 7. IB1 data byte

Bit position Bit name Function description

D7 VLR2EN VLR2 enable

D6 VLR2SEL2 VLR2 selection

D5 VLR2SEL1

D4 VLR2SEL0

D3 VLR1EN VLR1 enable

D2 VLR1SEL VLR1 selection

D1 HSD2EN HSD2 enable

D0 HSD1EN HSD1 enable

Bits D6-D4 are used to select VLR2 output voltage according to the following table

Table 8. VLR2 output level selection

VLR2SEL2 VLR2SEL1 VLR2SEL0 VLR2 output voltage

0 0 0 3.3V

0 0 1 5.0V

0 1 0 5.5V

0 1 1 6.0V

1 0 0 7.0V

1 0 1 7.5V

1 1 0 8.0V

1 1 1 10.0V

Doc ID 16819 Rev 2 21/24

Package information L5962

8 Package information

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK

®

is an ST trademark.

Figure 8. PowerSO36 (slug-up) mechanical data and package dimensions

DIM.

A 3.270 - 3.410 0.1287 - 0.1343
A2 3.100 - 3.180 0.1220 - 0.1252
A4 0.800 - 1.000 0.0315 - 0.0394
A5 - 0.200 - - 0.0079 -

a1 0.030 -

b 0.220 - 0.380 0.0087 - 0.0150

c 0.230 - 0.320 0.0091 - 0.0126

D 15.800 - 16.000 0.6220 - 0.6299
D1 9.400 - 9.800 0.3701 - 0.3858
D2 - 1.000 - - 0.0394 -

E 13.900 - 14.500 0.5472 - 0.5709
E1 10.900 - 11.100 0.4291 - 0.4370
E2 - - 2.900 - - 0.1142
E3 5.800 - 6.200 0.2283 - 0.2441
E4 2.900 - 3.200 0.1142 - 0.1260

e - 0.650 - - 0.0256 -

e3 - 11.050 - - 0.4350 -

G 0 - 0.075 0 - 0.0031
H 15.500 - 15.900 0.6102 - 0.6260

h - - 1.100 - - 0.0433

L 0.800 - 1.100 0.0315 - 0.0433

N - - 10˚ - - 10˚

s - -8˚- -8˚

(1) “D and E1” do not include mold flash or protusions.

Mold flash or protusions shall not exceed 0.15mm (0.006”).

(2) No intrusion allowed inwards the leads.

mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

-0.040

0.0012 - -0.0016

OUTLINE AND

MECHANICAL DATA

PowerSO36 (SLUG UP)

22/24 Doc ID 16819 Rev 2

7183931 G

L5962 Revision history

9 Revision history

Table 9. Document revision history

Date Revision Changes

24-Nov-2009 1 Initial release.

10-Dec-2009 2

Updated Figure 8: PowerSO36 (slug-up) mechanical data and

package dimensions on page 22.

Doc ID 16819 Rev 2 23/24

L5962

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24/24 Doc ID 16819 Rev 2