The L4989M and L4989MD are monolithic
integrated 5 V voltage regulators with a low drop
voltage at currents up to 150 mA.
The output voltage regulating element consists in
a p-channel MOS and the regulation is performed
regardless of input voltage transients up to 40 V.
The high precision of the output voltage is
obtained with a pre-trimmed reference voltage.
Table 1.Device summary
Package
SO-8 L4989DL4989D013TR
SO-20L4989MDL4989MD013TR
The devices are protected against short circuit
and an overtemperature protection switches off
the devices in case of extremely high power
dissipation.
The L4989M and L4989MD watchdogs are active
when the Enable pin is high. Features like reset
and watchdog make this devices particularly
suitable to supply microprocessor systems in
automotive applications.
Order codes
TubeTape and reel
April 2012Doc ID 022376 Rev. 11/19
This is information on a product in full production.
L4989D, L4989MDBlock diagram and pin configuration
1 Block diagram and pin configuration
Figure 1.Block diagram
Table 2.Pins description
Pin nameSO-8(D)S0-20(MD)Function
WE
n
11
Watchdog Enable input
If high watchdog functionality is active
Gnd24Ground reference
Gnd5, 6, 15, 16
Ground.
Connected these pins to a heat spreader ground
Reset output.
Res37
It is pulled down when output voltage goes below V
or frequency at Wi is too low.
Reset timing adjust.
Vcr410
A capacitor between Vcr pin and gnd, sets the reset
delay time (t
)
rd
Watchdog timer adjust
Vcw511
A capacitor between Vcw pin and gnd, sets the time
response of the watchdog monitor.
Watchdog input.
Wi614
If the frequency at this input pin is too low, the Reset
output is activated.
o_th
Doc ID 022376 Rev. 15/10
Block diagram and pin configurationL4989D, L4989MD
Table 2.Pins description (continued)
Pin nameSO-8(D)S0-20(MD)Function
Voltage regulator output
V
o
717
Block to ground with a capacitor >100nF (needed for
regulator stability)
V
S
N.C.
820
2, 3, 8, 9, 12,
13, 18, 19
Supply voltage
Block to ground directly at IC pin with a capacitor
Not connected
Figure 2.Pins configuration (top view)
WEn
GND
Res
Vcr
1
2
SO-8
3
4
8
7
6
5
Vs
Vo
Wi
Vcw
WEn
N.C.
N.C.
GND
GND
GND
Res
N.C.
N.C.
Vcr
1
2
3
4
5
6
7
8
9
10
SO-20
20
19
18
17
16
15
14
13
12
11
GAPGCFT00666
Vs
N.C.
N.C.
Vo
GND
GND
Wi
N.C.
N.C.
Vcw
6/10Doc ID 022376 Rev. 1
L4989D, L4989MDElectrical specifications
2 Electrical specifications
2.1 Absolute maximum ratings
Table 3.Absolute maximum ratings
SymbolParameterValueUnit
V
I
V
V
V
Vsdc
Vsdc
V
Vo
I
Vo
V
Wi
V
od
I
od
V
cr
cw
WEn
T
ESD
j
DC supply voltage-0.3 to 40V
Input current Internally limited
DC output voltage-0.3 to 6V
DC output current Internally limited
Watchdog input voltage-0.3 to VVo + 0.3V
Open Drain output voltage-0.3 to VVo + 0.3V
Open Drain output currentInternally limited
Reset delay voltage-0.3 to VVo + 0.3V
Watchdog delay voltage-0.3 to VVo + 0.3V
Watchdog Enable input voltage-0.3 to 40V
Junction temperature-40 to 150“C
ESD voltage level (HBM-MIL STD 883C)±2kV
Note:Maximum ratings are absolute ratings; exceeding any one of these values may cause
permanent damage to the integrated circuit.
2.2 Thermal data
Table 4.Thermal data
SymbolParameterS0-8S0-12+4+4Unit
R
th-jamb
1. With 6 sq. cm on board heat sink.
Thermal resistance junction to ambient 130 to 18050
(1)
Doc ID 022376 Rev. 17/10
°C/W
Electrical specificationsL4989D, L4989MD
2.3 Electrical characteristics
VS = 5.6 V to 31 V, Tj= -40°C to +150°C unless otherwise specified.
Table 5.General
PinSymbolParameterTest conditionMin.Typ.Max. Unit
V
o
V
o
V
o
V
, V
S
V
o
VS, V
V
, V
S
, V
V
S
V
, V
S
V
, V
S
V
, V
S
V
, V
S
V
, V
S
V
, V
S
V
, V
S
V
o_ref
I
short_13
I
lim
V
o
o
o
line
V
load
V
dp
SVRRipple rejectionfr = 100 Hz 55dB
Output voltage
Short circuit currentVS= 13.5 V
Output current limitationVS= 13.5 V
Line regulation voltage
Load regulation voltageIo= 1 to 150 mA25mV
Drop voltageIo= 150 mA180400mV
Current consumption with
I
o
qs_1
watchdog not active
I
qs_1=IVS-Io
Current consumption with
I
o
qs_10
watchdog not active
I
qs_10=IVS-Io
Current consumption with
I
o
qs_50
watchdog not active
I
qs_50=IVS-Io
Current consumption with
I
o
qs_150
watchdog not active
I
qs_150=IVS-Io
Current consumption with
I
o
qn_1
watchdog active
I
qn_1=IVS-Io
Current consumption with
I
o
qn_10
watchdog active
I
qn_10=IVS-Io
Current consumption with
I
o
qn_50
watchdog active
I
qn_50=IVS-Io
Current consumption with
I
o
qn_150
Tw
watchdog active
I
qn_150=IVS-Io
Thermal protection
temperature
VS= 5.6 to 31 V;
I
= 1 to 150 mA
o
(1)
(1)
= 5.6 to 31 V;
V
S
= 1 to 150 mA
I
o
VS= 13.5 V;
I
<1mA;
o
=low
WE
n
VS= 13.5 V;
I
=10mA;
o
=low
WE
n
VS= 13.5 V;
I
=50mA;
o
=low
WE
n
VS= 13.5 V;
I
=150mA;
o
=low
WE
n
VS= 13.5 V;
I
<1mA;
o
=high
WE
n
VS= 13.5 V;
I
=10mA;
o
=high
WE
n
VS= 13.5 V;
I
=50mA;
o
=high
WE
n
VS= 13.5 V;
I
=150mA;
o
=high
WE
n
4.855.05.15V
160210250mA
170250290mA
69115µA
127300µA
498900µA
1.402mA
110170µA
168350µA
5381000µA
1.452mA
150190°C
25mV
Tw _hy
1. See Figure 3.
Thermal protection
temperature hysteresis
8/10Doc ID 022376 Rev. 1
10°C
L4989D, L4989MDElectrical specifications
T able 6.Reset
PinSymbolParameterTest conditionMin.Typ. Max. Unit
R
=5kΩ to Vo;
ResVres_lReset output low voltage
ResI
ResR
ResV
VcrV
VcrV
VcrI
VcrI
ResT
ResT
1. When Vo becomes lower than 4V, the reset reaction time decreases down to 2µs assuring a faster reset
condition in this particular case.
Res_lkg
Res
o_th
rlth
rhth
cr
dr
rr_2
rd
Reset output high leakage
current
Pull up internal resistance Versus V
Reset threshold voltage
Reset timing low thresholdVS= 13.5 V10%13%16%
Reset timing high threshold VS= 13.5 V44%47%50%
Charge currentVS= 13.5 V81530µA
Discharge currentVS= 13.5 V81530µA
Reset reaction time
(1)
Reset delay time
ext
V
>1V
o
=5V1µA
V
Res
o
= 5.6 to 31 V;
V
S
= 1 to 150 mA
I
o
Vo=V
o_th
= 13.5 V;
V
S
Ctr = 1 nF
-100 mV100250700µs
102050kΩ
6%8%10%
65115165ms
0.4V
Below
V
o_ref
V
o_ref
V
o_ref
Table 7.Watchdog
PinSymbolParameterTest conditionMin.Typ.Max. Unit
WiVihInput high voltageV
WiVilInput low voltageV
WiVihInput hysteresisV
= 13.5 V3.5V
S
= 13.5 V1.5V
S
= 13.5 V500mV
S
WiRwiPull down resistorVS= 13.5 V30100250KΩ
VcwVwhthHigh thresholdV
= 13.5 V44%47%50%
S
VcwVwlthLow thresholdVS= 13.5 V10%13%16%
= 13.5 V;
V
VcwIcwcCharge current
VcwIcwdDischarge current
VcwTwopWatchdog period
RestwolWatchdog output low time
S
Vcw = 0.1 V
= 13.5 V;
V
S
Vcw = 2.5 V
= 13.5 V;
V
S
Ctw = 47 nF
= 13.5 V;
V
S
Ctw = 47 nF
51020µA
1.252.55µA
204080ms
4816ms
V
V
o_ref
o_ref
Doc ID 022376 Rev. 19/10
Electrical specificationsL4989D, L4989MD
Table 8.Watchdog Enable
PinSymbolParameterTest conditionMin.Typ. Max. Unit
WE
WE
WE
WE
V
n
n
n
n
WEn_l
V
WEn_h
V
WEn_hy
I_leakPull down currentVS= 13.5 V12.55µA
Enable input low voltage1V
Enable input high voltage3V
Enable input hysteresis6009201300mV
10/10Doc ID 022376 Rev. 1
L4989D, L4989MDApplication information
Vo
Vo_ref
IoutIshort Ilim
3 Application information
3.1 Voltage regulator
The voltage regulator uses a p-channel MOS transistor as a regulating element. With this
structure a very low dropout voltage at current up to 150 mA is obtained. The output voltage
is regulated up to transient input supply voltage of 40 V. No functional interruption due to
over-voltage pulses is generated.The voltage Regulator is always active and not depending
on the state of WE
input pin. A short circuit protection to GND is provided.
n
Figure 3.Behavior of output current versus regulated voltage V
3.2 Reset
The reset circuit supervises the output voltage Vo. The V
the in-ternal reference voltage and a resistor output divider. If the output voltage becomes
lower than V
guaranteed for an output voltage V
When the output voltage becomes higher than V
This delay is obtained by an internal oscillator.
The oscillator period is given by:
T
osc
where:
I
cr
I
dr
V
rhth
C
tr
t
is given by:
rd
t
rd
The Reset is always active and not depending on the state of WEn input pin.
reset threshold is defined with
o_th
then Res goes low with a reaction time trr. The reset low signal is
o_th
= [(V
rhth-Vrlth
) x Ctr] / Icr + [(V
greater than 1 V.
o
o_th
rhth-Vrlth
) x Ctr] / I
then Res goes high with a delay trd.
dr
:is an internally generated charge current
:is an internally generated discharge current
, V
:are two voltages defined with the output voltage and a resistor output
rlth
divider
:is an external capacitance.
= 512 x T
osc
o
Doc ID 022376 Rev. 111/10
Application informationL4989D, L4989MD
TRR
TRR
TRD4 OSC
4OSC
6RHTH
6RLTH
2ES
6CR
6O
7I
6OUT?TH
'!0'#&4
7I
6CW
2ES
6WLTH
6WHTH
TWOP
TWOL
6WLTH
("1($'5
Figure 4.Reset timing diagram
3.3 Watchdog
A connected microcontroller is monitored by the watchdog input Wi. If pulses are missing,
the Reset output pin is set to low. The pulse sequence time can be set within a wide range
with the external capacitor, C
constant current I
. If the lower threshold V
cwd
To prevent this the microcontroller must generate a positive edge during the discharge of the
capacitor before the voltage has reached the threshold V
minimum time t, during which the micro-controller must output the positive edge, the
following equation can be used:
Every Wi positive edge switches the current source from discharging to charging. The same
happens when the lower threshold is reached. When the voltage reaches the upper
threshold, V
, the current switches from charging to discharging. The result is a saw-tooth
whth
voltage at the watchdog timer capacitor C
. The watchdog circuit discharges the capacitor Ctw, with the
tw
(V
whth-Vwlth
is reached, a watchdog reset is generated.
wlth
. In order to calculate the
wlth
tw
.
) x Ctw = I
cwd
x t
Figure 5.Watchdog timing diagram
12/10Doc ID 022376 Rev. 1
L4989D, L4989MDPackage and packing information
'!0'#&4
4 Package and packing information
4.1 ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
4.2 SO-8package information
Figure 6.SO-8 package dimensions
Doc ID 022376 Rev. 113/10
Package and packing informationL4989D, L4989MD
T able 9.SO-8 mechanical data
Symbol
Min.Typ.Max.
A1.75
A10.100.25
A21.25
b0.280.48
c0.170.23
(1)
D
4.804.905.00
E5.806.006.20
(2)
E1
3.803.904.00
e1.27
h0.250.50
L0.401.27
Millimeters
L11.04
k0°8°
ccc0.10
1. Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs
shall not exceed 0.15mm in total (both side).
2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25mm per side.
14/10Doc ID 022376 Rev. 1
L4989D, L4989MDPackage and packing information
4.3 SO-20 package information
Figure 7.SO-20 package dimensions
T able 10.SO-20 mechanical data
Symbol
Min.Typ.Max.
A2.352.65
A10.100.30
B0.330.51
C0.230.32
(1)
D
12.6013.00
E7.407.60
e1.27
H10.010.65
h0.250.75
L0.401.27
k0°8°
ddd0.10
Millimeters
1. “D” dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs
shall not exceed 0.15mm per side.
Doc ID 022376 Rev. 115/10
Package and packing informationL4989D, L4989MD
All dimensions are in mm.
Base Q.ty100
Bulk Q.ty2000
Tube length (± 0.5)532
A3.2
B6
C (± 0.1)0.6
C
B
A
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Figure 11.SO-20 tape and reel shipment (suffix “TR”)
Doc ID 022376 Rev. 117/10
Revision historyL4989D, L4989MD
5 Revision history
Table 11.Document revision history
DateRevisionChanges
16-Apr-20121
Initial release.
This document replace the L4989 datasheet.
18/10Doc ID 022376 Rev. 1
L4989D, L4989MD
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