The L4976 is a step down monolithic power
switching regulator delivering 1A at a voltage
between 3.3V and 50V (selected by a simple
external divider). Realized in BCD mixed
technology, the device uses an internal power DMOS transistor (with a typical R
obtain very high efficency and high switching
speed. A switching frequency up to 300KHz is
achievable (the maximum power dissipation of the
packages must be observed). A wide input
voltage range between 8V to 55V and output
voltages regulated from 3.3V to 40V cover the
majority of today’s applications. Features of this
new generations of DC-DC converter include
pulse-by-pulse current limit, hiccup mode for short
circuit protection, voltage feedforward regulation,
protection against feedback loop disconnection
and thermal shutdown. The device is available in
plastic dual in line, MINIDIP 8 for standard
assembly, and SO16W for SMD assembly.
2 3 VREF 5.1V Reference voltage with 20mA current capability.
3 4 OSC
SO16W
(1)
N.C.
FB8
COMP
7
BOOT
6
5
NameDescription
An external resistor connected between the unregulated
input voltage and this pin and a capacitor connected
from this pin to ground fix the switching frequency. (Line
feed forward is automatically obtained)
GND
REF
V
OSC
OUT
OUT
N.C.
N.C.N.C.
2
3
4
5
6
7
8
SO16
16
15
14
13
12
11
10
N.C.1
N.C.
FB
COMP
BOOT
VCC
N.C.
9
4 5, 6 OUT Stepdown regulator output.
5 11 VCC Unregulated DC input voltage.
6 12 BOOT
7 13 COMP E/A output to be used for frequency compensation.
8 14 FB
1. Pins 1, 7, 8, 9, 10, 15 and 16 are not internally, electrically connected to the die.
4/17
A capacitor connected between this pin and OUT allows
to drive the internal VDMOS.
Stepdown feedback input. Connecting directly to this pin
results in an output voltage of 3.3V. An external resistive
divider is required for higher output voltages.
Figure 8.Load regulationFigure 9.Switching frequency vs. input
V
O
D97IN733
(V)
3.377
Tj=125˚C
3.376
fsw
(KHz)
107.5
105.0
voltage
D97IN735
3.375
3.374
Tj=25˚C
3.373
3.372
3.371
3.370
0 5 10 15 20 25 30 35 40 45 50 VCC(V)
Figure 10. Switching frequency vs.
fsw
(KHz)
105
100
95
junction temperature
D97IN785
102.5
Tj=25˚C
100.0
97.5
95.0
92.5
90.0
0 5 10 15 20 25 30 35 40 45 50 VCC(V)
Figure 11. Efficiency vs. output current
∆
(V)
0.5
0.4
0.3
0.2
0.1
V
D97IN736
Tj=125˚C
Tj=25˚C
Tj=-25˚C
90
-50050100Tj(˚C
Figure 12. Dropout voltage between pin 5
∆
V
(V)
0.5
0.4
0.3
0.2
0.1
0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 IO(A)
and 4
D97IN736
Tj=125˚C
Tj=25˚C
Tj=-25˚C
9/17
0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 IO(A)
Figure 13. Efficiency vs. output current
η
(%)
90
85
VCC=12V
VCC=8V
VCC=24V
80
75
VCC=48V
70
65
60
00.2 0.4 0.6 0.8 1.0 1.2 1.4 IO(A)
D97IN739
fsw=100KHz
=3.36V
V
O
Typical charcteristicsL4976
)
Figure 14. Efficiency vs output voltageFigure 15. Efficiency vs. output current
(%)
96
94
92
90
88
86
84
η
D97IN737
η
(%)
100KHz
200KHz
VCC=35V
IO=1.5A
90
85
80
75
VCC=12V
VCC=24V
VCC=48V
70
65
VCC=8V
fsw=200KHz
=5.1V
V
O
D97IN740
82
0510152025VO(V)
Figure 16. Efficiency vs. output currentFigure 17. Efficiency vs. Vo
(%)
90
η
VCC=8V
D97IN741
60
00.2 0.4 0.6 0.8 1.0 1.2 1.4 IO(A)
Pdiss
(mW)
VCC=35V
fsw=100KHz
800
85
80
VCC=12V
VCC=24V
600
75
70
65
VCC=48V
fsw=200KHz
V
60
55
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 IO(A)
Figure 18. Efficiency vs. V
CC
=3.36V
O
400
200
0
051015202530 V0(V)
Figure 19. Pulse by pulse limiting
current vs. junction
=
2
SW
=100KHz
00KHz
D97IN742
η
(%)
85
80
75
IO=1.5A
V
=5.1V-f
0
V
0
=5.1V-f
V
V
0
=3.36V-f
SW
SW
=3.36V-f
0
SW
=100KHz
=200KHz
Ilim
(A)
2.9
2.8
2.7
2.6
2.5
2.4
temperature.
fsw=100KHz
V
=35V
CC
D97IN744
IO=1.5A
IO=1A
IO=0.5A
D97IN747
70
0 1020304050VCC(V)
10/17
2.3
-50 -25025 5075 100 125 Tj(˚C
L4976Typical charcteristics
)
Figure 20. Power dissipation vs. V
Pdiss
CC
D97IN743
Figure 21. Load transient
(mW)
VO=5.1V
fsw=100KHz
800
600
IO=1.5A
IO=1A
400
IO=0.5A
200
0
0 1020304050VCC(V)
Figure 22. Line transientFigure 23. Open loop frequency and
V
CC
D97IN786
(V)
30
20
10
V
1
IO = 1A
f
= 100KHz
sw
2
1ms/DIV
O
(mV)
100
0
-100
GAIN
(dB)
50
0
-50
-100
-150
-200
1010
phase of error amplifier
Phase
10
3
2
10
5
4
10
10
6
GAIN
10
7
D97IN787
8
10
f(Hz
Phase
0
45
90
135
11/17
Package mechanical dataL4976
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
12/17
L4976Package mechanical data
Figure 24. DIP8 mechanical data & package dimensions
DIM.
mminch
MIN.TYP. MAX. MIN.TYP. MAX.
A3.320.131
a10.510.020
B1.151.65 0.0450.065
b0.3560.55 0.0140.022
b10.2040.304 0.0080.012
D10.920.430
E7.959.75 0.3130.384
e2.540.100
e37.620.300
e47.620.300
F6.60.260
I5.080.200
L3.183.81 0.1250.150
Z1.520.060
OUTLINE AND
MECHANICAL DATA
DIP-8
13/17
Package mechanical dataL4976
Figure 25. SO16Wide mechanical data & package dimensions
DIM.
A2.352.650.0930.104
A10.100.300.0040.012
B0.330.510.0130.200
C0.230.320.0090.013
(1)
D
E7.407.60 0.2910.299
e1.270.050
H10.010.65 0.3940.419
h0.250.750.0100.030
L0.401.270.0160.050
k0˚ (min.), 8˚ (max.)
ddd0.100.004
(1) “D” dimension does not include mold flash , protusions or gate
burrs. Mold flash, p rotusions o r gate bur rs shall not exceed
0.15mm per side.
mminch
MIN.TYP. MAX. MIN.TYP. MAX.
10.1010.50 0.3980.413
OUTLINE AND
MECHANICAL DATA
SO16 (Wide)
14/17
0016021 C
L4976Order code
7 Order code
Table 6. Order code
Part numberPackagePackaging
L4976DIP8Tube
L4976DSO16WTube
L4976D013TRSO16WTape and reel
15/17
Revision historyL4976
8 Revision history
Table 7. Revision history
DateRevisionChanges
5-Aug-20016First Issue
3-Apr-20077
Document reformatted, updated dropout voltage values in Ta b le 5 o n
page 6
16/17
L4976
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