ST ISA051V2 User Manual
Complete DDR2/3 memory power supply controller
evaluation board based on the PM6670AS
Features
■ 4.5 V to 36 V input voltage range
■ 0.9 V, ±1% voltage reference
■ 1.8 V (DDR2) or 1.5 V (DDR3) fixed output
voltages
■ 0.9 V to 2.6 V adjustable output voltage
■ 1.237 V ±1% reference voltage available
■ Very fast load transient response using
constant on-time loop control
■ No R
of the low-side MOSFETs
■ Negative current limit
■ Latched OVP, UVP and thermal shutdown
■ Fixed 3 ms soft-start
■ Selectable pulse-skipping at light load
■ Selectable no-audible (33 kHz) pulse-skip
mode
■ All ceramic output capacitors application
supported
■ Output voltage ripple compensation
current sensing using the R
SENSE
DS(on)
STEVAL-ISA051V2
Data Brief
STEVAL-ISA051V2
The device is fully compliant with system sleep
states S3 and S4/S5, providing LDO output high
impedance in suspend-to-RAM and tracking
discharge of all outputs in suspend-to-disk.
Description
This evaluation board based on the PM6670AS
device is a complete DDR2/3 power supply
regulator for portable applications designed to
meet JEDEC specifications. It integrates a
constant on-time (COT) buck controller, a 2 Apk
sink/source low dropout regulator and a 15 mA
low noise buffered reference.
The COT architecture assures fast transient
response supporting both polymeric and ceramic
output capacitors. An embedded integrator
control loop compensates the DC voltage error
due to the output ripple. The 2 Apk sink/source
linear regulator provides the memory termination
voltage with fast load transient response.
March 2008 Rev 1 1/4
For further information contact your local STMicroelectronics sales office.
www.st.com
4
Circuit schematic STEVAL-ISA051V2
DD
ASE
PG
SC
EF
EF
DDR
SEL
PD
66
AS
CC
60
BA
33
18
20
20
10
100
00
10
10
80
10
00
ND
PG
10
P2
DR
10
27
18
TT
EF
1 Circuit schematic
Figure 1. Schematic
Q
J1
VIN
1
C2
10u
12
12
C1
10u
n
100
C14
12
12
k
18
R2
D1
21
10u
R7
12
C5
12
8
7
6
5
L
Q1
STS5NF60
T41J
BA
12
3R9
1u
1
J9
GND
VCC
0k
R1 33
1 2
VCC
C11
12
VCC
1
J5
VCC
J2
VDD
1
C4
C3
R6
0
0
L1 1u
0
0
1 2
8
7
3
6
2
5
1
4
R4 3R3
1 2
n
100
0
1 2 C13
R3 1k5
1 2
C20
12
C19
12
C7
12
C6
12
VCC
19
20
21
22
23
24
U1
10u
10u
u
10
u
10
100n
C12
R10
0
0
12
12
VTT
THPD
25
STPSPS1L1L60A
D3
2 1
u
220
u
220
1 2
C15 47n
1n
R14 7.5k R15 6.8k
R17 0
0
18
VCC
CSNS
PHASE
HGATE
BOOT
LDOIN
VTTGND
1
0
C18
4R7
R16
12
STPSPS1L1L60A
D2
2 1
3
2
1
Q2
STS7NF60L
4
VCC
0k
0k
R12 10
R11 10
1 2
1 2
p
100
C21
15
17
14
16
PG
PGND
LGATE
70AS
PM66
SEL
VTTSNS
DDR
VTTREF
4
3
5
2
DSCG
13
S5
S3
DSCG
12
COMP
11
MODE
10
VSVSNS
9
VOSC
8
VREF
7
SGND
AVCC
6
12
0n
10
C10
12
0
0
C8
1
1
J7
J6
VTT
LDOIN
12
1
J8
REF
VTT
J3
PGND
PG
J4
1
1
_TP
TP1
GND
12
0k
R13
10
SW1
2
3
1
4
100p
C22
1 2
0
1 2
JP2
5 6
3 4
1 2
MODE
JP3
k
R9
18
C9
JP5
INT_CER
p
0
1 2
C16 680
0
12
C17
0
0
k
27
R8
0
0
SEL
DDR
JP1
5 6
3 4
1 2
33n
0
1
J10
AGND
0
1
J11
AGND
2/4
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