
Complete DDR2/3 memory power supply controller
evaluation board based on the PM6670S
Features
■ 4.5 V to 28 V input voltage range
■ 0.9 V, ±1% voltage reference
■ 1.8 V (DDR2) or 1.5 V (DDR3) fixed output
voltages
■ 0.9 V to 2.6 V adjustable output voltage
■ 1.237 V ±1% reference voltage available
■ Very fast load transient response
■ Constant on-time loop control
■ No R
of the low-side MOSFETs
■ Negative current limit
■ Latched OVP, UVP and thermal shutdown
■ Fixed 3 ms soft-start
■ Selectable pulse-skipping at light load
■ Selectable no-audible (33 kHz) pulse-skip
mode
■ All ceramic output capacitors application
supported
■ Output voltage ripple compensation
current sensing using the R
SENSE
DS(on)
STEVAL-ISA051V1
Data Brief
STEVAL-ISA051V1
The device is fully compliant with system sleep
states S3 and S4/S5, providing LDO output high
impedance in suspend-to-RAM and tracking
discharge of all outputs in suspend-to-disk.
Description
This evaluation board is based on the PM6670S
and represents a complete DDR2/3 power supply
regulator for portable applications designed to
meet JEDEC specifications. It integrates a
constant on-time (COT) buck controller, a 2 Apk
sink/source low drop-out regulator and a 15 mA
low noise buffered reference. The COT
architecture assures fast transient response
supporting both polymeric and ceramic output
capacitors. An embedded integrator control loop
compensates the DC voltage error due to the
output ripple. The 2 Apk sink/source linear
regulator provides the memory termination
voltage with fast load transient response.
February 2008 Rev 1 1/4
For further information contact your local STMicroelectronics sales office.
www.st.com
4

Circuit schematic STEVAL-ISA051V1
1 Circuit schematic
Figure 1. Schematic
1
VOUT_1S5
TP10
k
6
7
8
SW1
SW DIP-4
123
4 5
k
-68
R23
0603
k
-68
AUX
R22
0603
k
-68
0603
AUX
1
TP18
AUX
n
03-joi
R34
06
JP3
STRIP 3
2/4
1
TP16
AGND
1
TP14
VTT
1
TP1
VTTREF
CC
2
AV
JP1
STRIP 3
1
TP15
LDOIN
1
AGND
TP6
1
TP5
VCC
2
AVCC
R3
03-4
R2
06
C17
1 3
R3
03-4
R1
06
C1
VCC
R21
68k
0603-
R20
1 3
u
-22
1206
C11
2
1
00n
0603-1
AVCC
-1u
0603
n
-33
0603
C18
03-100n
06
C16
S8
1
TP9
VOUT_1
0p
03-10
06
C28
03-100p
06
C27
3-100p
060
C26
p
-100
0603
C25
VIN
C3
AVCC
u
-10
C12
0805
AVAVCC
1
JP8
AVAVCC
1
JP7
-join
0603
R33
k
-68
R4
0603
2
STRIP 2
k
-100
R3
0603
2
STRIP 2
0k
0k
3-15
3-12
R5
R6
060
060
JP4
STRIP 3
1 3
2
-100
R7
0603
+
12
u
-10
0805
37
38
39
40
41
42
43
44
45
46
47
48
VTT
C5
+
12
5
-1u
2839
L2
1 2
35
S5
EN_VTT36EN_1
EN_1S8
AGNDND_3
SESET_PH1
AGNDND_2
AVCC
VTT_GND
LDO_IN
VTTREF
DSCG
VTT_FB
VCC
_1
T_SWF
SE
AGND
2
1
B Case - 220u
C15
u
C6
B Case - 220
u
EL SMD C-10
TP8
GND
1
GND
TP11
k
-120
R8
0603
JP5
STRIP 3
1 3
2
u
C8
EL SMD C-10
p
-100
0603
C30
B Case - 220u
C7
470p
C23
0603-
5p
03-1
C34
06
47k
R12
0603-
34
29
32
30
28
31
33
27
1
2
2
1
S5
S5
S5
S05
S5_
S5_
S5_
S5_
VIN_1
VFB_1
EN_1
W_1
W_1
COMP_1
VS
VS
SGND_1
SGND_1
FPN
U1
41_Q
PM66
1
2
_1S8_1
_1S8_2
W_1S8_
W_1S8_
VOUT_1S8
SGND
VS
VIN_1S8_2
CSNS
SGND
VS
VIN_1S8_1
6
8
4
9
5
3
7
10
1u
2
2839-
L1
1
0u
05-1
C2
08
1
3-22n
C20
060
25
26
S5
S5
SS_1
PG_1
PG_1_1S8
24
PG_1_1S05
23
VIN_1_1S05_2
22
VIN_1_1S05_1
21
VSW_1S05_5_2
20
VSW_1S05_5_1
19
SGNDND_1_1S05_2
18
SGNDND_1_1S05_1
17
VFB_1_1S05
16
COMP_1S05
15
SS_1S05
14
SS_1S8
13
COMP_1S8
VFB_1S8
THERMAL
11
12
49
n
03-joi
R32
06
p
C19
-15
0603
C32
k
p
-100
VIN
-330
0603
0603
R11
C22
0p
03-10
06
C29
S05
1
PG_1
TP4
1
TP2
PG_1S8
1
TP3
PG_1S5
3-68k
R19
060
3-68k
AUX
060
R18
68k
R17
0603-
VIN
TP7
1
n
-joi
R30
0603
u
12
+
C14
TP17
EL SMD C-10
u
05-10u
VIN
08
C4
C13
EL SMD C-10
+
12
u
C10
9-1u
283
L3
1 2
00p
0603-1
C31
p
-15
0603
C33
68k
330p
R13
0603-
C24
0603-
n
C21
-22
0603
03-22n
06
TP13
B Case - 220
C9
B Case - 220u
TP12
56k
R9
0603-
VCC
GND
1
n
R31
0603-joi
1
GND
1
VOUT_1S05
180k
0603-
R10
STRIP 3
JP6
1 3
2

STEVAL-ISA051V1 Revision history
2 Revision history
Table 1. Document revision history
Date Revision Changes
11-Feb-2008 1 Initial release.
3/4

STEVAL-ISA051V1
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