
Monolithic VR for chipset and DDR2/3 demonstration board
Features
■ Switching section
– 0.8 V ±1% voltage reference
– 2.7 V to 5.5 V input voltage range
– Fast response, constant frequency, current
mode control
– Three independent, adjustable, SMPS For
DDR2/3 (VDDQ) and chipset supply
– S3-S5 states compliant DDR2/3 section
– Active soft-end for all outputs
– Selectable tracking discharge for VDDQ
– Separate Power Good signals
– Pulse skipping at light load
– Programmable current limit and soft-start
for all outputs
– Latched OVP, UVP protection
– Thermal protection
■ Reference and termination voltages (VTTREF
and VTT)
– ±2 Apk LDO for DDR2/3 termination (VTT)
with fold back
– Remote VTT output sensing
– High-Z VTT output in S3
– ±15 mA low noise DDR2/3 buffered
reference (VTTREF)
STEVAL-ISA050V1
based on the PM6641
Data Brief
STEVAL-ISA050V1
±15 mA low noise buffered reference. Each
regulator is provided of basic under voltage (UV)
and over voltage (OV) protections, programmable
soft-start and current limit, active soft-end and
pulse-skipping at light loads.
Application
■ Supply for ultra-mobile PC (UMPC)
Description
The STEVAL-ISA050V1 demonstration board is
based on the PM6641, that is a monolithic voltage
regulator module, with internal Power MOSFET,
specifically designed to supply DDR2/3 memory
and chipset in ultra-mobile PC and real estate
portable systems. It integrates three independent,
adjustable, constant frequency buck converters, a
±2 Apk low drop-out (LDO) linear regulator and a
November 2008 Rev 1 1/4
For further information contact your local STMicroelectronics sales office.
www.st.com
4

Circuit schematic STEVAL-ISA050V1
1 Circuit schematic
Figure 1. Schematic
1
TP1010VOUT_1S5
k
6
7
8
SW DIP-4
SW1
123
4 5
k
-68
R23
0603
k
-68
AUX
R22
0603
k
-68
0603
AUX
1
TP1818AUX
n
03-joi
R34
06
2/4
1
TP16
AGND
1
TP1414VTT
1
TP1
VTTREF
CC
2
AV
JP1
STRIP 3
1
TP1515LDOIN
1
AGND
TP6
1
VCC
TP5
STRIP 3
JP3
2
AVCC
R3
03-4
06
R2
C17
1 3
R3
03-4
R1
06
C1
VCC
R21
68k
0603-
R20
1 3
u
-22
1206
C11
2
1
00n
n
-33
0603-1
0603
C18
AVCC
C16
-1u
0603
03-100n
06
S8
1
TP9
VOUT_1
0p
03-10
06
C28
03-100p
06
C27
3-100p
060
C26
p
-100
0603
C25
VIN
C3
AVCC
u
-10
0805
C12
-join
R33
0603
k
-68
R4
AVAVCC
JP8
AVAVCC
JP7
0603
1
2
STRIP 2
k
-100
R3
0603
1
2
STRIP 2
0k
0k
3-15
3-12
R5
R6
060
060
JP4
STRIP 3
1 3
2
-100
R7
0603
+
12
u
-10
0805
37
38
39
40
41
42
43
44
45
46
47
48
12
5
-1u
2839
L2
1 2
35
S5
EN_VTT36EN_1
EN_1S8
AGNDND_3
SESET_PH1
AGNDND_2
AVCC
VTT_GND
VTT
LDO_IN
VTTREF
DSCG
VTT_FB
VCC
T_SWF
AGND_1
SE
2
1
B Case - 220u
C15
u
C6
B Case - 220
C5
EL SMD C-10u
+
GND
TP8
k
-120
R8
0603
JP5
C8
EL SMD C-10u
B Case - 220u
C7
34
32
33
S5
S05
VIN_1
EN_1
U1
VOUT_1S83CSNS4SGND_1S8_15SGND_1S8_26VS
1
1
TP11
GND
S05
1
PG_1
TP4
1
STRIP 3
1 3
2
p
-100
0603
C30
470p
C23
0603-
5p
03-1
C34
06
47k
R12
0603-
27
30
29
31
28
2
1
S5
S5_1
S5_2
S5_
S5_
VFB_1
W_1
W_1
VS
VS
SGND_1
SGND_1
FPN
41_Q
PM66
W_1S8_1
W_1S8_2
VIN_1S8_1
VS
8
7
9
10
1u
2
2839-
L1
1
0u
05-1
C2
08
3-22n
C20
060
25
26
S5
S5
S5
SS_1
PG_1
COMP_1
PG_1_1S8
24
PG_1_1S05
23
VIN_1_1S05_2
22
VIN_1_1S05_1
21
VSW_1S05_2
20
VSW_1S05_1
19
SGNDND_1_1S05_2
18
SGNDND_1_1S05_1
17
VFB_1_1S05
16
COMP_1S05
15
SS_1S05
14
SS_1S8
VIN_1S8_2
13
VFB_1S811COMP_1S8
THERMAL
12
49
n
03-joi
R32
06
p
-15
0603
C32
k
p
-100
VIN
-330
0603
0603
R11
C22
0p
03-10
06
C29
TP2
PG_1S8
1
TP3
PG_1S5
3-68k
R19
060
3-68k
AUX
R18
060
68k
0603-
R17
VIN
TP7
n
1
-joi
0603
R30
1
+
u
C14
EL SMD C-10u
TP1717GND
2
05-10u
VIN
08
C4
C13
EL SMD C-10
u
+
12
C10
9-1u
283
L3
1 2
00p
0603-1
C31
p
-15
0603
C33
330p
68k
R13
0603-
0603-
C24
n
-22
C21
0603
C19
03-22n
06
TP1313GND
B Case - 220
C9
B Case - 220u
TP1212VOUT_1S05
56k
R9
0603-
VCC
1
n
R31
0603-joi
1
1
180k
0603-
R10
JP6
STRIP 3
1 3
2
AM03286v1

STEVAL-ISA050V1 Revision history
2 Revision history
Table 1. Document revision history
Date Revision Changes
12-Nov-2008 1 Initial release.
3/4

STEVAL-ISA050V1
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