ST IFP006V1 User Manual
Quad high side smart power solid state relay evaluation board
Features
■ Shorted load protections
■ Junction over-temperature protection
■ Case over-temperature protection for thermal
independence of the channels
■ Thermal case shut-down non-simultaneous
restart for the various channels
■ Protection against loss of ground
■ Current limitation
■ Undervoltage shut-down
■ Open drain diagnostic outputs
■ 3.3 V CMOS/TTL compatible inputs
■ Fast demagnetization of inductive loads
■ Conforms to IEC 61131-2
STEVAL-IFP006V1
using the VNI4140K
Data Brief
STEVAL-IFP006V1
Description
The purpose of this design is to demonstrate the
features of the VNI4140K quad high side smart
power solid state relay. The application offers
robustness and complies with EMC industrial
standards. It implements short-circuit/overload
protection and thermal management as well,
achieving best-in-class MTBF values. The
reference design is suitable for use in
programmable logic controllers (PLCs) as well as
to drive generic loads which require up to 0.7 A of
nominal current (the typical current limitation is
0.7 - 1.7 A). Thanks to the very low R
80 mΩ typ. @ 25 °C per channel) the device
allows very low power consumption during
operation and for this reason making it an ideal
solution for IP65 / IP67 requirements. The device
is compliant with IEC 61131-2 (Programmable
Controllers International Standard).
DS(on)
(only
December 2007 Rev 1 1/8
For further information contact your local STMicroelectronics sales office.
www.st.com
8
Board schematic STEVAL-IFP006V1
1 Board schematic
Figure 1. Schematic diagram
B
OUT4
OUT3
OUT1
OUT2
M1
M.4VITEB
123
4
T3
T4
C3
10nF LV
1206
10nF LV
1206
13
STAT1
STAT37STAT4
STAT2
3
9
5
1206
GND
VNI4140K
DL1
DL2
DL3
DL4
6
LED
LED
LED
LED
10nF LV
RR1
C4
10K 1206
J3
GND DISC. TEST
A B
T11
T10
T9
OPEN
+
J2
FOR
J4
GND
+24Vdc
1
2
A B
OVL TEST
C6
C5
Vcc DISC. TEST
A B
47uF
100nF
OR
C
M2
M.2VITEB
D1
SM15T39AC
1206
IC1
CURRENT PROBE
Vcc
TAB
Vcc
1
T1
OUT1_a24OUT1_b23OUT1_c22OUT2_a
IN1
2
T2
C1
10nF LV
21
IN2
4
C2
1206
20
OUT2_b
OUT2_c19OUT3_a18OUT3_b17OUT3_c16OUT4_a15OUT4_b14OUT4_c
VNI4140K
IN38IN4
10
D
C8
4.7nF
4
321
1 2
VDD
C7
4.7nF
STAT4STAT3
STAT2STAT1
3 4
5 6
7 8
9 10
11 12
13 14
J5
CAN7
IN1 IN2
IN3 IN4
RR5
47K 1206
T5
T6
A
T12
T7
RR2
T8
10111213141516
89
10K 1206
1234567
STAT1
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
J1
EVALCOMMBOARD
IN1
IN2
IN3
IN4
VDD
STAT4
STAT3
STAT2
D
2/8
1234567
IN1
IN2
IN3
C
OPT1
TLP281-4
8 9
RR3
IN4
1K 1206
10111213141516
STAT1
STAT2
STAT3
B
STAT4
OPT2
TLP281-4
1 2 34
VDD
RR4
10K 1206
A
STEVAL-IFP006V1 Connectors
2 Connectors
This evaluation board uses two input header connectors, one screw drives the four-channels
output connector and one screw drives the two-channel supply connector.
Both input connectors, J5 and J1, provide the same bidirectional evaluation board
signalization guaranteeing the maximum compatibility with existing ST tools, such as the
ST7540 FSK powerline transceiver evaluation board (see AN2451 ) and similar.
Figure 2. J1 connector pinout
Figure 3. J5 connector pinout
3/8
Loading...