HCF4538B
DUAL MONOSTABLE MULTIVIBRATOR
■RETRIGGERABLE/RESETTABLE CAPABILITY
■TRIGGER AND RESET PROPAGATION DELAYS INDEPENDENT OF RX, CX
■TRIGGERING FROM LEADING OR TRAILING EDGE
■Q AND Q BUFFERED OUTPUT AVAILABLE
■SEPARATE RESETS
■WIDE RANGE OF OUTPUT PULSE WIDTHS
■QUIESCENT CURRENT SPECIFIED UP TO 20V
■5V, 10V AND 15V PARAMETRIC RATINGS
■SCHMITT TRIGGER INPUT ALLOWS UNLIMITED RISE AND FALL TIMES ON +TR AND -TR INPUTS
■INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C
■100% TESTED FOR QUIESCENT CURRENT
■MEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
DESCRIPTION
The HCF4538B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages.
The HCF4538B dual precision monostable multivibrator provides stable retriggerable/ resettable one-shot operation for any fixed voltage
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DIP |
SOP |
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ORDER CODES |
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PACKAGE |
TUBE |
T & R |
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DIP |
HCF4538BEY |
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SOP |
HCF4538BM1 |
HCF4538M013TR |
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timing application. An external resistor (RX) and an external capacitor (CX) control the timing and accuracy for the circuit. Adjustment of RX and CX provides a wide range of output pulse widths from the Q and Q terminals. The time delay from trigger input to output transition (trigger propagation delay) and the time delay from reset input to output transition (reset propagation delay) and the time delay from reset input to output transition (reset propagation delay) are independent of RX and CX. Precision control of output pulse width is achieved through linear CMOS techniques. Leading edge triggering (+TR) and trailing edge triggering (-TR) inputs are provided for triggering
PIN CONNECTION
September 2001 |
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HCF4538B
from either edge of an input pulse. An unused +TR input should be tied to VSS. An unused -TR input should be tied to VDD . A RESET (on low level) is provided for immediate termination of the output pulse or to prevent output pulses when power is turned on. An unused RESET input should be tied to VDD . However, if an entire section of the HCF4538B is not used, its inputs must be tied to either VDD or VSS (see table 1). In normal operation the circuit triggers (extends the output
IINPUT EQUIVALENT CIRCUIT
FUNCTIONAL DIAGRAM
pulse one period) on the application of each new trigger pulse. For operation in the non-retiggerable mode, Q is connected to -TR when leading edge triggering (+TR) is used or Q is connected to +TR when trailing edge triggering (-TR) is used. The time period (T) for this multivibrator can be calculated by : T = RX CX. The min. value of external resistance, RX, is 4KΩ. The max. and min. values of external capacitance, CX, are 100 μF and 5nF, respectively.
PIN DESCRIPTION
PIN No |
SYMBOL |
NAME AND FUNCTION |
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4, 12 |
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+TR |
Trigger Inputs (Low to |
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High, Edge-Triggered) |
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5, 11 |
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-TR |
Trigger Inputs (High to |
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Low, Edge-Triggered) |
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3, 13 |
RESET |
Direct Reset Inputs |
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(Active Low) |
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1, 15 |
CX1, CX2 |
External Capacitor Con- |
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nections |
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2, 14 |
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RXCX1 |
External Resistor/Capaci- |
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RXCX2 |
tor Connections |
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6, 10 |
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Q1, Q2 |
Pulse Outputs |
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Complementary Pulse |
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7, 9 |
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Q1, Q2 |
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Outputs |
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8 |
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VSS |
Negative Supply Voltage |
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16 |
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VDD |
Positive Supply Voltage |
Terminals 1, 8, 15 are electrically connected internally
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HCF4538B
TABLE 1 : Functional Terminal Connections
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VDD to Term. N° |
VSS to Term. N° |
Input Pulse to |
Other Connections |
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FUNCTION |
Term. N° |
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Mono (1) |
Mono (2) |
Mono (1) |
Mono (2) |
Mono (1) |
Mono (2) |
Mono (1) |
Mono (2) |
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Leading Edge Trigger/ |
3, 5 |
11, 13 |
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4 |
12 |
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Retriggerable |
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Leading Edge Trigger/Non |
3 |
13 |
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4 |
12 |
5, 7 |
11, 9 |
Retriggerable |
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Trailing Edge Trigger/ |
3 |
13 |
4 |
12 |
5 |
11 |
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Retriggerable |
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Trailing Edge Trigger/Non |
3 |
13 |
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5 |
11 |
4, 6 |
12, 10 |
Retriggerable |
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A Retriggerable one-shot multivibrator has an output pulse width which is extended on full time period (T) after application of the last trigger pulse.
A Non-Retriggerable one-shot multivibrator has a time period (T) referenced from the application of the firs trigger pulse.
LOGIC DIAGRAM
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