ST HCF4099B User Manual
HCF4099B
8 BIT ADDRESSABLE LATCH
■ SERIAL DATA INPUT - ACTIVE PARALLEL
OUTPUT
■ STORAGE REGISTER CAPABILITY -
MASTER CLEAR
■ CAN FUNCTION AS DEMULTIPLEXER
■ QUIESCENT CURRENT SPECIFIED UP TO
20V
■ STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
■ INPUT LEAKAGE CURRENT
I
= 100nA (MAX) AT VDD = 18V TA = 25°C
I
■ 100% TESTED FOR QUIESCENT CURRENT
■ MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTI ON OF B SERI ES CMOS
DEVICES"
DESCRIPTION
HCF4099B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF4099B, an 8-bit addressable latch, is a
serial-input, parallel output storage register that
can perform a variety of functions. Data is input to
a particular bit in the latch when that bit is
addressed (by means of input A0, A1, A2) and
when WRITE DISABLE is at a low level. When
DIP SOP
ORDER CODES
PACKAGE TUBE T & R
DIP HCF4099BEY
SOP HCF4099BM1 HCF4099M013TR
WRITE DISABLE is high, data entry is inhibited;
however, all 8 ou tputs can be continuously re ad
independent of WRITE DISABLE and address
inputs. A mas ter RESET input is available, which
resets all bits to a logic "0" level when RESET and
WRITE DISABLE are at a high level. When
RESET is at a high level, and WRITE DISABLE is
at a low level, the latch acts as a 1-of-8
demultiplexer ; the bit that is addressed has an
active output which follows the data input, while all
unaddressed bits are held to a logic "0" level.
PIN CONNECTION
1/14October 2002
HCF4099B
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
5, 6, 7 A0 to A2 Address Inputs
9, 10, 11, 12,
13, 14, 15, 1
3 DATA Data Inputs
2 RESET Reset Input
4
8
16
FUNCTIONAL DIAGRAM
Q0 to Q7 Latch Outputs
WRITE
DISABLE
V
SS
V
DD
Write Disable Input
Negative Supply Voltage
Positive Supply Voltage
TRUTH TABLE
SELECT INPUTS
CBA
LLLQ0
LLHQ1
LHLQ2
LHHQ3
HLLQ4
HLHQ5
HHLQ6
HHHQ7
INPUTS OUTPUTS OF
WRITE DISABLE RESET
L L D Qi0 ADDRESSABLE LATCH
L H Qi0 Qi0 MEMORY
H L D L DEMULTIPLEXER
H H L L CLEAR ALL BITS TO "0"
D: The lev el at the data inp ut ; Qi0 The level before the indi cated steady st ate input cond i tions were es tablished , (i=0, 1,... 7)
2/14
ADDRESSED
LAT CH
EACH OTHER
OUTPUT
LATCH ADDRESSED
FUNCTION
LOGIC DIAGRAM
HCF4099B
TIMING CHART
3/14
HCF4099B
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to V
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
V
V
T
Supply Voltage
DD
DC Input Voltage -0.5 to VDD + 0.5
I
I
DC Input Current
I
Power Dissipation per Package 200 mW
D
-0.5 to +22 V
10 mA
±
Power Dissipation per Output Transistor 100 mW
Operating Temperature
op
Storage Temperature
stg
pin voltage.
SS
Supply Voltage
DD
Input Voltage 0 to V
I
Operating Temperature
op
-55 to +125 °C
-65 to +150 °C
3 to 20 V
DD
-55 to 125 °C
V
V
4/14
DC SPECIFICATIONS
Test Conditions Value
T
Symbol Parameter
I
Quiescent Current 0/5 5 0.04 5 150 150
L
V
(V)
V
I
O
(V)
I
O
(µA)
V
DD
(V)
= 25°C
A
Min. Typ. Max. Min. Max. Min. Max.
0/10 10 0.04 10 300 300
0/15 15 0.04 20 600 600
0/20 20 0.08 100 3000 3000
V
High Level Output
OH
Voltage
0/5 <1 5 4.95 4.95 4.95
0/15 <1 15 14.95 14.95 14.95
Low Level Output
V
OL
Voltage
5/0 <1 5 0.05 0.05 0.05
15/0 <1 15 0.05 0.05 0.05
High Level Input
V
IH
Voltage
0.5/4.5 <1 5 3.5 3.5 3.5
1.5/18.5 <1 15 11 11 11
V
IL
Low Level Input
Voltage
0.5/4.5 <1 5 1.5 1.5 1.5
1.5/18.5 <1 15 4 4 4
I
OH
Output Drive
Current
0/5 2.5 5 -1.36 -3.2 -1.1 -1.1
0/5 4.6 5 -0.44 -1 -0.36 -0.36
0/10 9.5 10 -1.1 -2.6 -0.9 -0.9
0/15 13.5 15 -3.0 -6.8 -2.4 -2.4
I
OL
Output Sink
Current
0/5 0.4 5 0.44 1 0.36 0.36
0/15 1.5 15 3.0 6.8 2.4 2.4
Input Leakage
I
I
Current
C
Input Capacitance
I
The Noi se Margin fo r both "1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
0/18 any input 18
any input 5 7.5 pF
-5
10
±
-40 to 85°C -55 to 125°C
0.1
±
1
±
HCF4099B
Unit
A
µ
V0/10 <1 10 9.95 9.95 9.95
V10/0 <1 10 0.05 0.05 0.05
V1/9 <1 10 7 7 7
V9/1 <1 10 3 3 3
mA
mA0/10 0.5 10 1.1 2.6 0.9 0.9
1
±
A
µ
5/14
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