ST HCF4021B User Manual

HCF4021B

ASYNCHRONOUS PARALLEL IN OR SYNCHRONOUS

SERIAL IN/SERIAL OUT 8 - STAGE STATIC SHIFT REGISTER

■ MEDIUM SPEED OPERATION : 12 MHz

(Typ.) CLOCK RATE AT V

■ FULLY STATIC OPERATION

■ 8 MASTER-SLAVE FLIP-FLOPS PLUS

- VSS = 10V

DD

OUTPUT BUFFERING AND CONTROL
GATING

■ QUIESCENT CURRENT SPECIFIED UP TO

20V

■ 5V, 10V AND 15V PARAMETRIC RAT INGS

■ INPUT LEAKAGE CURRENT

I

= 100nA (MAX) AT VDD = 18V TA = 25°C

I

■ 100% TESTED FOR QUIESCENT CURRENT

■ MEETS ALL REQUIREMENTS OF JEDEC

JESD13B " STANDARD SPECIF ICATIONS
FOR DESCRIPTI ON OF B SERI ES CMOS
DEVICES"

DESCRIPTION

The HCF4021B is a m onolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
This device is an 8-stage paral lel or serial input/
serial output register having common CLOCK and
PARALLEL/SERIAL CONTROL inputs, a single
SERIAL data input, and individual parallel "JAM"
inputs to each register stage. Each regist er stage
is a D-type, master-slave flip-flop in addition to an
output from stage 8, "Q" outputs are also available
from stages 6 and 7. Serial entry is synchronous
with the clock but parallel entry is asynchronous.

DIP SOP

ORDER CODES

PACKAGE TUBE T & R

DIP HCF4021BEY

SOP HCF4021BM1 HCF4021M013TR

In this device, entry is controlled by the
PARALLEL/SERIAL CONTROL input. When the
PARALLEL/SERIA L CONTROL input is low, data
is serially shifted into the 8-stage register
synchronously with the positive transition of he
clock line. When the PARALLEL/SERIAL
CONTROL input is high, data is jammed in to the
8-stage register via the parallel input lines and
synchronous with the positive transition of the
clock line, the CLOCK input of the internal stage is
"forced" when asynchronous parallel entry is
made. Register expansion using multiple package
is permitted.

PIN CONNECTION

1/11September 2001

HCF4021B

IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION

PIN No SYMBOL NAME AND FUNCTION

7, 6, 5, 4, 13,

14, 15, 1

11 SERIAL IN Serial Input

9

10 CLOCK Clock Input

2, 3, 12 Q6, Q7, Q8 Buffered Outputs

8

16

TRUTH TABLE

PI1 to PI8 Parallel Input

PARALLEL/

SERIAL

CONTROL

V

SS

V

DD

Parallel/Serial Input Con­trol

Negative Supply Voltage
Positive Supply Voltage

CLOCK SERIAL INPUT

PARALLEL/

SERIAL

CONTROL

PI - 1 PI - n

Q

1

(INTERNAL)

Q

XX10000
XX10101
XX11010
XX11111

Q

n

Q

n

Q

X : Don’t Care

00XX0

10XX1
XXXX

Q

1

LOGIC DIAGRAM

n

- 1

- 1

n

2/11

HCF4021B

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

V

P

T

T

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to V

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Value Unit

V

V

T

Supply Voltage

DD

DC Input Voltage -0.5 to VDD + 0.5

I

I

DC Input Current

I

Power Dissipation per Package 200 mW

D

-0.5 to +22 V

± 10 mA

Power Dissipation per Output Transistor 100 mW
Operating Temperature

op

Storage Temperature

stg

pin voltage.

SS

Supply Voltage

DD

Input Voltage 0 to V

I

Operating Temperature

op

-55 to +125 °C

-65 to +150 °C

3 to 20 V

DD

-55 to 125 °C

V

V

3/11

HCF4021B

DC SPECIFICATIONS

Test Condition Value

T

Symbol Parameter

I

Quiescent Current 0/5 5 0.04 5 150 150

L

V

(V)

V

I

(V)

|I

|

O

O

(µA)

V

DD

(V)

= 25°C

A

Min. Typ. Max. Min. Max. Min. Max.

0/10 10 0.04 10 300 300
0/15 15 0.04 20 600 600
0/20 20 0.08 100 3000 3000

V

High Level Output

OH

Voltage

0/5 <1 5 4.95 4.95 4.95

0/15 <1 15 14.95 14.95 14.95

Low Level Output

V

OL

Voltage

5/0 <1 5 0.05 0.05 0.05

15/0 <1 15 0.05 0.05 0.05

High Level Input

V

IH

Voltage

0.5/4.5 <1 5 3.5 3.5 3.5

1.5/13.5 <1 15 11 11 11

V

IL

Low Level Input
Voltage

4.5/0.5 <1 5 1.5 1.5 1.5

13.5/1.5 <1 15 4 4 4

I

OH

Output Drive
Current

0/5 2.5 <1 5 -1.36 -3.2 -1.1 -1.1

0/5 4.6 <1 5 -0.44 -1 -0.36 -0.36
0/10 9.5 <1 10 -1.1 -2.6 -0.9 -0.9
0/15 13.5 <1 15 -3.0 -6.8 -2.4 -2.4

I

OL

Output Sink
Current

0/5 0.4 <1 5 0.44 1 0.36 0.36

0/15 1.5 <1 15 3.0 6.8 2.4 2.4

Input Leakage

I

I

Current

C

Input Capacitance

I

The Noi se Margin fo r both "1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V

0/18 Any Input 18

Any Input 5 7.5 pF

±10

-5

-40 to 85°C -55 to 125°C

±0.1 ±1 ±1 µA

Unit

µA

V0/10 <1 10 9.95 9.95 9.95

V10/0 <1 10 0.05 0.05 0.05

V1/9 <1 10 7 7 7

V9/1 <1 10 3 3 3

mA

mA0/10 0.5 <1 10 1.1 2.6 0.9 0.9

4/11

HCF4021B

DYNAMIC ELECTRICAL CHARACTERISTICS (T

Symbol Parameter

CLOCKED OPERATION

t

PLH tPHL

t

THL tTLH

f

CL

t

t

setup

t

setup

t

Propagation Delay Time 5 160 320

Transition Time 5 100 200

(1)

Maximum Clock Input
Frequency

Clock Pulse Width 5 180 90

t

W

Clock Input Rise or Fall

, t

r

f

Time

Setup Time, serial Input
(ref to CL)

Setup Time, Parallel Inputs
(ref to P/S)

Hold Time, serial in,

hold

parallel in, parallel /serial
control

t

t

(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.

(1) If more than one unit is cascaded t
of the out put of the drivi ng stage of the estimated capacitiv e l oad.

P/S Pulse Widht 5 160 80

WH

P/S Removal Time (ref to

rem

CL)

CL should be made less than or equal to the sum of the transition time and the fixed propagation delay

r

(V)

V

DD

15 60 120

15 40 80

536

15 8.5 17

15 50 25

515

15 15

5 120 60

15 60 30

55025

15 20 10

50

15 0

15 50 25

5 280 140

15 100 50

= 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)

amb

Test Condition Value (*) Unit

Min. Typ. Max.

ns10 80 160

ns10 50 100

MHz10 6 12

ns10 80 40

µs10 15

ns10 80 40

ns10 30 15

ns10 0

ns10 80 40

ns10 140 70

5/11

HCF4021B

TEST CIRCUIT

CL = 50pF or equivalent (in cludes jig and probe capac i t ance)
R

= 200KΩ

L

R

= Z

of pulse generator (typically 50Ω)

T

OUT

WAVEFORM 1 : PROPAGATION DELAY TIMES, CLOCK PULSE WIDTH (f=1MHz; 50% duty cycle)

6/11

WAVEFORM 2 : SETUP AND HOLD TIMES (SI TO CLOCK) (f=1MHz; 50% duty cycle)

HCF4021B

WAVEFORM 3 : SETUP AND HOLD TIME (PI TO P/S) (f=1MHz; 50% duty cycle)

7/11

HCF4021B

WAVEFORM 4 : PULSE WIDTH AND REMOVAL TIME (P/S TO CLOCK) (f=1MHz; 50 % duty cycle )

8/11

HCF4021B

Plastic DIP-16 (0.25) MECHANICAL DATA

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

a1 0.51 0.020

B 0.77 1.65 0.030 0.065
b 0.5 0.020

b1 0.25 0.010

D 20 0.787

E 8.5 0.335
e 2.54 0.100

e3 17.78 0.700

F 7.1 0.280

I 5.1 0.201
L 3.3 0.130
Z 1.27 0.050

P001C

9/11

HCF4021B

SO-16 MECHANICAL DATA

DIM.

A 1.75 0.068

a1 0.1 0.2 0.003 0.007
a2 1.65 0.064

b 0.35 0.46 0.013 0.018

b1 0.19 0.25 0.007 0.010

C 0.5 0.019

c1 45° (typ.)

D 9.8 10 0.385 0.393

E 5.8 6.2 0.228 0.244
e 1.27 0.050

e3 8.89 0.350

F 3.8 4.0 0.149 0.157

G 4.6 5.3 0.181 0.208

L 0.5 1.27 0.019 0.050

M 0.62 0.024

S8° (max.)

MIN. TYP MAX. MIN. TYP. MAX.

mm. inch

10/11

PO13H

HCF4021B

Information furnished is bel ieved to be accurate and reliable. However, STMicroe lectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No li cense is granted by i mp lication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication ar e subject to change without notice. This publication supersedes and replaces all information
previously supplied. S TMicroelectronics products are not authorized for use as critica l components in life suppo rt devices or
systems without express written approval of STMicroelectronics.

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