This document applies to hardware revision 1 evaluation boards.
This evaluation board is intended to be used to:
●enable quick evaluation and debugging of software for the SPEAr1310 rev.C embedded
MPU family
●act as a learning tool for rapid familiarity with the features of the SPEAr1310 rev.C
●provide a reference design to use as a starting point for the development of a final
application board
The EVALSP1310CPU board is equipped with interfaces to the high speed peripherals
embedded in SPEAr1310 rev. C devices.
Through an expansion connector it is possible to plug in dedicated expansion boards
(EVALBASEXP) and/or FPGA boards (EVALSP13xxFPGA) for developing customerspecific IPs.
The EVALSP1310CPU board is shipped in protective anti-static packaging. Do not submit
the board to high electrostatic potentials, and follow good practices for working with static
sensitive devices.
●Wear an anti-static wristband. Wearing a simple anti-static wristband can help to
prevent ESD from damaging the board.
●Zero potential. Always touch a grounded conducting material before handling the
board, and periodically while handling it.
●Use an anti-static mat. When configuring the board, place it on an anti-static mat to
reduce the possibility of ESD damage.
●Handle only the edges. Handle the board by its edges only, and avoid touching board
components.
3.1 Connecting
1.Connect a serial cable adapter (RS232 on J16) to a host PC (see Primary Serial cable
setting).
2. On a host PC running Windows or Linux, start the Terminal program.
3. Connect the AC adapter to a power outlet.
4. Power on the board (plug the AC adapter jack into J12). A sequence of boot messages
displays, followed by the Linux console prompt.
Software user manuals are available on request; contact your local ST representative.
3.2 Booting
The EVALSP1310CPU board can boot a Linux kernel pre-installed in the serial NOR Flash.
At power on, the serial port outputs a brief header message with some uBoot information
(uBoot version, SDK version, and some internal hardware information). At this point, you
can choose to:
●Stop the system directly in uBoot
To do this, press the spacebar on the host computer keyboard before the boot delay
time expires (default is 3 seconds).
●Boot Linux
The system logs you in automatically as super user, and the Linux shell prompt
displays on the screen.
3.3 Serial interface
A serial interface, which can typically be used to connect an operating system monitor
console, is available on the J16 connector.
Doc ID 023872 Rev 19/36
Getting startedUM1585
Cross
cable
J17
12
34
J17
12
34
modem
cable
Null
It is possible to simulate a cross cable by changing the position of the J17 jumpers as shown
below.
Refer to the schematic drawing (contact your local ST representative for availability), for the
pin-out of the connectors.
Figure 4.Serial cable setting (J17)
3.4 Reset switch
A manual reset switch (P1) is available on the top side of the board.
10/36Doc ID 023872 Rev 1
UM1585Block descriptions
4 Block descriptions
4.1 General power supply
The power supply block generates all the required voltages from a 5 V external AC/DC. The
generated voltages are:
●5 V obtained from an over voltage protection device with thermal shutdown
●1.2 V, generated from 5 V with a step-down switching regulator
●1.5 V, 2.5 V, and 3.3 V generated from 5 V with a multi-output switching regulator
●12 V generated from 5 V with a set-up converter
●1.8 V generated from 3.3 V with a low drop voltage regulator
Table 1.Common power rails
Jumper
NameUse
for current
measurement
+5V
VDD1V2
VDD1V5
VDD1V8
VDD2V5
VDD3V3
J13: Alternate power input connector
J11: Expansion connector
GigaPhy chip
SPEAr 1.8 V NAND8 Flash (JP3: Close 2&3 for 1.8 V)
NAND Flash chip (Close 2&3 of JP2 for 1.8V)
NAND expansion connector (Close2&3 of JP3)
SPEAr_OTP antifuses (JP1: Close 1&2 to supply)
SPEAr GMII interface(JP16: Close 2&3 for 2.5V)
SPEAr PCIe (JP24 close and JP5: Close 2&3 for ext power)
SPEAr A2D_PLLs_VDD2V5
SPEAr USB_VDD2V5
A2D connector
Ethernet RJ45 (J2)
Giga PHY (JP42 close 2&3)
SPEAr (SPEAr_VDD3V3)
PCIe Clock Source
JTAG MIPHY connector
Giga PHY (JP42 close 1&2)
Serial NOR Flash
NAND Flash chip (Close 1&2 of JP2 for 3.3V)
NAND expansion connector (Close1&2 of JP3)
CPU JTAG & trace connectors
JP31
JP30
JP32
JP39
-
JP3(2-3)
JP33
JP1(1-2)
JP16(2-3)
JP34
Doc ID 023872 Rev 111/36
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