Stepper motor driver mounting the L6474
EVAL6474H
Features
■ Voltage range from 8 V to 45 V
■ Phase current up to 3 A
SPI with daisy chain feature
■
■ Socket for external resonator or crystal
■ FLAG LED indicator
■ Suitable for use in combination with the
STEVAL-PCC009V2
Description
The EVAL6474H demonstration board is a
microstepping motor driver. In combination with
the STEVAL-PCC009V2 communication board
and the easySPIN evaluation software, the board
allows the user to investigate all the features of
the L6474 device.
rms
EVAL6474H
Data brief
The EVAL6474H supports the daisy chain
configuration making it suitable for the evaluation
of the L6474 in multi-motor applications.
February 2012 Doc ID 022766 Rev 1 1/10
For further information contact your local STMicroelectronics sales office.
www.st.com
10
Board description EVAL6474H
Phase A connector
Power supply connector
(8 V - 45 V )
Master SPI
connector
SYNC output
FLAG LED
(Red)
ADCIN input
regulation
JP1: VDD supply from
master SPI connector
JP2:
JP4: STCK to slave SPI connector
JP5: DIR to slave SPI connector
VDD to VREG
connection
OSCIN/OSCOUT
connector
JP3: Daisy chain
termination
Phase B connector
Slave SPI
connector
Application reference
area
AM10269V1
1 Board description
Table 1. EVAL6474H specifications
Parameter Value
Supply voltage (VS) 8 to 45 V
Maximum output current (each phase) 3 A
Logic supply voltage (VREG)
Logic interface voltage (VDD)
Low level logic input voltage 0 V
High level logic input voltage VDD
Operating temperature -25 to +125 °C
L6474H thermal resistance junction-to-ambient 21 °C/W typical
1. All logic inputs are 5 V tolerant.
rms
Externally supplied: 3.3 V internally supplied: 3 V
typical
Externally supplied: 3.3 V or 5 V internally
supplied: VREG
(1)
Figure 1. Jumper and connector location
2/10 Doc ID 022766 Rev 1
EVAL6474H Board description
Table 2. Jumpers and connectors description
Name Type Function
J1 Power supply Motor supply voltage
J5 Power output Bridge A outputs
J6 Power output Bridge B outputs
J2 SPI connector Master SPI
J3 SPI connector Slave SPI
J4 NM connector OSCIN and OSCOUT pins
J7 NM connector SYNC output
TP1 (VS) Test point Motor supply voltage test point
TP4 (VDD) Test point Logic interface supply voltage test point
TP5 (VREG) Test point
TP6 (GND) Test point Ground test point
TP2 (STCK) Test point Step clock input test point
Logic supply voltage/L6474 internal regulator test
point
TP8 (DIR) Test point DIR output test point
TP3 (STBY/RES) Test point STBY/RES input test point
TP7 (FLAG) Test point FLAG output test point
Table 3. Slave SPI connector pinout (J11)
Pin
number
1 Digital input L6474 direction input
2 Open drain output L6474 FLAG output
3 Ground Ground
4 Supply EXT_VDD (can be used as external logic power supply)
5 Digital output
6 Digital input SPI serial clock signal (connected to L6474 CK input)
7 Digital input
8 Digital input SPI slave select signal (connected to the L6474 CS input)
9 Digital input L6474 step-clock input
10 Digital input L6474 standby/reset input
Type Description
SPI master IN slave OUT signal (connected to the L6474 SDO
output through daisy chain termination jumper JP2)
SPI master OUT slave IN signal (connected to the L6474 SDI
input)
Doc ID 022766 Rev 1 3/10
VDD VREG
VS
SPI_OUT
GND
Application reference
FLAG
DIR
STBY/RES
STCK
1A
2A
1B
2B
VS
GND
SYNC
OPTION
STCK
DIR
nCS
CK
SDI
SDO
ADCIN
DIR
FLAGCKnCS
STBY_RESET
STCK
MISO
SDI
FLAG
STBY_RESET
SDO
MISO
CK
FLAG
STBY_RESET
nCS
SDO
MISO
STCK
DIR
VS
VREG
VDD
VREGVDD
VDD
VREG
EXT_VDD
VS
EXT_VDD
VREGVDD
EXT_VDD
VDD
VDD
VS
TP8
1
J1
MORSV-508-2P
1
2
+
C9
100uF/63V
JP3
+
C2
47uF/6.3V
U1
L6474
VDD
17
VREG
6
OSCIN7OSCOUT
8
CP
10
VBOOT
11
ADCIN
5
VSA
2
VSA
26
VSB
12
VSB
16
PGND
13
PGND
27
OUT1A1OUT2A28OUT1B14OUT2B
15
AGND
9
DIR
4
DGND
21
SYNC
22
FLAG
24
SDO
18
SDI20CK
19
CS
23
STBY_RES
3
STCK
25
EPAD
29
JP5
J3
CON-FLAT-5X2-180M
1
2
34567
8
9 10
TP1
1
J7
N.M.
1
J5
MORSV-508-2P
1
2
R6
39k
C11
10nF/50V
C5
100nF/4V
C14
1nF/4V
C1
220nF/16V
J6
MORSV-508-2P
1
2
J4
N.M.
1
2
C13 3.3nF/4V
TP6
1
C8
100nF/50V
DL1
RED
2
1
JP4
TP2
1
R1
39k
C10
100nF/50V
TP4
1
TP7
1
+
C4
10uF/4V
C7
100nF/50V
R3
39k
TP5
1
TP3
1
JP1
+
C9A
100uF/63V
R5
470
D1
BAV99
12
3
C15
1nF/4V
C6
100nF/50V
R4
39k
C3
100nF/6.3V
JP2
R2
50k
13
2
C16
1nF/4V
J2
SPI_IN
123 4
56789 10
AM10276V1
Board description EVAL6474H
Figure 2. EVAL6474H schematic
4/10 Doc ID 022766 Rev 1
EVAL6474H Board description
Table 4. Bill of material
Item Quantity Reference Value Package
1 1 C1 220 nF/16 V CAPC-0603
2 1 C2 47 µF/6.3 V CAPC-3216
3 1 C3 100 nF/6.3 V CAPC-0603
4 1 C4 10 µF/4 V CAPC-3216
5 1 C5 100 nF/4 V CAPC-0603
6 4 C6,C7,C8,C10 100 nF/50 V CAPC-0603
7 1 C9A 100 µF/63 V CAPE-R8H12-P35
8 1 C9 100 µF/63 V CAPES-R10HXX
9 1 C11 10 nF/50 V CAPC-0603
10 1 C13 3.3 nF/4 V CAPC-0603
11 3 C14,C15,C16 1 nF/4 V CAPC-0603
12 1 DL1 LED diode (red) LEDC-0805
13 1 D1 BAV99 SOT-23
14 1 JP1 Jumper - open JP2SO
15 4 JP2,JP3,JP4,JP5 Jumper - closed JP2SO
16 3 J1,J5,J6 Screw connector 2 poles MORSV-508-2P
17 2 J2, J3
18 1 J4 N.M. STRIP254P-M-2
19 1 J7 N.M. TPTH-44SQ70
20 4 R1,R3,R4,R6 39 kΩ RESC-0603
21 1 R2 50 kΩ TRIMM-100X50X110-64W
22 1 R5 470Ω RESC-0603
23 8
24 1 U1 L6474H HTSSOP28
TP1,TP2,TP3,TP4,T
P5,TP6,TP7,TP8
Pol. IDC male header
vertical 10 poles
Test point TH
CON-FLAT-5X2-180M
Doc ID 022766 Rev 1 5/10
Board description EVAL6474H
AM10270V1
AM10271V1
Figure 3. EVAL6474H - layout (silk screen)
Figure 4. EVAL6474H - layout (top layer)
6/10 Doc ID 022766 Rev 1
EVAL6474H Board description
AM10272V1
AM10273V1
Figure 5. EVAL6474H - layout (inner layer 2)
Figure 6. EVAL6474H - layout (inner layer 3)
Doc ID 022766 Rev 1 7/10
Board description EVAL6474H
AM10274V1
110
100
1000
0
5
10
15
20
25
Time (s)
Zth
(°C/W)
AM10275V1
Figure 7. EVAL6474H - layout (bottom layer)
1.1 Thermal data
Figure 8. Thermal impedance graph
8/10 Doc ID 022766 Rev 1
EVAL6474H Revision history
2 Revision history
Table 5. Document revision history
Date Revision Changes
02-Feb-2012 1 Initial release.
Doc ID 022766 Rev 1 9/10
EVAL6474H
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10/10 Doc ID 022766 Rev 1
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