ST EVAL6474H User Manual

Stepper motor driver mounting the L6474

EVAL6474H

Features

■ Voltage range from 8 V to 45 V

■ Phase current up to 3 A

SPI with daisy chain feature

■

■ Socket for external resonator or crystal

■ FLAG LED indicator

■ Suitable for use in combination with the

STEVAL-PCC009V2

Description

The EVAL6474H demonstration board is a microstepping motor driver. In combination with the STEVAL-PCC009V2 communication board and the easySPIN evaluation software, the board allows the user to investigate all the features of the L6474 device.

rms

EVAL6474H

Data brief

The EVAL6474H supports the daisy chain configuration making it suitable for the evaluation of the L6474 in multi-motor applications.

February 2012 Doc ID 022766 Rev 1 1/10

For further information contact your local STMicroelectronics sales office.

www.st.com

Board description EVAL6474H

Phase A connector

Power supply connector

(8 V - 45 V )

Master SPI connector

SYNC output

FLAG LED

(Red)

ADCIN input

regulation

JP1: VDD supply from master SPI connector

JP2:

JP4: STCK to slave SPI connector JP5: DIR to slave SPI connector

VDD to VREG

connection

OSCIN/OSCOUT connector

JP3: Daisy chain termination

Phase B connector

Slave SPI connector

Application reference

area

AM10269V1

1 Board description

Table 1. EVAL6474H specifications

Parameter Value

Supply voltage (VS) 8 to 45 V

Maximum output current (each phase) 3 A

Logic supply voltage (VREG)

Logic interface voltage (VDD)

Low level logic input voltage 0 V

High level logic input voltage VDD

Operating temperature -25 to +125 °C

L6474H thermal resistance junction-to-ambient 21 °C/W typical

1. All logic inputs are 5 V tolerant.

rms

Externally supplied: 3.3 V internally supplied: 3 V typical

Externally supplied: 3.3 V or 5 V internally supplied: VREG

(1)

Figure 1. Jumper and connector location

2/10 Doc ID 022766 Rev 1

EVAL6474H Board description

Table 2. Jumpers and connectors description

Name Type Function

J1 Power supply Motor supply voltage

J5 Power output Bridge A outputs

J6 Power output Bridge B outputs

J2 SPI connector Master SPI

J3 SPI connector Slave SPI

J4 NM connector OSCIN and OSCOUT pins

J7 NM connector SYNC output

TP1 (VS) Test point Motor supply voltage test point

TP4 (VDD) Test point Logic interface supply voltage test point

TP5 (VREG) Test point

TP6 (GND) Test point Ground test point

TP2 (STCK) Test point Step clock input test point

Logic supply voltage/L6474 internal regulator test point

TP8 (DIR) Test point DIR output test point

TP3 (STBY/RES) Test point STBY/RES input test point

TP7 (FLAG) Test point FLAG output test point

Table 3. Slave SPI connector pinout (J11)

number

1 Digital input L6474 direction input

2 Open drain output L6474 FLAG output

3 Ground Ground

4 Supply EXT_VDD (can be used as external logic power supply)

5 Digital output

6 Digital input SPI serial clock signal (connected to L6474 CK input)

7 Digital input

8 Digital input SPI slave select signal (connected to the L6474 CS input)

9 Digital input L6474 step-clock input

10 Digital input L6474 standby/reset input

Type Description

SPI master IN slave OUT signal (connected to the L6474 SDO output through daisy chain termination jumper JP2)

SPI master OUT slave IN signal (connected to the L6474 SDI input)

Doc ID 022766 Rev 1 3/10

+ 7 hidden pages