Fully integrated stepper motor driver based on the L6472
EVAL6472H
Features
■ Voltage range from 8 V to 45 V
■ Phase current up to 3 A
SPI with daisy chain feature
■
■ SW input
■ FLAG and BUSY LED indicators
■ Adjustable supply voltage compensation
■ Suitable for use in combination with STEVAL-
PCC009V2
Description
r.m.s.
EVAL6472H
Data brief
The EVAL6472H demonstration board is a fully
integrated microstepping motor driver. In
combination with the STEVAL-PCC009V2
communication board and the dSPIN evaluation
software, the board allows the user to investigate
all the features of the L6472 device. In particular,
the board can be used to regulate the L6472
parameters in order to fit application
requirements.
The EVAL6472H supports the daisy chain
configuration making it suitable for the evaluation
of the L6472 in the multi-motor applications.
March 2012Doc ID 022980 Rev 11/11
For further information contact your local STMicroelectronics sales office.
TP2 (VDD)Test pointLogic interface supply voltage test point
TP3 (VREG)Test point
TP5 (GND)Test pointGround test point
TP6 (GND)Test pointGround test point
Logic supply voltage/L6470 internal regulator test
point
TP8 (STCK)Test pointStep clock input test point
TP9 (STBY/RES)Test pointStandby/reset input test point
TP10 (FLAG)Test pointFLAG output test point
TP11
(BUSY/SYNC)
Test pointBUSY/SYNC output test point
Table 3.Master SPI connector pinout (J10)
Pin
number
1Open drain outputL6472 BUSY output
2Open drain outputL6472 FLAG output
3GroundGround
4SupplyEXT_VDD (can be used as external logic power supply)
5Digital output
6Digital inputSPI serial clock signal (connected to L6472 CK input)
7Digital input
8Digital inputSPI slave select signal (connected to L6472 CS input)
TypeDescription
SPI master IN slave OUT signal (connected to L6472 SDO
output through daisy chain termination jumper JP2)
SPI master OUT slave IN signal (connected to L6472 SDI
input)
9Digital inputL6472 step-clock input
10Digital inputL6472 standby/reset input
Doc ID 022980 Rev 13/11
Board descriptionEVAL6472H
Table 4.Slave SPI connector pinout (J11)
Pin
number
1Open drain outputL6472 BUSY output
2Open drain outputL6472 FLAG output
3GroundGround
4SupplyEXT_VDD (can be used as external logic power supply)
5Digital outputSPI master IN slave OUT signal (connected to pin 5 of J10)
6Digital inputSPI serial clock signal (connected to L6472 CK input)
7Digital input
8Digital inputSPI slave select signal (connected to L6472 CS input)
9Digital inputL6472 step-clock input
10Digital inputL6472 standby/reset input
TypeDescription
SPI master OUT slave IN signal (connected to L6472 SDO
output)
4/11Doc ID 022980 Rev 1
EVAL6472HBoard description
1A
2A
SW
1B
2B
OSCINOSCOUT
Application reference
VS
GND
OPTION
SE
R
/YBTSKCTS
TUO_IPSNI_IP
S
YSUBGALF
GND
VDD
VREG
VS
SW
MISO
SDI
CK
nCS
FLAG
BUSY
STCK
STBY_RESET
MISO
SDO
CK
nCS
FLAGBUSY
SDO
MISO
BUSY
SDI
CK
nCS
SW
ADCIN
SDO
BUSYFLAG
FLAG
STBY_RESETSTCK
STCK
STBY_RESET
VS
VS
EXT_VDDEXT_VDD
EXT_VDD
VDD
VREG
VREG
VDD
VREG
VDD
VS
VDD
VDDVDD
VS
VS
J6
MORSV-508-2P
1
2
J4
NM
1
2
C10
100pF/6V3
J2
1
234
567
8910
J1
MORSV-508-2P
1
2
TP1
1
DL2
YELLOW
21
C6
10nF/50V
D1
BAV99
12
3
JP3
DL1
RED
2
1
C1
220nF/16V
C15
100nF/50V
R9
470
C12
100pF/6V3
TP7
1
TP8
1
C14
10nF/6V3
U1
L6472
VDD
17
VREG
6
OSCIN7OSCOUT
8
CP
10
VBOOT
11
ADCIN
5
VSA
2
VSA
26
VSB
12
VSB
16
PGND
13
PGND
27
OUT1A
1
OUT2A
28
OUT1B
14
OUT2B
15
AGND
9
SW
4
DGND
21
BUSY_SYNC
22
FLAG24SDO18SDI
20
CK
19
CS
23
STBY_RES
3
STCK
25
EPAD
29
TP4
1
C4
100nF/6V3
+
C5
47uF/6V3
C8
100nF/50V
R8
100
R2
200K
13
2
+
C3
10uF/6V3
R1
31k6
R5
39k
R7
470
+
C9A
100uF/63V
J5
MORSV-508-2P
1
2
TP3
1
C13
3.3nF/6V3
D2
BZX585-B3V6
TP5
1
C7
100nF/50V
R6
39k
TP6
1
J3
12345
6
7
8
9
10
C16
100nF/50V
C11
100pF/6V3
JP2
TP2
1
C2
100nF/6V3
R4
39k
J7
NM
1
2
R3
8k2
+
C9
100uF/63V
JP1
AM10295V1
Figure 2.EVAL6472H schematic
Doc ID 022980 Rev 15/11
Board descriptionEVAL6472H
Table 5.Bill of material
IndexQuantityReferenceValuePackage
11C1220 nF/16 VCAPC-0603
22C2,C4100 nF/6V3CAPC-0603
31C310 µF/6V3CAPC-3216
41C547 µF/6V3CAPC-3216
51C610 nF/50 VCAPC-0603
64C7, C8, C15, C16100 nF/50 VCAPC-0603
71C9A100 µF/6V3 (option)CAPE-R10HXX-P5
81C9100 µF/6V3CAPES-R10HXX
93C10, C11, C12100 pF/6V3CAPC-0603
101C133.3 nF/6V3CAPC-0603
111C1410 nF/6V3CAPC-0603
121DL1LED diode (red)LEDC-0805
131DL2LED diode (amber)LEDC-0805
141D1BAV99SOT23
151D2BZX585-B3V6SOD323
161JP1Jumper - openJP2SO
172JP2, JP3Jumper - closedJP2SO
183J1, J5, J6Screw connector 2 polesMORSV-508-2P
192J2,J3
202J4, J7NMSTRIP254P-M-2
211R131.6 kΩRESC-0603
221R2200 kΩTRIMM-100X50X110-64W
231R38.2 kΩRESC-0603
243R4, R5, R639 kΩRESC-0603
252R7, R9470 ΩRESC-0603
261R8100 ΩRESC-0603
TP1, TP2, TP3,
277
281TP6TPTH-ring-1 mm blackTH
291U1L6472HTSSOP28
TP4, TP5, TP7,
TP8
Pol. IDC male header vertical
10 poles
TPTH-ring-1 mm redTH
CON-FLAT-5X2-180M
6/11Doc ID 022980 Rev 1
EVAL6472HBoard description
AM10290V2
AM10290V1
Figure 3.EVAL6472H - silkscreen
Figure 4.EVAL6472H - layout (top layer)
Doc ID 022980 Rev 17/11
Board descriptionEVAL6472H
AM10291V1
AM10292V1
Figure 5.EVAL6472H - layout (inner layer2)
Figure 6.EVAL6472H - layout (inner layer3)
8/11Doc ID 022980 Rev 1
EVAL6472HBoard description
AM10293V1
1
10
100
1000
Time (sec)
0
5
10
15
20
25
Zth (°C/W)
AM10294V1
Figure 7.EVAL6472H - layout (bottom layer3)
1.1 Thermal data
Figure 8.Thermal impedance graph
Doc ID 022980 Rev 19/11
Revision historyEVAL6472H
2 Revision history
Table 6.Document revision history
DateRevisionChanges
21-Mar-20121Initial release.
10/11Doc ID 022980 Rev 1
EVAL6472H
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