ST EMIF10-LCD01C2 User Manual
®
IPAD™
MAIN PRODUCT CHARACTERISTICS:
Where EMI filtering in ESD sensitive equipment is
required :
■ LCD for Mobile phones
■ Computers and printers
■ Communication systems
■ MCU Boards
DESCRIPTION
The EMIF10-LCD01C2 is a 10 line highly integrated devices designed to suppress EMI/RFI noise in
all systems subjected to electromagnetic interferences. The EMIF10 flip chip packaging means the
package size is equal to the die size.
This filter includes an ESD protection circuitry,
which prevents the device from destruction when
subjected to ESD surges up 15kV.
BENEFITS
■ EMI symmetrical (I/O) low-pass filter
■ High efficiency in EMI filtering
■ Very low PCB space consuming: < 7mm
■ Coating resin on back side
■ Very thin package: 0.69 mm
■ High efficiency in ESD suppression on input
2
pins (IEC61000-4-2 level 4)
■ High reliability offered by monolithic integration
■ High reducing of parasitic elements through
integration and wafer level packaging.
■ Lead free package
EMIF10-LCD01C2
10 LINE EMI FILTER
AND ESD PROTECTION
Lead free coated Flip-Chip
(25 bumps)
Figure 1: Pin Configuration (bump side)
5
I5
I10 I8 I6
O10 O8 O6
O5 O3 O1
Figure 2: Basic Cell Configuration
Input
3
4
I3
I4 I2
I9
GNDGND GND
O9 O7
O4 O2
Low-pass Filter
I7
12
I1
A
B
GNDGND
C
D
E
Output
COMPLIES WITH THE FOLLOWING STANDARDS:
IEC61000-4-2:
Level 4 input pins 15kV (air discharge)
8kV (contact discharge)
Level 1 output pins 2kV (air discharge)
2kV (contact discharge)
MIL STD 833E - Method 3015-6 Class 3
August 2005
GND GND GND
Table 1: Order Code
Part Number Marking
EMIF10-LCD01C2 FL
REV. 1
Ri/o = 100
Cline = 35pF
Ω
1/7
EMIF10-LCD01C2
Table 2: Absolute Maximum Ratings (T
amb
= 25°C)
Symbol Parameter Value Unit
T
T
T
Table 3: Electrical Characteristics (T
Symbol Parameter
V
BR
I
RM
V
RM
V
CL
Rd Dynamic resistance
I
PP
R
I/O
Junction temperature 125 °C
j
I
I
F
-40 to + 85
Operating temperature range
op
Storage temperature range -55 to +150 °C
stg
= 25°C)
amb
Breakdown voltage
Leakage current @ V
RM
Stand-off voltage
V
Clamping voltage
V
V
V
CL
RM
BR
F
I
RM
I
R
Peak pulse current
I
Series resistance between Input & Output
PP
V
Cline Input capacitance per line
Symbol Test conditions Min. Typ. Max. Unit
V
BR
I
RM
R
I/O
Cline
IR = 1 mA
VRM = 3V
6810V
500 nA
90 100 110 Ω
@ 0V bias 28 35 pF
Rt / Ft Induced rise and fall time 10-90% at 26 MHz fre-
quency signal V = 1.9 V (Rt / Ft input 1 ns, 50Ω
8
(1)
impedance generator)
(1) guaranteed by design
°C
ns
Figure 3: S21(dB) all lines attenuation
measurement and Aplac simulation
2/7
Figure 4: Analog cross talk measurements
EMIF10-LCD01C2
Figure 5: ESD response to IEC61000-4-2
(+15kV air discharge) on one input and on one
output
V
in
V
out
Figure 7: Line capacitance versus applied
voltage
CLine(pF)
35
30
25
20
15
10
5
0
0.0 1.0 2.0 3.0 4.0 5.0
VLine(V)
Figure 6: ESD response to IEC61000-4-2 (-15kV
air discharge) on one input and on one output
Figure 8: Rise time 10-90% measurements with
1.9V signal at 26 MHz frequency (50Ω
generator)
Figure 9: Fall time 10-90% measurements with
1.9V signal at 26 MHz frequency (50Ω
generator)
3/7
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