ST EMIF10-LCD01C2 User Manual

®

EMIF10-LCD01C2

 

10 LINE EMI FILTER

IPAD™

AND ESD PROTECTION

 

 

MAIN PRODUCT CHARACTERISTICS:

Where EMI filtering in ESD sensitive equipment is required :

LCD for Mobile phones

Computers and printers

Communication systems

MCU Boards

DESCRIPTION

The EMIF10-LCD01C2 is a 10 line highly integrated devices designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interferences. The EMIF10 flip chip packaging means the package size is equal to the die size.

This filter includes an ESD protection circuitry, which prevents the device from destruction when subjected to ESD surges up 15kV.

BENEFITS

EMI symmetrical (I/O) low-pass filter

High efficiency in EMI filtering

Very low PCB space consuming: < 7mm2

Coating resin on back side

Very thin package: 0.69 mm

High efficiency in ESD suppression on input pins (IEC61000-4-2 level 4)

High reliability offered by monolithic integration

High reducing of parasitic elements through integration and wafer level packaging.

Lead free package

COMPLIES WITH THE FOLLOWING STANDARDS:

IEC61000-4-2:

Level 4 input pins 15kV (air discharge) 8kV (contact discharge)

Level 1 output pins 2kV (air discharge) 2kV (contact discharge)

MIL STD 833E - Method 3015-6 Class 3

Lead free coated Flip-Chip (25 bumps)

Figure 1: Pin Configuration (bump side)

5

4

3

2

1

 

I5

I4

I3

I2

I1

A

I10

I9

I8

I7

I6

B

GND GND GND GND GND C

O10 O9 O8 O7 O6 D

O5 O4 O3 O2 O1 E

Figure 2: Basic Cell Configuration

 

Low-pass Filter

 

Input

 

Output

 

 

Ri/o = 100

 

 

Cline = 35pF

GND

GND

GND

Table 1: Order Code

Part Number

Marking

EMIF10-LCD01C2 FL

August 2005

REV. 1

1/7

EMIF10-LCD01C2

Table 2: Absolute Maximum Ratings (Tamb = 25°C)

Symbol

 

 

Parameter

 

 

 

 

 

 

Value

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Tj

 

Junction temperature

 

 

 

 

 

 

 

125

 

°C

Top

 

Operating temperature range

 

 

 

 

 

 

-40 to + 85

°C

Tstg

 

Storage temperature range

 

 

 

 

 

 

-55 to +150

°C

Table 3: Electrical Characteristics (Tamb = 25°C)

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

 

Parameter

 

 

 

 

I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VBR

 

Breakdown voltage

 

 

 

 

IF

 

 

 

 

 

 

IRM

 

Leakage current @ VRM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VRM

 

Stand-off voltage

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VF

 

 

 

 

VCL

 

Clamping voltage

 

 

VCL VBR VRM

 

 

 

 

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IRM

 

 

 

Rd

 

Dynamic resistance

 

 

 

 

 

 

IR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IPP

 

Peak pulse current

 

 

 

 

 

 

 

 

 

 

 

 

RI/O

 

Series resistance between Input & Output

 

 

 

 

 

 

IPP

 

 

 

 

Cline

 

Input capacitance per line

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

Test conditions

 

 

Min.

 

 

 

Typ.

 

Max.

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

VBR

IR = 1 mA

 

 

6

 

8

 

10

V

IRM

VRM = 3V

 

 

 

 

 

 

 

 

500

nA

RI/O

 

 

 

 

90

 

100

 

110

Cline

@ 0V bias

 

 

 

 

28

 

35

pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rt / Ft

Induced rise and fall time 10-90% at 26 MHz fre-

 

 

 

 

 

 

 

 

 

 

 

 

quency signal V = 1.9 V (Rt / Ft input 1 ns, 50Ω

 

 

8 (1)

 

 

 

ns

 

 

 

impedance generator)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(1) guaranteed by design

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure

3: S21(dB) all lines attenuation

Figure 4: Analog cross talk measurements

measurement and Aplac simulation

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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ST EMIF10-LCD01C2 User Manual

EMIF10-LCD01C2

Figure 5: ESD response to IEC61000-4-2 (+15kV air discharge) on one input and on one output

Vin

Vout

Figure 6: ESD response to IEC61000-4-2 (-15kV air discharge) on one input and on one output

Figure 7: Line capacitance versus applied voltage

CLine(pF)

 

 

 

 

 

 

 

 

 

 

35

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

30

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

 

 

 

VLine(V)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.0

1.0

2.0

3.0

4.0

5.0

Figure 9: Fall time 10-90% measurements with 1.9V signal at 26 MHz frequency (50generator)

Figure 8: Rise time 10-90% measurements with 1.9V signal at 26 MHz frequency (50generator)

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