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EMIF10-LCD01C2 |
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10 LINE EMI FILTER |
IPAD™ |
AND ESD PROTECTION |
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MAIN PRODUCT CHARACTERISTICS:
Where EMI filtering in ESD sensitive equipment is required :
■LCD for Mobile phones
■Computers and printers
■Communication systems
■MCU Boards
DESCRIPTION
The EMIF10-LCD01C2 is a 10 line highly integrated devices designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interferences. The EMIF10 flip chip packaging means the package size is equal to the die size.
This filter includes an ESD protection circuitry, which prevents the device from destruction when subjected to ESD surges up 15kV.
BENEFITS
■EMI symmetrical (I/O) low-pass filter
■High efficiency in EMI filtering
■Very low PCB space consuming: < 7mm2
■Coating resin on back side
■Very thin package: 0.69 mm
■High efficiency in ESD suppression on input pins (IEC61000-4-2 level 4)
■High reliability offered by monolithic integration
■High reducing of parasitic elements through integration and wafer level packaging.
■Lead free package
COMPLIES WITH THE FOLLOWING STANDARDS:
IEC61000-4-2:
Level 4 input pins 15kV (air discharge) 8kV (contact discharge)
Level 1 output pins 2kV (air discharge) 2kV (contact discharge)
MIL STD 833E - Method 3015-6 Class 3
Lead free coated Flip-Chip (25 bumps)
Figure 1: Pin Configuration (bump side)
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4 |
3 |
2 |
1 |
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I5 |
I4 |
I3 |
I2 |
I1 |
A |
I10 |
I9 |
I8 |
I7 |
I6 |
B |
GND GND GND GND GND C
O10 O9 O8 O7 O6 D
O5 O4 O3 O2 O1 E
Figure 2: Basic Cell Configuration
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Low-pass Filter |
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Input |
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Output |
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Ri/o = 100Ω |
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Cline = 35pF |
GND |
GND |
GND |
Table 1: Order Code
Part Number |
Marking |
EMIF10-LCD01C2 FL
August 2005 |
REV. 1 |
1/7 |
EMIF10-LCD01C2
Table 2: Absolute Maximum Ratings (Tamb = 25°C)
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Parameter |
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Value |
Unit |
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Tj |
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Junction temperature |
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125 |
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°C |
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Top |
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Operating temperature range |
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-40 to + 85 |
°C |
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Tstg |
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Storage temperature range |
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-55 to +150 |
°C |
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Table 3: Electrical Characteristics (Tamb = 25°C) |
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Symbol |
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Parameter |
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I |
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VBR |
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Breakdown voltage |
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IF |
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IRM |
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Leakage current @ VRM |
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VRM |
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Stand-off voltage |
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VF |
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VCL |
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Clamping voltage |
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VCL VBR VRM |
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V |
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IRM |
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Rd |
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Dynamic resistance |
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IR |
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IPP |
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Peak pulse current |
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RI/O |
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Series resistance between Input & Output |
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IPP |
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Cline |
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Input capacitance per line |
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Symbol |
Test conditions |
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Min. |
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Typ. |
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Max. |
Unit |
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VBR |
IR = 1 mA |
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6 |
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8 |
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10 |
V |
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IRM |
VRM = 3V |
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500 |
nA |
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RI/O |
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90 |
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100 |
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110 |
Ω |
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Cline |
@ 0V bias |
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28 |
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35 |
pF |
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Rt / Ft |
Induced rise and fall time 10-90% at 26 MHz fre- |
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quency signal V = 1.9 V (Rt / Ft input 1 ns, 50Ω |
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8 (1) |
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ns |
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impedance generator) |
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(1) guaranteed by design |
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Figure |
3: S21(dB) all lines attenuation |
Figure 4: Analog cross talk measurements |
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measurement and Aplac simulation |
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2/7
EMIF10-LCD01C2
Figure 5: ESD response to IEC61000-4-2 (+15kV air discharge) on one input and on one output
Vin
Vout
Figure 6: ESD response to IEC61000-4-2 (-15kV air discharge) on one input and on one output
Figure 7: Line capacitance versus applied voltage
CLine(pF) |
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35 |
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25 |
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5 |
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VLine(V) |
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0 |
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0.0 |
1.0 |
2.0 |
3.0 |
4.0 |
5.0 |
Figure 9: Fall time 10-90% measurements with 1.9V signal at 26 MHz frequency (50Ω generator)
Figure 8: Rise time 10-90% measurements with 1.9V signal at 26 MHz frequency (50Ω generator)
3/7