ST EMIF10-COM01F2 User Manual
EMIF10-COM01F2
10-line IPAD™, EMI filter including ESD protection
Features
■EMI symmetrical (I/O) low-pass filter
■Lead free package
■Very low PCB space consuming: < 6 mm2
■Very thin package: 0.65 mm
■High efficiency in ESD suppression on both input & output pins
■High reliability offered by monolithic integration
Complies with the following standard:
■IEC 61000-4-2 level 4
–15 kV (air discharge)
–8 kV (contact discharge)
Applications
EMI filtering and ESD protection for:
■Computers and printers
■Communication systems
■Mobile phones
Description
The EMIF10-COM01F2 is a highly integrated device designed to suppress EMI / RFI noise in all systems subjected to electromagnetic interferences. The EMIF10 Flip-Chip packaging means the package size is equal to the die size.
Additionally, this filter includes an ESD protection circuitry which prevents damage to the application when subjected to ESD surges up to 15 kV.
Flip Chip (25 bumps)
Figure 1. Pin configuration (bump side)
5 |
4 |
3 |
2 |
1 |
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I5 |
I4 |
I3 |
I2 |
I1 |
A |
I10 |
I9 |
I8 |
I7 |
I6 |
B |
GND |
GND |
GND |
GND |
GND |
C |
010 |
09 |
08 |
07 |
06 |
D |
05 |
04 |
03 |
02 |
01 |
E |
Figure 2. Basic cell configuration
Low-pass Filter
Input |
Output |
RI/O = 200Ω
Cline = 45 pF
TM: IPAD is a trademark of STMicroelectronics.
April 2008 |
Rev 5 |
1/7 |
www.st.com
Characteristics |
EMIF10-COM01F2 |
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1 Characteristics
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Table 1. |
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Absolute ratings (Tamb = 25 °C) |
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Symbol |
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Parameter and test conditions |
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Value |
Unit |
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VPP |
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ESD discharge IEC61000-4-2, air discharge |
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15 |
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kV |
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ESD discharge IEC61000-4-2, contact discharge |
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8 |
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Tj |
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Junction temperature |
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125 |
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°C |
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Top |
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Operating temperature range |
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- 40 to + 85 |
°C |
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Tstg |
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Storage temperature range |
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- 55 to + 150 |
°C |
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Table 2. |
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Electrical characteristics (Tamb = 25 °C) |
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Symbol |
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Parameter |
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I |
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VBR |
Breakdown voltage |
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IRM |
Leakage current @ VRM |
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VRM |
Stand-off voltage |
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VCL VBR VRM |
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VCL |
Clamping voltage |
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IRM |
V |
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Rd |
Dynamic impedance |
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IR |
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IPP |
Peak pulse current |
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RI/O |
Resistance between Input and Output |
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slope :1 / R d |
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IPP |
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Cline |
Input capacitance per line |
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Symbol |
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Test conditions |
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Min. |
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Typ. |
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Max. |
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Unit |
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VBR |
IR = 1 mA |
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6 |
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8 |
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10 |
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V |
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IRM |
VRM = 3 V per line |
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500 |
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nA |
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Rd |
IPP = 10 A, tp = 2.5 µs |
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1 |
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Ω |
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RI/O |
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180 |
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200 |
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220 |
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Ω |
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Cline |
At 0 V bias |
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45 |
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50 |
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pF |
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tLH |
Vinput = 2.8 V |
Rload = 100 kΩ |
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25 |
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ns |
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Figure 3. S21(db) attenuation |
Figure 4. |
Analog crosstalk |
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measurement(1)
0.00 dB -10.00
-20.00
-30.00
-40.00
-50.00
100.0k 1.0M 10.0M 100.0M 1.0G f/Hz
0.00 dB -10.00
-20.00
-30.00
-40.00
-50.00
-60.00
-70.00
-80.00
-90.00
-100.00
100.0k 1.0M 10.0M 100.0M 1.0G f/Hz
Xtalk 1/2
1. Spikes at high frequencies are induced by the PCB layout
2/7
EMIF10-COM01F2 |
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Characteristics |
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Figure 5. |
ESD response to IEC 61000-4-2 |
Figure 6. |
ESD response to IEC 61000-4-2 |
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(+15 kV air discharge) on one input |
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(-15 kV air discharge) on one input |
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(Vin) and on one output (Vout) |
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(Vin) and on one output (Vout) |
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V(in1) |
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V(in1) |
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V(out1) |
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V(out1) |
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Figure 7. |
Rise time measurement |
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Square signal Generator Vc = 2.8V
EMIF10-COM01F2 |
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In |
Out |
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Vout |
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Vin |
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100k |
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Figure 8. Capacitance versus reverse applied voltage
C(pF)
50
F=1MHz
Vosc=30mV
40
30
20
10
0 |
1 |
2 |
3 |
4 |
5 |
VR(V)
3/7
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