IPAD™
Main product characteristics
EMI filtering and ESD protection for:
■ Computers and printers
■ Communication systems
■ Mobile phones
EMIF10-COM01C2
EMI Filter including ESD protection
Description
The EMIF10-COM01C2 is a highly integrated
device designed to suppress EMI / RFI noise in all
systems subjected to electromagnetic
interferences. The EMIF10 Flip-Chip packaging
means the package size is equal to the die size.
Additionally, this filter includes an ESD protection
circuitry which prevents damage to the application
when subjected to ESD surges up to 15 kV.
Benefits
■ EMI symmetrical (I/O) low-pass filter
■ Coating resin on flat side
■ Very low PCB space consuming: < 6 mm
■
Very thin package: 0.65 mm
■ High efficiency in ESD suppression on both
input and output pins
■ High reliability offered by monolithic integration
■ Lead free package
Complies with the following standards:
2
Lead free coated Flip-Chip
(25 Bumps)
Order code
Part Number Marking
EMIF10-COM01C2 FE
Figure 1. Pin configuration (Bump side)
54
I5
Figure 2. Basic cell configuration
3
21
I3
I9 I8I10
GNDGND
I1
I2I4
I6
I7
GNDGND GND
0609 08010 07
0204 0305
01
A
B
C
D
E
IEC 61000-4-2 level 4
15 kV (air discharge)
Input
Low-pass Filter
Output
8 kV (contact discharge)
R = 200
I/O
C = 45 pF
TM: IPAD is a trademark of STMicroelctronics
line
April 2006 Rev4 1/7
Ω
www.st.com
7
Characteristics EMIF10-COM01C2
1 Characteristics
Table 1. Absolute Ratings (T
Symbol Parameter and test conditions Value Unit
= 25 °C)
amb
V
T
T
Table 2. Electrical Characteristics (T
ESD discharge IEC61000-4-2, air discharge
PP
ESD discharge IEC61000-4-2, contact discharge
Junction temperature 125 °C
T
j
Operating temperature range - 40 to + 85 °C
op
Storage temperature range - 55 to + 150 °C
stg
Symbol Parameter
V
V
V
R
C
Breakdown voltage
BR
I
Leakage current @ V
RM
Stand-off voltage
RM
Clamping voltage
CL
R
Dynamic impedance
d
I
Peak pulse current
PP
Resistance between Input and Output
I/O
Input capacitance per line
line
RM
= 25 °C)
amb
V
V
CL
slope : 1 / R d
V
RM
BR
15
8
I
I
RM
I
R
I
PP
Symbol Test conditions Min. Typ. Max. Unit
kV
V
V
I
R
R
C
t
IR = 1 mA 6 8 10 V
BR
VRM = 3 V per line 500 nA
RM
IPP = 10 A, tp = 2.5 µs 1 Ω
d
I/O
At 0 V bias 45 50 pF
line
V
LH
= 2.8 V R
input
= 100 kΩ 25 ns
load
2/7
180 200 220 Ω
EMIF10-COM01C2 Characteristics
Figure 3. S21(db) attenuation
measurement
0.00
0.00
0.00
dB
dB
dB
-10.00
-10.00
-10.00
-20.00
-20.00
-20.00
-30.00
-30.00
-30.00
-40.00
-40.00
-40.00
-50.00
-50.00
-50.00
100.0k 1.0M 10.0M 100.0M 1.0G
100.0k 1.0M 10.0M 100.0M 1.0G
100.0k 1.0M 10.0M 100.0M 1.0G
1. Spikes at high frequencies are induced by the PCB layout
(1)
f/Hz
f/Hz
f/Hz
Figure 5. ESD response to IEC 61000-4-2
(+15 kV air discharge) on one input
(V
) and on one output (V
in
V(in1)
out
)
Figure 4. Analog crosstalk
0.00
0.00
dB
dB
-10.00
-10.00
-20.00
-20.00
-30.00
-30.00
-40.00
-40.00
-50.00
-50.00
-60.00
-60.00
-70.00
-70.00
-80.00
-80.00
-90.00
-90.00
-100.00
-100.00
100.0k 1.0M 10.0M 100.0M 1.0G
100.0k 1.0M 10.0M 100.0M 1.0G
Xtalk 1/2 448
Xtalk 1/2 448
f/Hz
f/Hz
Xtalk 1/2 342
Xtalk 1/2 342
Figure 6. ESD response to IEC 61000-4-2
(-15 kV air discharge) on one input
(Vin) and on one output (V
out
V(in1)
)
Figure 7. Rise time measurement
Square signal
Generator Vc = 2.8V
Vin
V(out1)
EMIF10-COM01C2
In Out
100k
V(out1)
Vout
Vout
Vin
3/7
Characteristics EMIF10-COM01C2
Figure 8. Capacitance versus reverse applied
voltage
C(pF)
50
F=1MHz
40
30
20
10
012345
VR(V)
Vosc=30mV
Figure 9. Aplac model
in
200R
MODEL = demif10 MODEL = demif10
sub
1.1 PCB grounding recommendations
In order to ensure a good efficiency in terms of ESD protection and filtering behavior, we
recommend to implement microvias (100 µm dia.) between the GND bumps and the GND
layer. GND bumps can be connected together in PCB layer 1, and in addition, if possible,
use through hole vias (200 µm dia.) in both sides of filter to improve contact to GND (layer).
This layout will minimize the distance to the ground and thus parasitic inductances. In
addition, we recommend to have GND plane wherever possible.
out
Demif10 model
BV = 7
IBV = 1m
CJO = 25p
M = 0.3333
RS = 1
VJ = 0.6
TT = 100n
4/7
EMIF10-COM01C2 Ordering Information Scheme
2 Ordering Information Scheme
EMIF yy - xxx zz Cx
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
or
3 letters = application
2 digits = version
Packag e
C = coated flip-chip
x = 1: 500µm, Bump = 315µm
= 2: Leadfree Pitch = 500µm, Bump = 315µm
3 Package information
Figure 10. Flip-Chip package dimensions
500 µm ± 50
315 µm ± 50
500 µm ± 50
2.42 mm ± 50 µm
2.42 mm ± 50 µm
695 µm ± 70
Figure 11. Foot print recommendations Figure 12. Marking
Dot, ST logo
xx = marking
Copper pad Diameter:
250 µm recommended, 300 µm max
Solder stencil opening: 330 µm
Solder mask opening recommendation:
340 µm min for 300 µm copper pad diameter
z = manufacturing location
yww = datecode
(y = year
ww = week)
E
xyxwz
w
5/7
Ordering information EMIF10-COM01C2
Figure 13. Flip-Chip tape and reel specification
Dot identifying Pin A1 location
8 +/- 0.3
ST
yww
xxz
E
4 +/- 0.1
yww
xxz
ST
E
Ø 1.5 +/- 0.1
yww
xxz
1.75 +/- 0.1 3.5 +/- 0.1
ST
E
0.73 +/- 0.05
All dimensions in mm
User direction of unreeling
4 +/- 0.1
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available
at: www.st.com.
Note: More informations are available in the application notes:
AN1235: “Flip-Chip: Package description and recommendations for use”
AN1751: "EMI Filters: Recommendations and measurements"
4 Ordering information
Ordering code Marking Package Weight Base qty Delivery mode
EMIF10-COM01C2 FE Flip-Chip 8.3 mg 5000 Tape and reel
5 Revision history
Date Revision Description of Changes
12-Jul-2005 1 First issue.
12-Aug-2005 2
27-Jan-2006 3
04-Apr-2006 4
6/7
Lead free added in Benefits on page 1. ECOPACK
statement added on page 6.
Improved graphics to show coating. Updated attenuation
measurement graphic (Figure 3). Weight corrected.
Reformatted to current standard. Pin identification in
Figure 1 updated.
EMIF10-COM01C2
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