ST EMIF10-1K010F2 User Manual

EMIF10-1K010F2

10-line IPAD™, EMI filter including ESD protection

Features

EMI symmetrical (I/O) low-pass filter

High efficiency in EMI filtering

Lead free package

Very low PCB space consuming: 2.42 mm x 2.42 mm

Very thin package: 0.650 mm

High efficiency in ESD suppression on both input and output pins (IEC 61000-4-2 level 4)

High reliability offered by monolithic integration

High reducing of parasitic elements through integration & wafer level packaging

Complies with the following standards:

IEC 61000-4-2 level 4

15 kV (air discharge)

8 kV (contact discharge)

MIL STD 883F - Method 3015.7 Class 3

Applications

Where EMI filtering in ESD sensitive equipment is required:

Mobile Phones

Computers and printers

Communication systems

MCU Boards

Description

The EMIF10-1K010F2 is a highly integrated device designed to suppress EMI / RFI noise in all systems subjected to electromagnetic interferences. The EMIF10 Flip-Chip packaging means the package size is equal to the die size.

Additionally, this filter includes an ESD protection circuitry which prevents damage to the application when subjected to ESD surges up to 15 kV.

Flip Chip (24 bumps)

Figure 1. Pin configuration (bump side)

5

4

3

2

1

 

I7

GND

GND

I3

 

A

I9

GND

GND

I5

I1

B

I10

I8

I6

I4

I2

C

09

07

05

03

01

D

010

08

06

04

02

E

Figure 2. Basic cell configuration

Low pass filter

Input Output

RI/O = 1 kΩ

Cline = 100 pF

TM: IPAD is a trademark of STMicroelectronics.

April 2008

Rev 4

1/8

www.st.com

Characteristics

EMIF10-1K010F2

 

 

1 Characteristics

Table 1.

 

Absolute ratings (Tamb = 25 °C)

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

Parameter and test conditions

 

 

 

 

 

 

Value

 

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ESD discharge IEC 61000-4-2

 

 

 

 

 

 

 

 

 

 

 

VPP

 

– Air discharge

 

 

 

 

 

15

 

 

kV

 

– Contact discharge

 

 

 

 

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MIL STD 883F - Method 3015.7 Class 3

 

 

 

 

 

25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Tj

 

Junction temperature

 

 

 

 

 

125

 

 

°C

Top

 

Operating temperature range

 

 

 

 

- 40 to + 85

 

°C

Tstg

 

Storage temperature range

 

 

 

 

- 55 to + 150

 

°C

Table 2.

 

Electrical characteristics (Tamb = 25 °C)

 

 

 

 

 

 

 

Symbol

 

Parameter

 

 

 

 

 

 

I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VBR

Breakdown voltage

 

 

 

 

 

 

IF

 

 

 

IRM

Leakage current @ VRM

 

 

 

 

 

 

 

 

 

 

 

 

VRM

Stand-off voltage

 

 

VBR

 

 

 

VF

 

 

VCL

Clamping voltage

 

 

VRM

 

 

 

 

 

 

VCL

 

 

 

 

 

 

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IRM

 

Rd

Dynamic impedance

 

 

 

 

 

 

 

IR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IPP

Peak pulse current

 

 

 

 

 

 

 

 

 

 

 

 

RI/O

Resistance between Input and Output

 

 

 

 

 

 

 

IPP

 

 

Cline

Input capacitance per line

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

Test conditions

 

Min.

Typ.

 

 

Max.

 

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VBR

IR = 1 mA

 

6

 

 

8

 

 

10

 

 

V

IRM

VRM = 3 V per line

 

 

 

 

 

 

 

 

200

 

 

nA

Rd

IPP = 10 A, tp = 2.5 µs

 

 

 

 

 

1

 

 

 

 

 

Ω

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RI/O

 

 

 

900

 

 

1000

 

 

1100

 

 

Ω

Cline

F = 1 MHz VOSC = 30 mV Vline = 0 V

 

80

 

 

100

 

 

120

 

 

pF

2/8

ST EMIF10-1K010F2 User Manual

EMIF10-1K010F2

Characteristics

 

 

Figure 3. S21(db) attenuation measurement Figure 4.

Analog cross talk measurements

0.00

dB

- 10.00

- 20.00

- 30.00

- 40.00

- 50.00

1.0M

3.0M

10.0M

30.0M

100.0M

300.0M

1.0G

3.0G

 

 

 

f/Hz

 

 

 

 

Figure 5. ESD response to IEC 61000-4-2 (+15 kV air discharge) on one input (Vin) and on one output (Vout)

Figure 6. ESD response to IEC 61000-4-2 (-15 kV air discharge) on one input (Vin) and on one output (Vout)

INPUT

INPUT

OUTPUT

OUTPUT

Figure 7. Capacitance versus reverse applied voltage

C (pF)

120

Input / GND

100

 

 

 

 

 

80

 

 

 

 

 

60

 

 

 

 

 

40

 

 

 

 

 

20

 

 

 

 

 

 

 

 

VR (V)

 

 

0

1.0

2.0

3.0

4.0

5.0

0.0

3/8

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