Datasheet EMIF10-1K010F2 Datasheet (ST)

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10-line IPAD™, EMI filter including ESD protection

Features

■ EMI symmetrical (I/O) low-pass filter

■ High efficiency in EMI filtering

■ Lead free package

■ Very low PCB space consuming:

2.42 mm x 2.42 mm

■ Very thin package: 0.650 mm

■ High efficiency in ESD suppression on both

input and output pins (IEC 61000-4-2 level 4)

■ High reliability offered by monolithic integration

■ High reducing of parasitic elements through

integration & wafer level packaging

Complies with the following standards:

■ IEC 61000-4-2 level 4

– 15 kV (air discharge) – 8 kV (contact discharge)

■ MIL STD 883F - Method 3015.7 Class 3

Applications

Where EMI filtering in ESD sensitive equipment is required:

■ Mobile Phones

■ Computers and printers

■ Communication systems

■ MCU Boards

Description

EMIF10-1K010F2

Flip Chip

(24 bumps)

Figure 1. Pin configuration (bump side)

I10 I8 I6

09 07 05 03 01

010 08 06 04 02

Figure 2. Basic cell configuration

Input

GND GND

Low pass filter

I4 I2

Output

The EMIF10-1K010F2 is a highly integrated device designed to suppress EMI / RFI noise in all systems subjected to electromagnetic

R = 1 k

C = 100 pF

line

I/O

interferences. The EMIF10 Flip-Chip packaging means the package size is equal to the die size.

Additionally, this filter includes an ESD protection circuitry which prevents damage to the application when subjected to ESD surges up to 15 kV.

TM: IPAD is a trademark of STMicroelectronics.

April 2008 Rev 4 1/8

www.st.com

Characteristics EMIF10-1K010F2

1 Characteristics

Table 1. Absolute ratings (T

Symbol Parameter and test conditions Value Unit

ESD discharge IEC 61000-4-2

Table 2. Electrical characteristics (T

Symbol Parameter

I/O

line

– Air discharge

– Contact discharge

MIL STD 883F - Method 3015.7 Class 3

Junction temperature 125 °C

Operating temperature range - 40 to + 85 °C

Storage temperature range - 55 to + 150 °C

stg

Breakdown voltage

Leakage current @ V

Stand-off voltage

Clamping voltage

Dynamic impedance

Peak pulse current

Resistance between Input and Output

Input capacitance per line

= 25 °C)

amb

= 25 °C)

amb

Symbol Test conditions Min. Typ. Max. Unit

BRIR

I/O

line

= 1 mA 6 8 10 V

VRM = 3 V per line 200 nA

IPP = 10 A, tp = 2.5 µs 1 Ω

F = 1 MHz V

= 30 mV V

OSC

= 0 V 80 100 120 pF

line

2/8

900 1000 1100 Ω

EMIF10-1K010F2 Characteristics

Figure 3. S21(db) attenuation measurement Figure 4. Analog cross talk measurements

0.00

- 10.00

- 20.00

- 30.00

- 40.00

- 50.00

Figure 5. ESD response to IEC 61000-4-2

1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G f/Hz

(+15 kV air discharge) on one input

) and on one output (V

out

INPUT

)

Figure 6. ESD response to IEC 61000-4-2

(-15 kV air discharge) on one input (Vin) and on one output (V

out

INPUT

)

OUTPUT

Figure 7. Capacitance versus reverse applied voltage

C (pF)

120

100

0.0 1.0 2.0 3.0 4.0 5.0

V(V)

OUTPUT

Input / GND

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Application information EMIF10-1K010F2

2 Application information

Figure 8. Aplac model

50pH 50pHRs Rs50m 50mLs Ls

+ +

Port 15 50

- -

cap_line cap_line

Lgnd

MODEL = demif10

Rgnd

Rseries

MODEL = demif10

sub

Rgnd RgndRgnd Lgnd Lgnd Lgnd

Rsubump

Rsub

Rsubump

Csubump

GNDi

Csubump

Figure 9. Aplac parametersl

Cz 57pF Rseries 960 cap_line 0.8pF Ls 0.6nH Rbump 50m Lbump 50pH Rs 0.15 Csubump 15pF Rsubump 0.15 Rsub 0.1 lhole 1.2nH opt Rhole 0.15 cap_hole 0.15pF Rgnd 0.25 Ignd 0.4nH

Model demif10 BV = 7 IBV = 1m CJO = Cz M = 0.3333 Rs = 1 VJ = 0.6 TT = 100n

Port 16

GNDi

Lbump

Rbump

Lhole

cap_hole

sub

Rhole

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EMIF10-1K010F2 Ordering information scheme

3 Ordering information scheme

Figure 10. Ordering information scheme

EMIF yy - xxx zz Fx

EMI Filter

Number of lines

Information

x = resistance value (Ohms) z = capacitance value / 100 (pF) or 3 letters = application 2 digits = version

Package

F = Flip Chip X = 2: lead-free pitch = 500 µm, bump = 315 µm

4 Package information

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at

www.st.com.

Figure 11. Flip Chip package dimensions

500 µm ± 50

210 µm

310 µm ± 50

2.39 mm ± 30 µm

210 µm

650 µm ± 65

250 µm ± 40

5/8

Ordering information EMIF10-1K010F2

Figure 12. Footprint recommendations Figure 13. Marking

Dot, ST logo xx = marking

Copper pad Diameter:

250 µm recommended, 300 µm max

Solder stencil opening: 330 µm

Solder mask opening recommendation:

340 µm min for 310 µm copper pad diameter

z = manufacturing location yww = datecode

(y = year

ww = week)

xyxwz

Figure 14. Flip Chip tape and reel specification

Dot identifying Pin A1 location

4 ± 0.1

Ø 1.5 ± 0.1

1.75 ± 0.1 3.5 ± 0.1

2.60

yww

xxz

User direction of unreeling

0.73 ± 0.05

All dimensions in mm

8 ± 0.3

yww

xxz

5 Ordering information

Table 3. Ordering information

Order code Marking Package Weight Base qty Delivery mode

EMIF10-1K010F2 FD Flip Chip 7.9 mg 5000 Tape and reel

Note: More information is available in the application notes:

AN1235: “Flip Chip: Package description and recommendations for use”

AN1751: "EMI Filters: Recommendations and measurements

2.60

4 ± 0.1

yww

xxz

6/8

EMIF10-1K010F2 Revision history

6 Revision history

Table 4. Document revision history

Date Revision Description of changes

12-Oct-2004 1 First issue.

28-Aug-2006 2 Die layout upgrade.

18-Sep-2006 3 Added pocket dimensions to Figure 11.

17-Apr-2008 4

Updated ECOPACK statement. Updated Figure 10, Figure 11,

Figure 12. and Figure 14. Reformatted to current standards.

7/8

EMIF10-1K010F2

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Datasheet EMIF10-1K010F2 Datasheet (ST)

Specifications and Main Features

Frequently Asked Questions

User Manual

10-line IPAD™, EMI filter including ESD protection

EMIF10-1K010F2

Figure 1. Pin configuration (bump side)

Figure 2. Basic cell configuration

1 Characteristics

Figure 7. Capacitance versus reverse applied voltage

2 Application information

Figure 8. Aplac model

Figure 9. Aplac parametersl

3 Ordering information scheme

Figure 10. Ordering information scheme

4 Package information

Figure 11. Flip Chip package dimensions

Figure 12. Footprint recommendations Figure 13. Marking

Figure 14. Flip Chip tape and reel specification

5 Ordering information

Table 3. Ordering information

6 Revision history

Table 4. Document revision history